From 31b82f4a797dc5223d1325036efe1dccb4bf3d29 Mon Sep 17 00:00:00 2001 From: David Faust Date: Thu, 17 Sep 2020 09:45:42 -0700 Subject: [PATCH] bpf: xBPF SDIV, SMOD instructions Add gas and opcodes support for two xBPF-exclusive ALU operations: SDIV (signed division) and SMOD (signed modulo), and add tests for them in gas. cpu/ * bpf.cpu (insn-op-code-alu): Add SDIV and SMOD. (define-alu-insn-bin, daib): Take ISAs as an argument. (define-alu-instructions): Update calls to daib pmacro with ISAs; add sdiv and smod. gas/ * testsuite/gas/bpf/alu-xbpf.d: New file. * testsuite/gas/bpf/alu-xbpf.s: Likewise. * testsuite/gas/bpf/alu32-xbpf.d: Likewise. * testsuite/gas/bpf/alu32-xbpf.d: Likewise. * testuiste/gas/bpf/bpf.exp: Run new tests. opcodes/ * bpf-desc.c: Regenerate. * bpf-desc.h: Likewise. * bpf-opc.c: Likewise. * bpf-opc.h: Likewise. --- cpu/bpf.cpu | 38 ++++++------ gas/testsuite/gas/bpf/alu-xbpf.d | 17 ++++++ gas/testsuite/gas/bpf/alu-xbpf.s | 11 ++++ gas/testsuite/gas/bpf/alu32-xbpf.d | 17 ++++++ gas/testsuite/gas/bpf/alu32-xbpf.s | 11 ++++ gas/testsuite/gas/bpf/bpf.exp | 3 + opcodes/bpf-desc.c | 80 +++++++++++++++++++++++++ opcodes/bpf-desc.h | 9 +-- opcodes/bpf-opc.c | 96 ++++++++++++++++++++++++++++++ opcodes/bpf-opc.h | 8 ++- 10 files changed, 267 insertions(+), 23 deletions(-) create mode 100644 gas/testsuite/gas/bpf/alu-xbpf.d create mode 100644 gas/testsuite/gas/bpf/alu-xbpf.s create mode 100644 gas/testsuite/gas/bpf/alu32-xbpf.d create mode 100644 gas/testsuite/gas/bpf/alu32-xbpf.s diff --git a/cpu/bpf.cpu b/cpu/bpf.cpu index eb7bf5caa5e..13dde7094c8 100644 --- a/cpu/bpf.cpu +++ b/cpu/bpf.cpu @@ -249,6 +249,8 @@ (ADD #x0) (SUB #x1) (MUL #x2) (DIV #x3) (OR #x4) (AND #x5) (LSH #x6) (RSH #x7) (NEG #x8) (MOD #x9) (XOR #xa) (MOV #xb) (ARSH #xc) (END #xd) + ;; xBPF-only: signed div, signed mod + (SDIV #xe) (SMOD #xf) ;; Codes for OP_CLASS_JMP (JA #x0) (JEQ #x1) (JGT #x2) (JGE #x3) (JSET #x4) (JNE #x5) (JSGT #x6) (JSGE #x7) (CALL #x8) (EXIT #x9) @@ -420,12 +422,12 @@ ())) (define-pmacro (define-alu-insn-bin x-basename x-suffix x-op-class x-op-code - x-endian x-mode x-semop) + x-endian x-mode x-semop x-isas) (begin ;; dst = dst OP immediate (dni (.sym x-basename x-suffix "i" x-endian) (.str x-basename x-suffix " immediate") - (endian-isas x-endian) + (.splice (.unsplice x-isas)) (.str x-basename x-suffix " $dst" x-endian ",$imm32") (+ imm32 (f-offset16 0) ((.sym f-src x-endian) 0) (.sym dst x-endian) x-op-class OP_SRC_K x-op-code) @@ -434,7 +436,7 @@ ;; dst = dst OP src (dni (.sym x-basename x-suffix "r" x-endian) (.str x-basename x-suffix " register") - (endian-isas x-endian) + (.splice (.unsplice x-isas)) (.str x-basename x-suffix " $dst" x-endian ",$src" x-endian) (+ (f-imm32 0) (f-offset16 0) (.sym src x-endian) (.sym dst x-endian) x-op-class OP_SRC_X x-op-code) @@ -471,10 +473,10 @@ ;; Binary ALU instructions (all the others) ;; For ALU32: DST = (u32) DST OP (u32) SRC is correct semantics -(define-pmacro (daib x-basename x-op-code x-endian x-semop) +(define-pmacro (daib x-basename x-op-code x-endian x-semop x-isas) (begin - (define-alu-insn-bin x-basename "" OP_CLASS_ALU64 x-op-code x-endian DI x-semop) - (define-alu-insn-bin x-basename "32" OP_CLASS_ALU x-op-code x-endian USI x-semop))) + (define-alu-insn-bin x-basename "" OP_CLASS_ALU64 x-op-code x-endian DI x-semop x-isas) + (define-alu-insn-bin x-basename "32" OP_CLASS_ALU x-op-code x-endian USI x-semop x-isas))) ;; Move ALU instructions (mov) (define-pmacro (daim x-basename x-op-code x-endian) @@ -484,17 +486,19 @@ (define-pmacro (define-alu-instructions x-endian) (begin - (daib add OP_CODE_ADD x-endian add) - (daib sub OP_CODE_SUB x-endian sub) - (daib mul OP_CODE_MUL x-endian mul) - (daib div OP_CODE_DIV x-endian udiv) - (daib or OP_CODE_OR x-endian or) - (daib and OP_CODE_AND x-endian and) - (daib lsh OP_CODE_LSH x-endian sll) - (daib rsh OP_CODE_RSH x-endian srl) - (daib mod OP_CODE_MOD x-endian umod) - (daib xor OP_CODE_XOR x-endian xor) - (daib arsh OP_CODE_ARSH x-endian sra) + (daib add OP_CODE_ADD x-endian add (endian-isas x-endian)) + (daib sub OP_CODE_SUB x-endian sub (endian-isas x-endian)) + (daib mul OP_CODE_MUL x-endian mul (endian-isas x-endian)) + (daib div OP_CODE_DIV x-endian udiv (endian-isas x-endian)) + (daib or OP_CODE_OR x-endian or (endian-isas x-endian)) + (daib and OP_CODE_AND x-endian and (endian-isas x-endian)) + (daib lsh OP_CODE_LSH x-endian sll (endian-isas x-endian)) + (daib rsh OP_CODE_RSH x-endian srl (endian-isas x-endian)) + (daib mod OP_CODE_MOD x-endian umod (endian-isas x-endian)) + (daib xor OP_CODE_XOR x-endian xor (endian-isas x-endian)) + (daib arsh OP_CODE_ARSH x-endian sra (endian-isas x-endian)) + (daib sdiv OP_CODE_SDIV x-endian div ((ISA (.sym xbpf x-endian)))) + (daib smod OP_CODE_SMOD x-endian mod ((ISA (.sym xbpf x-endian)))) (daiu neg OP_CODE_NEG x-endian neg) (daim mov OP_CODE_MOV x-endian))) diff --git a/gas/testsuite/gas/bpf/alu-xbpf.d b/gas/testsuite/gas/bpf/alu-xbpf.d new file mode 100644 index 00000000000..7f97d49ddc4 --- /dev/null +++ b/gas/testsuite/gas/bpf/alu-xbpf.d @@ -0,0 +1,17 @@ +#as: --EL -mxbpf +#objdump: -dr -mxbpf +#name: xBPF ALU64 insns + +.*: +file format .*bpf.* + +Disassembly of section \.text: + +0+ <\.text>: + 0: e7 02 00 00 02 00 00 00 sdiv %r2,2 + 8: e7 03 00 00 fd ff ff ff sdiv %r3,-3 + 10: e7 04 00 00 ef be ad 7e sdiv %r4,0x7eadbeef + 18: ef 25 00 00 00 00 00 00 sdiv %r5,%r2 + 20: f7 02 00 00 03 00 00 00 smod %r2,3 + 28: f7 03 00 00 fc ff ff ff smod %r3,-4 + 30: f7 04 00 00 ef be ad 7e smod %r4,0x7eadbeef + 38: ff 25 00 00 00 00 00 00 smod %r5,%r2 diff --git a/gas/testsuite/gas/bpf/alu-xbpf.s b/gas/testsuite/gas/bpf/alu-xbpf.s new file mode 100644 index 00000000000..ebcebd79008 --- /dev/null +++ b/gas/testsuite/gas/bpf/alu-xbpf.s @@ -0,0 +1,11 @@ + # Tests for xBPF-specific alu instructions + .text + sdiv %r2, 2 + sdiv %r3, -3 + sdiv %r4, 0x7eadbeef + sdiv %r5, %r2 + + smod %r2, 3 + smod %r3, -4 + smod %r4, 0x7eadbeef + smod %r5, %r2 diff --git a/gas/testsuite/gas/bpf/alu32-xbpf.d b/gas/testsuite/gas/bpf/alu32-xbpf.d new file mode 100644 index 00000000000..03411d62d20 --- /dev/null +++ b/gas/testsuite/gas/bpf/alu32-xbpf.d @@ -0,0 +1,17 @@ +#as: --EL -mxbpf +#objdump: -dr -mxbpf +#name: xBPF ALU32 insns + +.*: +file format .*bpf.* + +Disassembly of section \.text: + +0+ <\.text>: + 0: e4 02 00 00 02 00 00 00 sdiv32 %r2,2 + 8: e4 03 00 00 fd ff ff ff sdiv32 %r3,-3 + 10: e4 04 00 00 ef be ad 7e sdiv32 %r4,0x7eadbeef + 18: ec 25 00 00 00 00 00 00 sdiv32 %r5,%r2 + 20: f4 02 00 00 03 00 00 00 smod32 %r2,3 + 28: f4 03 00 00 fc ff ff ff smod32 %r3,-4 + 30: f4 04 00 00 ef be ad 7e smod32 %r4,0x7eadbeef + 38: fc 25 00 00 00 00 00 00 smod32 %r5,%r2 diff --git a/gas/testsuite/gas/bpf/alu32-xbpf.s b/gas/testsuite/gas/bpf/alu32-xbpf.s new file mode 100644 index 00000000000..9ce5a26bb78 --- /dev/null +++ b/gas/testsuite/gas/bpf/alu32-xbpf.s @@ -0,0 +1,11 @@ + # Tests for xBPF-specific alu instructions + .text + sdiv32 %r2, 2 + sdiv32 %r3, -3 + sdiv32 %r4, 0x7eadbeef + sdiv32 %r5, %r2 + + smod32 %r2, 3 + smod32 %r3, -4 + smod32 %r4, 0x7eadbeef + smod32 %r5, %r2 diff --git a/gas/testsuite/gas/bpf/bpf.exp b/gas/testsuite/gas/bpf/bpf.exp index 242b1902ba0..f7c04f40266 100644 --- a/gas/testsuite/gas/bpf/bpf.exp +++ b/gas/testsuite/gas/bpf/bpf.exp @@ -41,4 +41,7 @@ if {[istarget bpf*-*-*]} { run_dump_test indcall-1 run_list_test indcall-bad-1 + + run_dump_test alu-xbpf + run_dump_test alu32-xbpf } diff --git a/opcodes/bpf-desc.c b/opcodes/bpf-desc.c index 6914ce98e62..adcff34e7f1 100644 --- a/opcodes/bpf-desc.c +++ b/opcodes/bpf-desc.c @@ -520,6 +520,46 @@ static const CGEN_IBASE bpf_cgen_insn_table[MAX_INSNS] = BPF_INSN_ARSH32RLE, "arsh32rle", "arsh32", 64, { 0, { { { (1<