* [PATCH 1/2] aarch64: Add DT_RELR support for ILP32 ABI
2024-06-17 15:00 [PATCH 0/2] aarch64: DT_RELR for ILP32 Szabolcs Nagy
@ 2024-06-17 15:00 ` Szabolcs Nagy
2024-06-17 15:01 ` [PATCH 2/2] aarch64: Add DT_RELR tests " Szabolcs Nagy
2024-06-24 13:57 ` [PATCH 0/2] aarch64: DT_RELR for ILP32 Nick Clifton
2 siblings, 0 replies; 4+ messages in thread
From: Szabolcs Nagy @ 2024-06-17 15:00 UTC (permalink / raw)
To: binutils
Extend the 64bit DT_RELR support to work on 32bit ELF too. For this
only a few changes were needed in the sizing and creation of the
relr relocations.
---
bfd/elfnn-aarch64.c | 37 +++++++++++++++++++--------------
ld/emulparams/aarch64elf32.sh | 2 ++
ld/emulparams/aarch64linux32.sh | 2 ++
3 files changed, 25 insertions(+), 16 deletions(-)
diff --git a/bfd/elfnn-aarch64.c b/bfd/elfnn-aarch64.c
index 2221de0a480..000564672df 100644
--- a/bfd/elfnn-aarch64.c
+++ b/bfd/elfnn-aarch64.c
@@ -9451,6 +9451,11 @@ sort_relr (struct bfd_link_info *info,
return true;
}
+/* Size of a relr entry and a relocated location. */
+#define RELR_SZ (ARCH_SIZE / 8)
+/* Number of consecutive locations a relr bitmap entry references. */
+#define RELR_N (ARCH_SIZE - 1)
+
/* Size .relr.dyn whenever the layout changes, the number of packed
relocs are unchanged but the packed representation can. */
@@ -9473,19 +9478,19 @@ elfNN_aarch64_size_relative_relocs (struct bfd_link_info *info,
{
bfd_vma base = addr[i];
i++;
- srelrdyn->size += 8;
- base += 8;
+ srelrdyn->size += RELR_SZ;
+ base += RELR_SZ;
for (;;)
{
bfd_size_type start_i = i;
while (i < htab->relr_count
- && addr[i] - base < 63 * 8
- && (addr[i] - base) % 8 == 0)
+ && addr[i] - base < RELR_N * RELR_SZ
+ && (addr[i] - base) % RELR_SZ == 0)
i++;
if (i == start_i)
break;
- srelrdyn->size += 8;
- base += 63 * 8;
+ srelrdyn->size += RELR_SZ;
+ base += RELR_N * RELR_SZ;
}
}
if (srelrdyn->size != oldsize)
@@ -9522,25 +9527,25 @@ elfNN_aarch64_finish_relative_relocs (struct bfd_link_info *info)
{
bfd_vma base = addr[i];
i++;
- bfd_put_64 (dynobj, base, loc);
- loc += 8;
- base += 8;
+ bfd_put_NN (dynobj, base, loc);
+ loc += RELR_SZ;
+ base += RELR_SZ;
for (;;)
{
bfd_vma bits = 0;
while (i < htab->relr_count)
{
bfd_vma delta = addr[i] - base;
- if (delta >= 63 * 8 || delta % 8 != 0)
+ if (delta >= RELR_N * RELR_SZ || delta % RELR_SZ != 0)
break;
- bits |= (bfd_vma) 1 << (delta / 8);
+ bits |= (bfd_vma) 1 << (delta / RELR_SZ);
i++;
}
if (bits == 0)
break;
- bfd_put_64 (dynobj, (bits << 1) | 1, loc);
- loc += 8;
- base += 63 * 8;
+ bfd_put_NN (dynobj, (bits << 1) | 1, loc);
+ loc += RELR_SZ;
+ base += RELR_N * RELR_SZ;
}
}
free (addr);
@@ -9548,8 +9553,8 @@ elfNN_aarch64_finish_relative_relocs (struct bfd_link_info *info)
/* Pad any excess with 1's, a do-nothing encoding. */
while (loc < srelrdyn->contents + srelrdyn->size)
{
- bfd_put_64 (dynobj, 1, loc);
- loc += 8;
+ bfd_put_NN (dynobj, 1, loc);
+ loc += RELR_SZ;
}
return true;
}
diff --git a/ld/emulparams/aarch64elf32.sh b/ld/emulparams/aarch64elf32.sh
index 5a08d9e29f1..45bf31a179a 100644
--- a/ld/emulparams/aarch64elf32.sh
+++ b/ld/emulparams/aarch64elf32.sh
@@ -1,3 +1,5 @@
+source_sh ${srcdir}/emulparams/dt-relr.sh
+
ARCH="aarch64:ilp32"
MACHINE=
NOP=0x1f2003d5
diff --git a/ld/emulparams/aarch64linux32.sh b/ld/emulparams/aarch64linux32.sh
index 3e75d1492e6..3292c7ca32a 100644
--- a/ld/emulparams/aarch64linux32.sh
+++ b/ld/emulparams/aarch64linux32.sh
@@ -1,3 +1,5 @@
+source_sh ${srcdir}/emulparams/dt-relr.sh
+
ARCH="aarch64:ilp32"
MACHINE=
NOP=0x1f2003d5
--
2.25.1
^ permalink raw reply [flat|nested] 4+ messages in thread* [PATCH 2/2] aarch64: Add DT_RELR tests for ILP32 ABI
2024-06-17 15:00 [PATCH 0/2] aarch64: DT_RELR for ILP32 Szabolcs Nagy
2024-06-17 15:00 ` [PATCH 1/2] aarch64: Add DT_RELR support for ILP32 ABI Szabolcs Nagy
@ 2024-06-17 15:01 ` Szabolcs Nagy
2024-06-24 13:57 ` [PATCH 0/2] aarch64: DT_RELR for ILP32 Nick Clifton
2 siblings, 0 replies; 4+ messages in thread
From: Szabolcs Nagy @ 2024-06-17 15:01 UTC (permalink / raw)
To: binutils
---
binutils/testsuite/lib/binutils-common.exp | 2 +-
ld/testsuite/ld-aarch64/aarch64-elf.exp | 4 +
ld/testsuite/ld-aarch64/relr-align-ilp32.d | 23 ++++
ld/testsuite/ld-aarch64/relr-align-ilp32.s | 106 ++++++++++++++++++
ld/testsuite/ld-aarch64/relr-got-pie-ilp32.d | 16 +++
.../ld-aarch64/relr-got-shared-ilp32.d | 16 +++
6 files changed, 166 insertions(+), 1 deletion(-)
create mode 100644 ld/testsuite/ld-aarch64/relr-align-ilp32.d
create mode 100644 ld/testsuite/ld-aarch64/relr-align-ilp32.s
create mode 100644 ld/testsuite/ld-aarch64/relr-got-pie-ilp32.d
create mode 100644 ld/testsuite/ld-aarch64/relr-got-shared-ilp32.d
diff --git a/binutils/testsuite/lib/binutils-common.exp b/binutils/testsuite/lib/binutils-common.exp
index ebc4c735855..bf291d731e2 100644
--- a/binutils/testsuite/lib/binutils-common.exp
+++ b/binutils/testsuite/lib/binutils-common.exp
@@ -473,7 +473,7 @@ proc supports_dt_relr {} {
if { ([istarget x86_64-*-*]
|| [istarget i?86-*-*]
|| [istarget powerpc64*-*-*]
- || ([istarget aarch64*-*-*] && ![istarget *-*-*ilp32]))
+ || [istarget aarch64*-*-*])
&& ([istarget *-*-linux*]
|| [istarget *-*-gnu*]) } {
return 1
diff --git a/ld/testsuite/ld-aarch64/aarch64-elf.exp b/ld/testsuite/ld-aarch64/aarch64-elf.exp
index dc5eed50bfd..c7d97f3ced9 100644
--- a/ld/testsuite/ld-aarch64/aarch64-elf.exp
+++ b/ld/testsuite/ld-aarch64/aarch64-elf.exp
@@ -478,6 +478,10 @@ if { [supports_dt_relr] } {
run_dump_test_lp64 "relr-text-shared"
run_dump_test_lp64 "relr-discard-pie"
run_dump_test_lp64 "relr-discard-shared"
+
+ run_dump_test "relr-align-ilp32"
+ run_dump_test "relr-got-pie-ilp32"
+ run_dump_test "relr-got-shared-ilp32"
}
if { ![skip_sframe_tests] } {
diff --git a/ld/testsuite/ld-aarch64/relr-align-ilp32.d b/ld/testsuite/ld-aarch64/relr-align-ilp32.d
new file mode 100644
index 00000000000..d2a5982a3f3
--- /dev/null
+++ b/ld/testsuite/ld-aarch64/relr-align-ilp32.d
@@ -0,0 +1,23 @@
+#source: relr-align-ilp32.s
+#as: -mabi=ilp32
+#ld: -m [aarch64_choose_ilp32_emul] -shared -z pack-relative-relocs -T relocs-ilp32.ld
+#readelf: -rW
+
+Relocation section '\.rela\.dyn' at offset 0x1.* contains 3 entries:
+ Offset Info Type Sym. Value Symbol's Name \+ Addend
+12340009 000000b7 R_AARCH64_P32_RELATIVE 10000
+1234000d 000000b7 R_AARCH64_P32_RELATIVE 10000
+12340025 000000b7 R_AARCH64_P32_RELATIVE 10000
+
+Relocation section '\.relr\.dyn' at offset 0x1.* contains 10 entries which relocate 10 locations:
+Index: Entry Address Symbolic Address
+0000: 12340000 12340000 double_0
+0001: 00000003 12340004 double_0 \+ 0x4
+0002: 12340012 12340012 double_2
+0003: 00000003 12340016 double_2 \+ 0x4
+0004: 12340020 12340020 single_0
+0005: 1234002a 1234002a single_2
+0006: 12340034 12340034 big
+0007: 123400b4 123400b4 big \+ 0x80
+0008: 80000001 12340130 big \+ 0xfc
+0009: 00000003 12340134 big \+ 0x100
diff --git a/ld/testsuite/ld-aarch64/relr-align-ilp32.s b/ld/testsuite/ld-aarch64/relr-align-ilp32.s
new file mode 100644
index 00000000000..7e2e084d7cb
--- /dev/null
+++ b/ld/testsuite/ld-aarch64/relr-align-ilp32.s
@@ -0,0 +1,106 @@
+// Test DT_RELR with differently aligned relative relocs.
+
+.text
+.global _start
+_start:
+foo:
+
+.data
+.p2align 3
+double_0:
+.word foo
+.word foo
+.byte 0
+double_1:
+.word foo
+.word foo
+.byte 0
+double_2:
+.word foo
+.word foo
+.byte 0
+.byte 0
+.byte 0
+.byte 0
+.byte 0
+.byte 0
+single_0:
+.word foo
+.byte 0
+single_1:
+.word foo
+.byte 0
+single_2:
+.word foo
+.byte 0
+.byte 0
+.byte 0
+.byte 0
+.byte 0
+.byte 0
+big:
+.word foo
+.word 1
+.word 2
+.word 3
+.word 4
+.word 5
+.word 6
+.word 7
+.word 8
+.word 9
+.word 10
+.word 11
+.word 12
+.word 13
+.word 14
+.word 15
+.word 16
+.word 17
+.word 18
+.word 19
+.word 20
+.word 21
+.word 22
+.word 23
+.word 24
+.word 25
+.word 26
+.word 27
+.word 28
+.word 29
+.word 30
+.word 31
+.word foo + 32
+.word 33
+.word 34
+.word 35
+.word 36
+.word 37
+.word 38
+.word 39
+.word 40
+.word 41
+.word 42
+.word 43
+.word 44
+.word 45
+.word 46
+.word 47
+.word 48
+.word 49
+.word 50
+.word 51
+.word 52
+.word 53
+.word 54
+.word 55
+.word 56
+.word 57
+.word 58
+.word 59
+.word 60
+.word 61
+.word 62
+.word foo + 63
+.word foo + 64
diff --git a/ld/testsuite/ld-aarch64/relr-got-pie-ilp32.d b/ld/testsuite/ld-aarch64/relr-got-pie-ilp32.d
new file mode 100644
index 00000000000..04cb52ef3a2
--- /dev/null
+++ b/ld/testsuite/ld-aarch64/relr-got-pie-ilp32.d
@@ -0,0 +1,16 @@
+#source: relr-got.s
+#as: -mabi=ilp32
+#ld: -m [aarch64_choose_ilp32_emul] -pie -z pack-relative-relocs -T relocs-ilp32.ld
+#readelf: -rW
+
+Relocation section '\.rela\.dyn' at offset 0x1.* contains 2 entries:
+ Offset Info Type Sym\. Value Symbol's Name \+ Addend
+00000000 .* R_AARCH64_NONE 0
+00020018 .* R_AARCH64_P32_GLOB_DAT 00000000 sym_weak_undef \+ 0
+
+Relocation section '\.relr\.dyn' at offset 0x1.* contains 2 entries which relocate 4 locations:
+Index: Entry Address Symbolic Address
+0000: 00020004 00020004 _GLOBAL_OFFSET_TABLE_ \+ 0x4
+0001: 0000000f 00020008 _GLOBAL_OFFSET_TABLE_ \+ 0x8
+ 0002000c _GLOBAL_OFFSET_TABLE_ \+ 0xc
+ 00020010 _GLOBAL_OFFSET_TABLE_ \+ 0x10
diff --git a/ld/testsuite/ld-aarch64/relr-got-shared-ilp32.d b/ld/testsuite/ld-aarch64/relr-got-shared-ilp32.d
new file mode 100644
index 00000000000..b835a0c792e
--- /dev/null
+++ b/ld/testsuite/ld-aarch64/relr-got-shared-ilp32.d
@@ -0,0 +1,16 @@
+#source: relr-got.s
+#as: -mabi=ilp32
+#ld: -m [aarch64_choose_ilp32_emul] -shared -z pack-relative-relocs -T relocs-ilp32.ld
+#readelf: -rW
+
+Relocation section '\.rela\.dyn' at offset 0x1.* contains 3 entries:
+ Offset Info Type Sym. Value Symbol's Name \+ Addend
+00020010 .* R_AARCH64_P32_GLOB_DAT 00010038 sym_global \+ 0
+00020014 .* R_AARCH64_P32_GLOB_DAT 0000002a sym_global_abs \+ 0
+00020018 .* R_AARCH64_P32_GLOB_DAT 00000000 sym_weak_undef \+ 0
+
+Relocation section '\.relr\.dyn' at offset 0x1.* contains 2 entries which relocate 3 locations:
+Index: Entry Address Symbolic Address
+0000: 00020004 00020004 _GLOBAL_OFFSET_TABLE_ \+ 0x4
+0001: 00000007 00020008 _GLOBAL_OFFSET_TABLE_ \+ 0x8
+ 0002000c _GLOBAL_OFFSET_TABLE_ \+ 0xc
--
2.25.1
^ permalink raw reply [flat|nested] 4+ messages in thread