From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-sender-0.a4lg.com (mail-sender.a4lg.com [153.120.152.154]) by sourceware.org (Postfix) with ESMTPS id 0EAC13858404 for ; Thu, 16 Dec 2021 11:07:10 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 0EAC13858404 Received: by mail-sender-0.a4lg.com (Postfix) with ESMTPSA id 311BA30008B; Thu, 16 Dec 2021 11:07:07 +0000 (UTC) From: Tsukasa OI To: Tsukasa OI Cc: binutils@sourceware.org Subject: [PATCH 2/5] RISC-V: Cache management instructions Date: Thu, 16 Dec 2021 20:04:55 +0900 Message-Id: In-Reply-To: References: Mime-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-4.0 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, GIT_PATCH_0, SPF_HELO_NONE, SPF_PASS, TXREP, UNWANTED_LANGUAGE_BODY autolearn=ham autolearn_force=no version=3.4.4 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on server2.sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 16 Dec 2021 11:07:11 -0000 This commit adds Zicbom/Zicboz instructions. bfd/ChangeLog: * elfxx-riscv.c (riscv_multi_subset_supports): Add probing for new instruction classes. include/ChangeLog: * opcode/riscv-opc.h (MATCH_CBO_CLEAN, MASK_CBO_CLEAN, MATCH_CBO_FLUSH, MASK_CBO_FLUSH, MATCH_CBO_INVAL, MASK_CBO_INVAL, MATCH_CBO_ZERO, MASK_CBO_ZERO): New macros. * opcode/riscv.h (enum riscv_insn_class): Add new instruction classes INSN_CLASS_ZICBOM and INSN_CLASS_ZICBOZ. opcodes/ChangeLog: * riscv-opc.c (riscv_opcodes): Add cache-block management instructions. --- bfd/elfxx-riscv.c | 4 ++++ include/opcode/riscv-opc.h | 8 ++++++++ include/opcode/riscv.h | 2 ++ opcodes/riscv-opc.c | 6 ++++++ 4 files changed, 20 insertions(+) diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c index 14089e8d7d4..a0a043cb5a8 100644 --- a/bfd/elfxx-riscv.c +++ b/bfd/elfxx-riscv.c @@ -2332,6 +2332,10 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps, { case INSN_CLASS_I: return riscv_subset_supports (rps, "i"); + case INSN_CLASS_ZICBOM: + return riscv_subset_supports (rps, "zicbom"); + case INSN_CLASS_ZICBOZ: + return riscv_subset_supports (rps, "zicboz"); case INSN_CLASS_ZICSR: return riscv_subset_supports (rps, "zicsr"); case INSN_CLASS_ZIFENCEI: diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h index a6ece366fa4..c804c1afd95 100644 --- a/include/opcode/riscv-opc.h +++ b/include/opcode/riscv-opc.h @@ -1998,6 +1998,14 @@ #define MASK_HINVAL_VVMA 0xfe007fff #define MATCH_HINVAL_GVMA 0x66000073 #define MASK_HINVAL_GVMA 0xfe007fff +#define MATCH_CBO_CLEAN 0x10200f +#define MASK_CBO_CLEAN 0xfff07fff +#define MATCH_CBO_FLUSH 0x20200f +#define MASK_CBO_FLUSH 0xfff07fff +#define MATCH_CBO_INVAL 0x200f +#define MASK_CBO_INVAL 0xfff07fff +#define MATCH_CBO_ZERO 0x40200f +#define MASK_CBO_ZERO 0xfff07fff /* Privileged CSR addresses. */ #define CSR_USTATUS 0x0 #define CSR_UIE 0x4 diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h index cbc90b00008..37f60a8b61c 100644 --- a/include/opcode/riscv.h +++ b/include/opcode/riscv.h @@ -388,6 +388,8 @@ enum riscv_insn_class INSN_CLASS_V, INSN_CLASS_ZVEF, INSN_CLASS_SVINVAL, + INSN_CLASS_ZICBOM, + INSN_CLASS_ZICBOZ, }; /* This structure holds information for a particular instruction. */ diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c index f220006fc93..fc2a1107784 100644 --- a/opcodes/riscv-opc.c +++ b/opcodes/riscv-opc.c @@ -849,6 +849,12 @@ const struct riscv_opcode riscv_opcodes[] = {"sfence.vma", 0, INSN_CLASS_I, "s,t", MATCH_SFENCE_VMA, MASK_SFENCE_VMA, match_opcode, 0 }, {"wfi", 0, INSN_CLASS_I, "", MATCH_WFI, MASK_WFI, match_opcode, 0 }, +/* Zicbom and Zicboz instructions. */ +{"cbo.clean", 0, INSN_CLASS_ZICBOM, "s", MATCH_CBO_CLEAN, MASK_CBO_CLEAN, match_opcode, 0 }, +{"cbo.flush", 0, INSN_CLASS_ZICBOM, "s", MATCH_CBO_FLUSH, MASK_CBO_FLUSH, match_opcode, 0 }, +{"cbo.inval", 0, INSN_CLASS_ZICBOM, "s", MATCH_CBO_INVAL, MASK_CBO_INVAL, match_opcode, 0 }, +{"cbo.zero", 0, INSN_CLASS_ZICBOZ, "s", MATCH_CBO_ZERO, MASK_CBO_ZERO, match_opcode, 0 }, + /* Zbb or zbkb instructions. */ {"clz", 0, INSN_CLASS_ZBB, "d,s", MATCH_CLZ, MASK_CLZ, match_opcode, 0 }, {"ctz", 0, INSN_CLASS_ZBB, "d,s", MATCH_CTZ, MASK_CTZ, match_opcode, 0 }, -- 2.32.0