From: Jan Beulich <jbeulich@suse.com>
To: Binutils <binutils@sourceware.org>
Cc: "H.J. Lu" <hjl.tools@gmail.com>
Subject: [PATCH v7 6/7] x86: drop (now) stray IsString
Date: Fri, 2 Dec 2022 11:21:02 +0100 [thread overview]
Message-ID: <ac7e5911-4c5e-27c3-b0e5-cd3dcfa67155@suse.com> (raw)
In-Reply-To: <dc39887b-fc6e-2827-e0b1-e99949e08796@suse.com>
The need for them on the operand-less string insns has gone away with
the removal of maybe_adjust_templates() and associated logic. Since
i386_index_check() needs adjustment then anyway, take the opportunity
and also simplify it, possible again as a result of said removal (plus
the opcode template adjustments done here).
---
v7: PadLock parts split off.
v4: New.
--- a/gas/config/tc-i386.c
+++ b/gas/config/tc-i386.c
@@ -11373,11 +11373,9 @@ i386_index_check (const char *operand_st
{
const char *kind = "base/index";
enum flag_code addr_mode = i386_addressing_mode ();
- const insn_template *t = current_templates->start;
+ const insn_template *t = current_templates->end - 1;
- if (t->opcode_modifier.isstring
- && (current_templates->end[-1].opcode_modifier.isstring
- || i.mem_operands))
+ if (t->opcode_modifier.isstring)
{
/* Memory operands of string insns are special in that they only allow
a single register (rDI, rSI, or rBX) as their memory address. */
@@ -11394,14 +11392,12 @@ i386_index_check (const char *operand_st
if (t->opcode_modifier.prefixok == PrefixRep)
{
- int es_op = current_templates->end[-1].opcode_modifier.isstring
- - IS_STRING_ES_OP0;
+ int es_op = t->opcode_modifier.isstring - IS_STRING_ES_OP0;
int op = 0;
- if (!current_templates->end[-1].operand_types[0].bitfield.baseindex
+ if (!t->operand_types[0].bitfield.baseindex
|| ((!i.mem_operands != !intel_syntax)
- && current_templates->end[-1].operand_types[1]
- .bitfield.baseindex))
+ && t->operand_types[1].bitfield.baseindex))
op = 1;
expected_reg
= (const reg_entry *) str_hash_find (reg_hash,
@@ -11444,6 +11440,8 @@ i386_index_check (const char *operand_st
}
else
{
+ t = current_templates->start;
+
if (addr_mode != CODE_16BIT)
{
/* 32-bit/64-bit checks. */
--- a/opcodes/i386-opc.tbl
+++ b/opcodes/i386-opc.tbl
@@ -490,37 +490,37 @@ loopne, 0xe0, None, Cpu64, JumpByte|No_b
set<cc>, 0xf9<cc:opc>, 0, Cpu386, Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf, { Reg8|Byte|Unspecified|BaseIndex }
// String manipulation.
-cmps, 0xa6, None, 0, W|No_sSuf|IsString|RepPrefixOk, {}
+cmps, 0xa6, None, 0, W|No_sSuf|RepPrefixOk, {}
cmps, 0xa6, None, 0, W|No_sSuf|IsStringEsOp0|RepPrefixOk, { Byte|Word|Dword|Qword|Unspecified|BaseIndex, Byte|Word|Dword|Qword|Unspecified|BaseIndex }
-scmp, 0xa6, None, 0, W|No_sSuf|IsString|RepPrefixOk, {}
+scmp, 0xa6, None, 0, W|No_sSuf|RepPrefixOk, {}
scmp, 0xa6, None, 0, W|No_sSuf|IsStringEsOp0|RepPrefixOk, { Byte|Word|Dword|Qword|Unspecified|BaseIndex, Byte|Word|Dword|Qword|Unspecified|BaseIndex }
-ins, 0x6c, None, Cpu186, W|No_sSuf|No_qSuf|IsString|RepPrefixOk, {}
+ins, 0x6c, None, Cpu186, W|No_sSuf|No_qSuf|RepPrefixOk, {}
ins, 0x6c, None, Cpu186, W|No_sSuf|No_qSuf|IsStringEsOp1|RepPrefixOk, { InOutPortReg, Byte|Word|Dword|Unspecified|BaseIndex }
-outs, 0x6e, None, Cpu186, W|No_sSuf|No_qSuf|IsString|RepPrefixOk, {}
+outs, 0x6e, None, Cpu186, W|No_sSuf|No_qSuf|RepPrefixOk, {}
outs, 0x6e, None, Cpu186, W|No_sSuf|No_qSuf|IsString|RepPrefixOk, { Byte|Word|Dword|Unspecified|BaseIndex, InOutPortReg }
-lods, 0xac, None, 0, W|No_sSuf|IsString|RepPrefixOk, {}
+lods, 0xac, None, 0, W|No_sSuf|RepPrefixOk, {}
lods, 0xac, None, 0, W|No_sSuf|IsString|RepPrefixOk, { Byte|Word|Dword|Qword|Unspecified|BaseIndex }
lods, 0xac, None, 0, W|No_sSuf|IsString|RepPrefixOk, { Byte|Word|Dword|Qword|Unspecified|BaseIndex, Acc|Byte|Word|Dword|Qword }
-slod, 0xac, None, 0, W|No_sSuf|IsString|RepPrefixOk, {}
+slod, 0xac, None, 0, W|No_sSuf|RepPrefixOk, {}
slod, 0xac, None, 0, W|No_sSuf|IsString|RepPrefixOk, { Byte|Word|Dword|Qword|Unspecified|BaseIndex }
slod, 0xac, None, 0, W|No_sSuf|IsString|RepPrefixOk, { Byte|Word|Dword|Qword|Unspecified|BaseIndex, Acc|Byte|Word|Dword|Qword }
-movs, 0xa4, None, 0, W|No_sSuf|IsString|RepPrefixOk, {}
+movs, 0xa4, None, 0, W|No_sSuf|RepPrefixOk, {}
movs, 0xa4, None, 0, W|No_sSuf|IsStringEsOp1|RepPrefixOk, { Byte|Word|Dword|Qword|Unspecified|BaseIndex, Byte|Word|Dword|Qword|Unspecified|BaseIndex }
-smov, 0xa4, None, 0, W|No_sSuf|IsString|RepPrefixOk, {}
+smov, 0xa4, None, 0, W|No_sSuf|RepPrefixOk, {}
smov, 0xa4, None, 0, W|No_sSuf|IsStringEsOp1|RepPrefixOk, { Byte|Word|Dword|Qword|Unspecified|BaseIndex, Byte|Word|Dword|Qword|Unspecified|BaseIndex }
-scas, 0xae, None, 0, W|No_sSuf|IsString|RepPrefixOk, {}
+scas, 0xae, None, 0, W|No_sSuf|RepPrefixOk, {}
scas, 0xae, None, 0, W|No_sSuf|IsStringEsOp0|RepPrefixOk, { Byte|Word|Dword|Qword|Unspecified|BaseIndex }
scas, 0xae, None, 0, W|No_sSuf|IsStringEsOp0|RepPrefixOk, { Byte|Word|Dword|Qword|Unspecified|BaseIndex, Acc|Byte|Word|Dword|Qword }
-ssca, 0xae, None, 0, W|No_sSuf|IsString|RepPrefixOk, {}
+ssca, 0xae, None, 0, W|No_sSuf|RepPrefixOk, {}
ssca, 0xae, None, 0, W|No_sSuf|IsStringEsOp0|RepPrefixOk, { Byte|Word|Dword|Qword|Unspecified|BaseIndex }
ssca, 0xae, None, 0, W|No_sSuf|IsStringEsOp0|RepPrefixOk, { Byte|Word|Dword|Qword|Unspecified|BaseIndex, Acc|Byte|Word|Dword|Qword }
-stos, 0xaa, None, 0, W|No_sSuf|IsString|RepPrefixOk, {}
+stos, 0xaa, None, 0, W|No_sSuf|RepPrefixOk, {}
stos, 0xaa, None, 0, W|No_sSuf|IsStringEsOp0|RepPrefixOk, { Byte|Word|Dword|Qword|Unspecified|BaseIndex }
stos, 0xaa, None, 0, W|No_sSuf|IsStringEsOp1|RepPrefixOk, { Acc|Byte|Word|Dword|Qword, Byte|Word|Dword|Qword|Unspecified|BaseIndex }
-ssto, 0xaa, None, 0, W|No_sSuf|IsString|RepPrefixOk, {}
+ssto, 0xaa, None, 0, W|No_sSuf|RepPrefixOk, {}
ssto, 0xaa, None, 0, W|No_sSuf|IsStringEsOp0|RepPrefixOk, { Byte|Word|Dword|Qword|Unspecified|BaseIndex }
ssto, 0xaa, None, 0, W|No_sSuf|IsStringEsOp1|RepPrefixOk, { Acc|Byte|Word|Dword|Qword, Byte|Word|Dword|Qword|Unspecified|BaseIndex }
-xlat, 0xd7, None, 0, No_wSuf|No_lSuf|No_sSuf|No_qSuf|IsString, {}
+xlat, 0xd7, None, 0, No_wSuf|No_lSuf|No_sSuf|No_qSuf, {}
xlat, 0xd7, None, 0, No_wSuf|No_lSuf|No_sSuf|No_qSuf|IsString, { Byte|Unspecified|BaseIndex }
// Bit manipulation.
next prev parent reply other threads:[~2022-12-02 10:21 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-12-02 10:13 [PATCH v7 0/7] x86: suffix handling changes Jan Beulich
2022-12-02 10:18 ` [PATCH v7 1/7] x86: constify parse_insn()'s input Jan Beulich
2022-12-02 10:18 ` [PATCH v7 2/7] x86: re-work insn/suffix recognition Jan Beulich
2022-12-02 10:19 ` [PATCH v7 3/7] ix86: don't recognize/derive Q suffix in the common case Jan Beulich
2022-12-02 10:20 ` [PATCH v7 4/7] x86-64: allow HLE store of accumulator to absolute 32-bit address Jan Beulich
2022-12-02 10:20 ` [PATCH v7 5/7] x86: move bad-use-of-TLS-reloc check Jan Beulich
2022-12-02 10:21 ` Jan Beulich [this message]
2022-12-02 10:21 ` [PATCH v7 7/7] x86: further re-work insn/suffix recognition to also cover MOVSX Jan Beulich
2022-12-09 10:56 ` [PATCH v7 0/7] x86: suffix handling changes Jan Beulich
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