* [PATCH v1 1/7] aarch64: Add support for FEAT_SME_F16F16 feature.
2024-07-12 16:35 [PATCH v1 0/7][Binutils] aarch64: Add support for FEAT_SME_F16F16 feature and instructions Srinath Parvathaneni
@ 2024-07-12 16:35 ` Srinath Parvathaneni
2024-07-12 16:35 ` [PATCH v1 2/7] aarch64: Add support for FEAT_SME_F16F16 fmops and fmopa instructions Srinath Parvathaneni
` (6 subsequent siblings)
7 siblings, 0 replies; 12+ messages in thread
From: Srinath Parvathaneni @ 2024-07-12 16:35 UTC (permalink / raw)
To: binutils; +Cc: richard.earnshaw, nickc, Srinath Parvathaneni
[-- Attachment #1: Type: text/plain, Size: 1362 bytes --]
This patch adds support for FEAT_SME_F16F16 feature (Non-widening
half-precision FP16 to FP16 arithmetic for SME2), which is enabled
using command line flags +sme-f16f16 to -march (which enables both
FEAT_SME2 and FEAT_SME_F16F16).
There are couple of instructions (fadd and fsub variants) which should
be allowed by the assembler on either passing +sme-f16f16 or +sme-f8f16.
Those instructions are already supported in the current assembler, this
patch adds tests for those instructions as well.
---
gas/config/tc-aarch64.c | 3 +-
gas/doc/c-aarch64.texi | 2 ++
gas/testsuite/gas/aarch64/sme-f16f16-1-bad.d | 4 +++
gas/testsuite/gas/aarch64/sme-f16f16-1-bad.l | 33 +++++++++++++++++
gas/testsuite/gas/aarch64/sme-f16f16-1-bad.s | 21 +++++++++++
gas/testsuite/gas/aarch64/sme-f16f16-1.d | 38 ++++++++++++++++++++
gas/testsuite/gas/aarch64/sme-f16f16-1.s | 33 +++++++++++++++++
include/opcode/aarch64.h | 2 ++
8 files changed, 135 insertions(+), 1 deletion(-)
create mode 100644 gas/testsuite/gas/aarch64/sme-f16f16-1-bad.d
create mode 100644 gas/testsuite/gas/aarch64/sme-f16f16-1-bad.l
create mode 100644 gas/testsuite/gas/aarch64/sme-f16f16-1-bad.s
create mode 100644 gas/testsuite/gas/aarch64/sme-f16f16-1.d
create mode 100644 gas/testsuite/gas/aarch64/sme-f16f16-1.s
[-- Warning: decoded text below may be mangled, UTF-8 assumed --]
[-- Attachment #2: v1-0001-aarch64-Add-support-for-FEAT_SME_F16F16-feature.patch --]
[-- Type: text/x-patch; name="v1-0001-aarch64-Add-support-for-FEAT_SME_F16F16-feature.patch", Size: 9286 bytes --]
diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c
index ceb0f34c885..929ee3d0245 100644
--- a/gas/config/tc-aarch64.c
+++ b/gas/config/tc-aarch64.c
@@ -10731,6 +10731,7 @@ static const struct aarch64_option_cpu_value_table aarch64_features[] = {
AARCH64_FEATURES (2, FP8, SME2)},
{"sme-f8f16", AARCH64_FEATURE (SME_F8F16),
AARCH64_FEATURE (SME_F8F32)},
+ {"sme-f16f16", AARCH64_FEATURE (SME_F16F16), AARCH64_FEATURE (SME2)},
{NULL, AARCH64_NO_FEATURES, AARCH64_NO_FEATURES},
};
@@ -10749,7 +10750,7 @@ static const struct aarch64_virtual_dependency_table aarch64_dependencies[] = {
{AARCH64_FEATURE (SSVE_FP8DOT4), AARCH64_FEATURE (FP8DOT4_SVE)},
{AARCH64_FEATURES (2, FP8DOT2, SVE2), AARCH64_FEATURE (FP8DOT2_SVE)},
{AARCH64_FEATURE (SSVE_FP8DOT2), AARCH64_FEATURE (FP8DOT2_SVE)},
- /* TODO: Add SME_F16F16->SME_F16F16_F8F16 when SME_F16F16 is added. */
+ {AARCH64_FEATURE (SME_F16F16), AARCH64_FEATURE (SME_F16F16_F8F16)},
{AARCH64_FEATURE (SME_F8F16), AARCH64_FEATURE (SME_F16F16_F8F16)},
};
diff --git a/gas/doc/c-aarch64.texi b/gas/doc/c-aarch64.texi
index 8e46038a787..010bf032919 100644
--- a/gas/doc/c-aarch64.texi
+++ b/gas/doc/c-aarch64.texi
@@ -315,6 +315,8 @@ automatically cause those extensions to be disabled.
@tab Enable @code{wfet} and @code{wfit} instructions.
@item @code{xs} @tab
@tab Enable the XS memory attribute extension.
+@item @code{sme-f16f16} @tab
+ @tab Enable the SME2 F16F16 Extension.
@end multitable
@multitable @columnfractions .20 .80
diff --git a/gas/testsuite/gas/aarch64/sme-f16f16-1-bad.d b/gas/testsuite/gas/aarch64/sme-f16f16-1-bad.d
new file mode 100644
index 00000000000..2d69c3add1e
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sme-f16f16-1-bad.d
@@ -0,0 +1,4 @@
+#name: Test of invalid FEAT_SME_F16F16 fadd and fsub instructions.
+#as: -march=armv9.4-a+sme-f16f16
+#source: sme-f16f16-1-bad.s
+#error_output: sme-f16f16-1-bad.l
diff --git a/gas/testsuite/gas/aarch64/sme-f16f16-1-bad.l b/gas/testsuite/gas/aarch64/sme-f16f16-1-bad.l
new file mode 100644
index 00000000000..18a9c183ccd
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sme-f16f16-1-bad.l
@@ -0,0 +1,33 @@
+.*: Assembler messages:
+.*: Error: operand mismatch -- `fadd za.s\[w8,0,vgx2\],{z0.h-z1.h}'
+.*: Info: did you mean this\?
+.*: Info: fadd za.s\[w8, 0, vgx2\], {z0.s-z1.s}
+.*: Info: other valid variant\(s\):
+.*: Info: fadd za.d\[w8, 0, vgx2\], {z0.d-z1.d}
+.*: Error: too many registers in vector register list at operand 2 -- `fadd za.h\[w13,0,vgx2\],{z1.h-z0.h}'
+.*: Error: invalid vector group size at operand 1 -- `fadd za.h\[w8,11,vgx3\],{z0.h-z1.h}'
+.*: Error: too many registers in vector register list at operand 2 -- `fadd za.h\[w8,0,vgx2\],{z0.h-z4.h}'
+.*: Error: operand mismatch -- `fadd za.s\[w8,0,vgx4\],{z0.h-z3.h}'
+.*: Info: did you mean this\?
+.*: Info: fadd za.s\[w8, 0, vgx4\], {z0.s-z3.s}
+.*: Info: other valid variant\(s\):
+.*: Info: fadd za.d\[w8, 0, vgx4\], {z0.d-z3.d}
+.*: Error: too many registers in vector register list at operand 2 -- `fadd za.h\[w14,0,vgx4\],{z10.h-z3.h}'
+.*: Error: invalid vector group size at operand 1 -- `fadd za.h\[w8,15,vgx1\],{z3.h-z2.h}'
+.*: Error: expected a list of 4 registers at operand 2 -- `fadd za.h\[w8,0,vgx4\],{z30.h-z31.h}'
+.*: Error: operand mismatch -- `fsub za.s\[w8,0,vgx2\],{z0.h-z1.h}'
+.*: Info: did you mean this\?
+.*: Info: fsub za.s\[w8, 0, vgx2\], {z0.s-z1.s}
+.*: Info: other valid variant\(s\):
+.*: Info: fsub za.d\[w8, 0, vgx2\], {z0.d-z1.d}
+.*: Error: too many registers in vector register list at operand 2 -- `fsub za.h\[w13,0,vgx2\],{z1.h-z0.h}'
+.*: Error: invalid vector group size at operand 1 -- `fsub za.h\[w8,11,vgx3\],{z0.h-z1.h}'
+.*: Error: too many registers in vector register list at operand 2 -- `fsub za.h\[w8,0,vgx2\],{z0.h-z4.h}'
+.*: Error: operand mismatch -- `fsub za.s\[w8,0,vgx4\],{z0.h-z3.h}'
+.*: Info: did you mean this\?
+.*: Info: fsub za.s\[w8, 0, vgx4\], {z0.s-z3.s}
+.*: Info: other valid variant\(s\):
+.*: Info: fsub za.d\[w8, 0, vgx4\], {z0.d-z3.d}
+.*: Error: too many registers in vector register list at operand 2 -- `fsub za.h\[w14,0,vgx4\],{z10.h-z3.h}'
+.*: Error: invalid vector group size at operand 1 -- `fsub za.h\[w8,15,vgx1\],{z3.h-z2.h}'
+.*: Error: expected a list of 4 registers at operand 2 -- `fsub za.h\[w8,0,vgx4\],{z30.h-z31.h}'
diff --git a/gas/testsuite/gas/aarch64/sme-f16f16-1-bad.s b/gas/testsuite/gas/aarch64/sme-f16f16-1-bad.s
new file mode 100644
index 00000000000..06fb65022b6
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sme-f16f16-1-bad.s
@@ -0,0 +1,21 @@
+/* FADD. */
+fadd za.s[w8, 0, vgx2], {z0.h - z1.h}
+fadd za.h[w13, 0, vgx2], {z1.h - z0.h}
+fadd za.h[w8, 11, vgx3], {z0.h - z1.h}
+fadd za.h[w8, 0, vgx2], {z0.h - z4.h}
+
+fadd za.s[w8, 0, vgx4], {z0.h - z3.h}
+fadd za.h[w14, 0, vgx4], {z10.h - z3.h}
+fadd za.h[w8, 15, vgx1], {z3.h - z2.h}
+fadd za.h[w8, 0, vgx4], {z30.h - z31.h}
+
+/* FSUB. */
+fsub za.s[w8, 0, vgx2], {z0.h - z1.h}
+fsub za.h[w13, 0, vgx2], {z1.h - z0.h}
+fsub za.h[w8, 11, vgx3], {z0.h - z1.h}
+fsub za.h[w8, 0, vgx2], {z0.h - z4.h}
+
+fsub za.s[w8, 0, vgx4], {z0.h - z3.h}
+fsub za.h[w14, 0, vgx4], {z10.h - z3.h}
+fsub za.h[w8, 15, vgx1], {z3.h - z2.h}
+fsub za.h[w8, 0, vgx4], {z30.h - z31.h}
diff --git a/gas/testsuite/gas/aarch64/sme-f16f16-1.d b/gas/testsuite/gas/aarch64/sme-f16f16-1.d
new file mode 100644
index 00000000000..7e725711039
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sme-f16f16-1.d
@@ -0,0 +1,38 @@
+#name: Test of FEAT_SME_F16F16 fsub and fsub instructions.
+#as: -march=armv9.4-a+sme-f16f16
+#objdump: -dr
+
+[^:]+: file format .*
+
+
+[^:]+:
+
+[^:]+:
+.*: c1a41c00 fadd za.h\[w8, 0, vgx2\], {z0.h-z1.h}
+.*: c1a47c00 fadd za.h\[w11, 0, vgx2\], {z0.h-z1.h}
+.*: c1a41c07 fadd za.h\[w8, 7, vgx2\], {z0.h-z1.h}
+.*: c1a41fc0 fadd za.h\[w8, 0, vgx2\], {z30.h-z31.h}
+.*: c1a47fc7 fadd za.h\[w11, 7, vgx2\], {z30.h-z31.h}
+.*: c1a43e03 fadd za.h\[w9, 3, vgx2\], {z16.h-z17.h}
+.*: c1a45d01 fadd za.h\[w10, 1, vgx2\], {z8.h-z9.h}
+.*: c1a51c00 fadd za.h\[w8, 0, vgx4\], {z0.h-z3.h}
+.*: c1a57c00 fadd za.h\[w11, 0, vgx4\], {z0.h-z3.h}
+.*: c1a51c07 fadd za.h\[w8, 7, vgx4\], {z0.h-z3.h}
+.*: c1a51f80 fadd za.h\[w8, 0, vgx4\], {z28.h-z31.h}
+.*: c1a57f87 fadd za.h\[w11, 7, vgx4\], {z28.h-z31.h}
+.*: c1a53d83 fadd za.h\[w9, 3, vgx4\], {z12.h-z15.h}
+.*: c1a55d01 fadd za.h\[w10, 1, vgx4\], {z8.h-z11.h}
+.*: c1a41c08 fsub za.h\[w8, 0, vgx2\], {z0.h-z1.h}
+.*: c1a47c08 fsub za.h\[w11, 0, vgx2\], {z0.h-z1.h}
+.*: c1a41c0f fsub za.h\[w8, 7, vgx2\], {z0.h-z1.h}
+.*: c1a41fc8 fsub za.h\[w8, 0, vgx2\], {z30.h-z31.h}
+.*: c1a47fcf fsub za.h\[w11, 7, vgx2\], {z30.h-z31.h}
+.*: c1a43e0b fsub za.h\[w9, 3, vgx2\], {z16.h-z17.h}
+.*: c1a45d09 fsub za.h\[w10, 1, vgx2\], {z8.h-z9.h}
+.*: c1a51c08 fsub za.h\[w8, 0, vgx4\], {z0.h-z3.h}
+.*: c1a57c08 fsub za.h\[w11, 0, vgx4\], {z0.h-z3.h}
+.*: c1a51c0f fsub za.h\[w8, 7, vgx4\], {z0.h-z3.h}
+.*: c1a51f88 fsub za.h\[w8, 0, vgx4\], {z28.h-z31.h}
+.*: c1a57f8f fsub za.h\[w11, 7, vgx4\], {z28.h-z31.h}
+.*: c1a53d8b fsub za.h\[w9, 3, vgx4\], {z12.h-z15.h}
+.*: c1a55d09 fsub za.h\[w10, 1, vgx4\], {z8.h-z11.h}
diff --git a/gas/testsuite/gas/aarch64/sme-f16f16-1.s b/gas/testsuite/gas/aarch64/sme-f16f16-1.s
new file mode 100644
index 00000000000..d0ac7f8e908
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sme-f16f16-1.s
@@ -0,0 +1,33 @@
+/* FADD. */
+fadd za.h[w8, 0, vgx2], {z0.h - z1.h}
+fadd za.h[w11, 0, vgx2], {z0.h - z1.h}
+fadd za.h[w8, 7, vgx2], {z0.h - z1.h}
+fadd za.h[w8, 0, vgx2], {z30.h - z31.h}
+fadd za.h[w11, 7, vgx2], {z30.h - z31.h}
+fadd za.h[w9, 3, vgx2], {z16.h - z17.h}
+fadd za.h[w10, 1], {z8.h - z9.h}
+
+fadd za.h[w8, 0, vgx4], {z0.h - z3.h}
+fadd za.h[w11, 0, vgx4], {z0.h - z3.h}
+fadd za.h[w8, 7, vgx4], {z0.h - z3.h}
+fadd za.h[w8, 0, vgx4], {z28.h - z31.h}
+fadd za.h[w11, 7, vgx4], {z28.h - z31.h}
+fadd za.h[w9, 3, vgx4], {z12.h - z15.h}
+fadd za.h[w10, 1], {z8.h - z11.h}
+
+/* FSUB. */
+fsub za.h[w8, 0, vgx2], {z0.h - z1.h}
+fsub za.h[w11, 0, vgx2], {z0.h - z1.h}
+fsub za.h[w8, 7, vgx2], {z0.h - z1.h}
+fsub za.h[w8, 0, vgx2], {z30.h - z31.h}
+fsub za.h[w11, 7, vgx2], {z30.h - z31.h}
+fsub za.h[w9, 3, vgx2], {z16.h - z17.h}
+fsub za.h[w10, 1], {z8.h - z9.h}
+
+fsub za.h[w8, 0, vgx4], {z0.h - z3.h}
+fsub za.h[w11, 0, vgx4], {z0.h - z3.h}
+fsub za.h[w8, 7, vgx4], {z0.h - z3.h}
+fsub za.h[w8, 0, vgx4], {z28.h - z31.h}
+fsub za.h[w11, 7, vgx4], {z28.h - z31.h}
+fsub za.h[w9, 3, vgx4], {z12.h - z15.h}
+fsub za.h[w10, 1], {z8.h - z11.h}
diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h
index 1b01931b0cb..e2e4c6d0a09 100644
--- a/include/opcode/aarch64.h
+++ b/include/opcode/aarch64.h
@@ -264,6 +264,8 @@ enum aarch64_feature_bit {
AARCH64_FEATURE_SME_F8F32,
/* SME F8F16 instructions. */
AARCH64_FEATURE_SME_F8F16,
+ /* Non-widening half-precision FP16 to FP16 arithmetic for SME2. */
+ AARCH64_FEATURE_SME_F16F16,
/* Virtual features. These are used to gate instructions that are enabled
by either of two (or more) sets of command line flags. */
^ permalink raw reply [flat|nested] 12+ messages in thread* [PATCH v1 2/7] aarch64: Add support for FEAT_SME_F16F16 fmops and fmopa instructions.
2024-07-12 16:35 [PATCH v1 0/7][Binutils] aarch64: Add support for FEAT_SME_F16F16 feature and instructions Srinath Parvathaneni
2024-07-12 16:35 ` [PATCH v1 1/7] aarch64: Add support for FEAT_SME_F16F16 feature Srinath Parvathaneni
@ 2024-07-12 16:35 ` Srinath Parvathaneni
2024-07-12 16:35 ` [PATCH v1 3/7] aarch64: Add support for FEAT_SME_F16F16 fmopa and fmops instructions (regenerated files) Srinath Parvathaneni
` (5 subsequent siblings)
7 siblings, 0 replies; 12+ messages in thread
From: Srinath Parvathaneni @ 2024-07-12 16:35 UTC (permalink / raw)
To: binutils; +Cc: richard.earnshaw, nickc, Srinath Parvathaneni
[-- Attachment #1: Type: text/plain, Size: 1006 bytes --]
This patch adds support for FEAT_SME_F16F16 instructions fmops and fmopa,
which are available on passing command line flags +sme-f16f16 and the
spec is available here[1].
[1]: https://developer.arm.com/documentation/ddi0602/2024-06/SME-Instructions?lang=en
---
gas/testsuite/gas/aarch64/sme-f16f16-2-bad.d | 4 +++
gas/testsuite/gas/aarch64/sme-f16f16-2-bad.l | 29 ++++++++++++++++++++
gas/testsuite/gas/aarch64/sme-f16f16-2-bad.s | 17 ++++++++++++
gas/testsuite/gas/aarch64/sme-f16f16-2.d | 28 +++++++++++++++++++
gas/testsuite/gas/aarch64/sme-f16f16-2.s | 21 ++++++++++++++
opcodes/aarch64-tbl.h | 14 ++++++++++
6 files changed, 113 insertions(+)
create mode 100644 gas/testsuite/gas/aarch64/sme-f16f16-2-bad.d
create mode 100644 gas/testsuite/gas/aarch64/sme-f16f16-2-bad.l
create mode 100644 gas/testsuite/gas/aarch64/sme-f16f16-2-bad.s
create mode 100644 gas/testsuite/gas/aarch64/sme-f16f16-2.d
create mode 100644 gas/testsuite/gas/aarch64/sme-f16f16-2.s
[-- Warning: decoded text below may be mangled, UTF-8 assumed --]
[-- Attachment #2: v1-0002-aarch64-Add-support-for-FEAT_SME_F16F16-fmops-and.patch --]
[-- Type: text/x-patch; name="v1-0002-aarch64-Add-support-for-FEAT_SME_F16F16-fmops-and.patch", Size: 8338 bytes --]
diff --git a/gas/testsuite/gas/aarch64/sme-f16f16-2-bad.d b/gas/testsuite/gas/aarch64/sme-f16f16-2-bad.d
new file mode 100644
index 00000000000..51cb30628d2
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sme-f16f16-2-bad.d
@@ -0,0 +1,4 @@
+#name: Test of invalid FEAT_SME_F16F16 fmops and fmopa instructions.
+#as: -march=armv9.4-a+sme-f16f16
+#source: sme-f16f16-2-bad.s
+#error_output: sme-f16f16-2-bad.l
diff --git a/gas/testsuite/gas/aarch64/sme-f16f16-2-bad.l b/gas/testsuite/gas/aarch64/sme-f16f16-2-bad.l
new file mode 100644
index 00000000000..083b3a08ca4
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sme-f16f16-2-bad.l
@@ -0,0 +1,29 @@
+.*: Assembler messages:
+.*: Error: operand mismatch -- `fmopa ZA1.h,p0,p0/m,z0.h,z0.h'
+.*: Info: did you mean this\?
+.*: Info: fmopa za1.h, p0/m, p0/m, z0.h, z0.h
+.*: Error: operand mismatch -- `fmopa ZA0.h,p7/m,p0,z0.h,z0.h'
+.*: Info: did you mean this\?
+.*: Info: fmopa za0.h, p7/m, p0/m, z0.h, z0.h
+.*: Error: operand mismatch -- `fmopa ZA0.h,p0/m,p7/m,z0.s,z0.s'
+.*: Info: did you mean this\?
+.*: Info: fmopa za0.s, p0/m, p7/m, z0.s, z0.s
+.*: Error: operand mismatch -- `fmopa ZA0.h,p0/m,p0/m,z31.d,z0.d'
+.*: Info: did you mean this\?
+.*: Info: fmopa za0.d, p0/m, p0/m, z31.d, z0.d
+.*: Error: ZA tile number out of range at operand 1 -- `fmopa ZA2.h,p0/m,p8/m,z0.s,z31.b'
+.*: Error: ZA tile number out of range at operand 1 -- `fmopa ZA4.h,p15/m,p11/m,z0.s,z31.b'
+.*: Error: operand mismatch -- `fmops ZA1.h,p0,p0/m,z0.h,z0.h'
+.*: Info: did you mean this\?
+.*: Info: fmops za1.h, p0/m, p0/m, z0.h, z0.h
+.*: Error: operand mismatch -- `fmops ZA0.h,p7/m,p0,z0.h,z0.h'
+.*: Info: did you mean this\?
+.*: Info: fmops za0.h, p7/m, p0/m, z0.h, z0.h
+.*: Error: operand mismatch -- `fmops ZA0.h,p0/m,p7/m,z0.s,z0.s'
+.*: Info: did you mean this\?
+.*: Info: fmops za0.s, p0/m, p7/m, z0.s, z0.s
+.*: Error: operand mismatch -- `fmops ZA0.h,p0/m,p0/m,z31.d,z0.d'
+.*: Info: did you mean this\?
+.*: Info: fmops za0.d, p0/m, p0/m, z31.d, z0.d
+.*: Error: ZA tile number out of range at operand 1 -- `fmops ZA2.h,p0/m,p8/m,z0.s,z31.b'
+.*: Error: ZA tile number out of range at operand 1 -- `fmops ZA4.h,p15/m,p11/m,z0.s,z31.b'
diff --git a/gas/testsuite/gas/aarch64/sme-f16f16-2-bad.s b/gas/testsuite/gas/aarch64/sme-f16f16-2-bad.s
new file mode 100644
index 00000000000..4bce38087a9
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sme-f16f16-2-bad.s
@@ -0,0 +1,17 @@
+/* FMOPA. */
+fmopa ZA0.s, p0/m, p0/m, z0.h, z0.h
+fmopa ZA1.h, p0, p0/m, z0.h, z0.h
+fmopa ZA0.h, p7/m, p0, z0.h, z0.h
+fmopa ZA0.h, p0/m, p7/m, z0.s, z0.s
+fmopa ZA0.h, p0/m, p0/m, z31.d, z0.d
+fmopa ZA2.h, p0/m, p8/m, z0.s, z31.b
+fmopa ZA4.h, p15/m, p11/m, z0.s, z31.b
+
+/* FMOPS. */
+fmops ZA0.s, p0/m, p0/m, z0.h, z0.h
+fmops ZA1.h, p0, p0/m, z0.h, z0.h
+fmops ZA0.h, p7/m, p0, z0.h, z0.h
+fmops ZA0.h, p0/m, p7/m, z0.s, z0.s
+fmops ZA0.h, p0/m, p0/m, z31.d, z0.d
+fmops ZA2.h, p0/m, p8/m, z0.s, z31.b
+fmops ZA4.h, p15/m, p11/m, z0.s, z31.b
diff --git a/gas/testsuite/gas/aarch64/sme-f16f16-2.d b/gas/testsuite/gas/aarch64/sme-f16f16-2.d
new file mode 100644
index 00000000000..41e156d9b9b
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sme-f16f16-2.d
@@ -0,0 +1,28 @@
+#name: Test of FEAT_SME_F16F16 fmopa and fmops instructions.
+#as: -march=armv9.4-a+sme-f16f16
+#objdump: -dr
+
+[^:]+: file format .*
+
+
+[^:]+:
+
+[^:]+:
+.*: 81800008 fmopa za0.h, p0/m, p0/m, z0.h, z0.h
+.*: 81800009 fmopa za1.h, p0/m, p0/m, z0.h, z0.h
+.*: 81801c08 fmopa za0.h, p7/m, p0/m, z0.h, z0.h
+.*: 8180e008 fmopa za0.h, p0/m, p7/m, z0.h, z0.h
+.*: 818003e8 fmopa za0.h, p0/m, p0/m, z31.h, z0.h
+.*: 819f0008 fmopa za0.h, p0/m, p0/m, z0.h, z31.h
+.*: 819fffe9 fmopa za1.h, p7/m, p7/m, z31.h, z31.h
+.*: 818fad48 fmopa za0.h, p3/m, p5/m, z10.h, z15.h
+.*: 819965e9 fmopa za1.h, p1/m, p3/m, z15.h, z25.h
+.*: 81800018 fmops za0.h, p0/m, p0/m, z0.h, z0.h
+.*: 81800019 fmops za1.h, p0/m, p0/m, z0.h, z0.h
+.*: 81801c18 fmops za0.h, p7/m, p0/m, z0.h, z0.h
+.*: 8180e018 fmops za0.h, p0/m, p7/m, z0.h, z0.h
+.*: 818003f8 fmops za0.h, p0/m, p0/m, z31.h, z0.h
+.*: 819f0018 fmops za0.h, p0/m, p0/m, z0.h, z31.h
+.*: 819ffff9 fmops za1.h, p7/m, p7/m, z31.h, z31.h
+.*: 818fad58 fmops za0.h, p3/m, p5/m, z10.h, z15.h
+.*: 819965f9 fmops za1.h, p1/m, p3/m, z15.h, z25.h
diff --git a/gas/testsuite/gas/aarch64/sme-f16f16-2.s b/gas/testsuite/gas/aarch64/sme-f16f16-2.s
new file mode 100644
index 00000000000..2032cf36790
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sme-f16f16-2.s
@@ -0,0 +1,21 @@
+/* FMOPA. */
+fmopa ZA0.h, p0/m, p0/m, z0.h, z0.h
+fmopa ZA1.h, p0/m, p0/m, z0.h, z0.h
+fmopa ZA0.h, p7/m, p0/m, z0.h, z0.h
+fmopa ZA0.h, p0/m, p7/m, z0.h, z0.h
+fmopa ZA0.h, p0/m, p0/m, z31.h, z0.h
+fmopa ZA0.h, p0/m, p0/m, z0.h, z31.h
+fmopa ZA1.h, p7/m, p7/m, z31.h, z31.h
+fmopa ZA0.h, p3/m, p5/m, z10.h, z15.h
+fmopa ZA1.h, p1/m, p3/m, z15.h, z25.h
+
+/* FMOPS. */
+fmops ZA0.h, p0/m, p0/m, z0.h, z0.h
+fmops ZA1.h, p0/m, p0/m, z0.h, z0.h
+fmops ZA0.h, p7/m, p0/m, z0.h, z0.h
+fmops ZA0.h, p0/m, p7/m, z0.h, z0.h
+fmops ZA0.h, p0/m, p0/m, z31.h, z0.h
+fmops ZA0.h, p0/m, p0/m, z0.h, z31.h
+fmops ZA1.h, p7/m, p7/m, z31.h, z31.h
+fmops ZA0.h, p3/m, p5/m, z10.h, z15.h
+fmops ZA1.h, p1/m, p3/m, z15.h, z25.h
diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h
index d49ad3683b5..cd8c8257aec 100644
--- a/opcodes/aarch64-tbl.h
+++ b/opcodes/aarch64-tbl.h
@@ -1715,6 +1715,10 @@
{ \
QLF5(S_H,P_M,P_M,S_B,S_B) \
}
+#define OP_SVE_HMMHH \
+{ \
+ QLF5(S_H,P_M,P_M,S_H,S_H) \
+}
#define OP_SVE_HMS \
{ \
QLF3(S_H,P_M,S_S), \
@@ -2861,6 +2865,8 @@ static const aarch64_feature_set aarch64_feature_sme_f8f16 =
AARCH64_FEATURES (2, SME_F8F32, SME2);
static const aarch64_feature_set aarch64_feature_sme_f16f16_f8f16 =
AARCH64_FEATURES (2, SME_F16F16_F8F16, SME2);
+static const aarch64_feature_set aarch64_feature_sme_f16f16 =
+ AARCH64_FEATURES (2, SME_F16F16, SME2);
#define CORE &aarch64_feature_v8
#define FP &aarch64_feature_fp
@@ -2948,6 +2954,7 @@ static const aarch64_feature_set aarch64_feature_sme_f16f16_f8f16 =
#define SME_F8F32 &aarch64_feature_sme_f8f32
#define SME_F8F16 &aarch64_feature_sme_f8f16
#define SME_F16F16_F8F16 &aarch64_feature_sme_f16f16_f8f16
+#define SME_F16F16 &aarch64_feature_sme_f16f16
#define CORE_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS) \
{ NAME, OPCODE, MASK, CLASS, OP, CORE, OPS, QUALS, FLAGS, 0, 0, NULL }
@@ -3169,6 +3176,9 @@ static const aarch64_feature_set aarch64_feature_sme_f16f16_f8f16 =
{ NAME, OPCODE, MASK, CLASS, 0, SME_F8F16, OPS, QUALS, F_STRICT | FLAGS, CONSTRAINTS, 0, NULL }
#define SME_F16F16_F8F16_INSNC(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS,CONSTRAINTS) \
{ NAME, OPCODE, MASK, CLASS, 0, SME_F16F16_F8F16, OPS, QUALS, F_STRICT | FLAGS, CONSTRAINTS, 0, NULL }
+#define SME_F16F16_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,TIED) \
+ { NAME, OPCODE, MASK, CLASS, OP, SME_F16F16, OPS, QUALS, \
+ FLAGS | F_STRICT, 0, TIED, NULL }
#define MOPS_CPY_OP1_OP2_PME_INSN(NAME, OPCODE, MASK, FLAGS, CONSTRAINTS) \
MOPS_INSN (NAME, OPCODE, MASK, 0, \
@@ -6686,6 +6696,10 @@ const struct aarch64_opcode aarch64_opcode_table[] =
SME2p1_INSN ("zero", 0xc00f0000, 0xffff9ffe, sme2_movaz, 0, OP1 (SME_ZA_array_off1x4), OP_SVE_D, F_OD (2) | F_VG_REQ, 0),
SME2p1_INSN ("zero", 0xc00f8000, 0xffff9ffe, sme2_movaz, 0, OP1 (SME_ZA_array_off1x4), OP_SVE_D, F_OD (4) | F_VG_REQ, 0),
+/* SME2.1 half-precision floating-point instructions. */
+ SME_F16F16_INSN("fmopa", 0x81800008, 0xffe0001e, sme_misc, 0, OP5 (SME_ZAda_1b, SVE_Pg3, SME_Pm, SVE_Zn, SVE_Zm_16), OP_SVE_HMMHH, 0, 0),
+ SME_F16F16_INSN("fmops", 0x81800018, 0xffe0001e, sme_misc, 0, OP5 (SME_ZAda_1b, SVE_Pg3, SME_Pm, SVE_Zn, SVE_Zm_16), OP_SVE_HMMHH, 0, 0),
+
/* SVE2p1 Instructions. */
SVE2p1_INSN("addqv",0x04052000, 0xff3fe000, sve2_urqvs, 0, OP3 (Vd, SVE_Pg3, SVE_Zn), OP_SVE_vUS_BHSD_BHSD, F_OPD_SIZE, 0),
SVE2p1_INSN("andqv",0x041e2000, 0xff3fe000, sve2_urqvs, 0, OP3 (Vd, SVE_Pg3, SVE_Zn), OP_SVE_vUS_BHSD_BHSD, F_OPD_SIZE, 0),
^ permalink raw reply [flat|nested] 12+ messages in thread* [PATCH v1 3/7] aarch64: Add support for FEAT_SME_F16F16 fmopa and fmops instructions (regenerated files).
2024-07-12 16:35 [PATCH v1 0/7][Binutils] aarch64: Add support for FEAT_SME_F16F16 feature and instructions Srinath Parvathaneni
2024-07-12 16:35 ` [PATCH v1 1/7] aarch64: Add support for FEAT_SME_F16F16 feature Srinath Parvathaneni
2024-07-12 16:35 ` [PATCH v1 2/7] aarch64: Add support for FEAT_SME_F16F16 fmops and fmopa instructions Srinath Parvathaneni
@ 2024-07-12 16:35 ` Srinath Parvathaneni
2024-07-12 16:35 ` [PATCH v1 4/7] aarch64: Add support for FEAT_SME_F16F16 fmla and fmls instructions Srinath Parvathaneni
` (4 subsequent siblings)
7 siblings, 0 replies; 12+ messages in thread
From: Srinath Parvathaneni @ 2024-07-12 16:35 UTC (permalink / raw)
To: binutils; +Cc: richard.earnshaw, nickc, Srinath Parvathaneni
[-- Attachment #1: Type: text/plain, Size: 248 bytes --]
This patch includes the regenerated files for
aarch64: Add support for FEAT_SME_F16F16 fmopa and fmops instructions.
---
opcodes/aarch64-dis-2.c | 476 +++++++++++++++++++++-------------------
1 file changed, 249 insertions(+), 227 deletions(-)
[-- Warning: decoded text below may be mangled, UTF-8 assumed --]
[-- Attachment #2: v1-0003-aarch64-Add-support-for-FEAT_SME_F16F16-fmopa-and.patch --]
[-- Type: text/x-patch; name="v1-0003-aarch64-Add-support-for-FEAT_SME_F16F16-fmopa-and.patch", Size: 126473 bytes --]
diff --git a/opcodes/aarch64-dis-2.c b/opcodes/aarch64-dis-2.c
index 4138ec8907f..f1aa790b28f 100644
--- a/opcodes/aarch64-dis-2.c
+++ b/opcodes/aarch64-dis-2.c
@@ -271,7 +271,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000000x000101x00xxxxxxxxxxxxxx
luti4. */
- return 3428;
+ return 3430;
}
else
{
@@ -310,7 +310,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000000xx01101x00xxxxxxxxxxxxxx
luti4. */
- return 3429;
+ return 3431;
}
else
{
@@ -542,7 +542,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000000010011x1xxxx00xxxxxxxxxx
movt. */
- return 3430;
+ return 3432;
}
}
else
@@ -1366,7 +1366,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx000000101xxxxxxxxxxxxxxxx00xxx
fmopa. */
- return 3496;
+ return 3498;
}
else
{
@@ -1374,7 +1374,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx000000101xxxxxxxxxxxxxxxx01xxx
fmopa. */
- return 3495;
+ return 3497;
}
}
else
@@ -1722,7 +1722,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx0000010001xxxx1xx0xxxxx1000xxx
fmlall. */
- return 3489;
+ return 3491;
}
}
}
@@ -1752,7 +1752,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx0000010001xxxxxxx1xxxxxx00xxxx
fdot. */
- return 3474;
+ return 3476;
}
}
else
@@ -2077,11 +2077,22 @@ aarch64_opcode_lookup_1 (uint32_t word)
{
if (((word >> 30) & 0x1) == 0)
{
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- x0000001100xxxxxxxxxxxxxxxx0xxxx
- bfmopa. */
- return 2411;
+ if (((word >> 3) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x0000001100xxxxxxxxxxxxxxxx00xxx
+ bfmopa. */
+ return 2411;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x0000001100xxxxxxxxxxxxxxxx01xxx
+ fmopa. */
+ return 3325;
+ }
}
else
{
@@ -2124,7 +2135,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x10000011001xxxxxxx0xxxxxx100xxx
fmlall. */
- return 3488;
+ return 3490;
}
}
}
@@ -2229,7 +2240,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x10000011001xxxxxxx1xxxxxx10xxxx
fmlal. */
- return 3481;
+ return 3483;
}
}
}
@@ -2261,11 +2272,22 @@ aarch64_opcode_lookup_1 (uint32_t word)
{
if (((word >> 30) & 0x1) == 0)
{
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- x0000001100xxxxxxxxxxxxxxxx1xxxx
- bfmops. */
- return 2412;
+ if (((word >> 3) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x0000001100xxxxxxxxxxxxxxxx10xxx
+ bfmops. */
+ return 2412;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x0000001100xxxxxxxxxxxxxxxx11xxx
+ fmops. */
+ return 3326;
+ }
}
else
{
@@ -2402,7 +2424,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x10000011001xxxxxxx1xxxxxx11xxxx
fmlal. */
- return 3480;
+ return 3482;
}
}
}
@@ -2444,7 +2466,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx0000010100xxxxxxxxxxxxxxxx0xxx
fmlall. */
- return 3487;
+ return 3489;
}
else
{
@@ -2812,7 +2834,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xxx000010101xxxx0xx0xxxxxx111xxx
fdot. */
- return 3467;
+ return 3469;
}
else
{
@@ -2881,7 +2903,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xxx000010101xxxx1xx0xxxxxx001xxx
fdot. */
- return 3468;
+ return 3470;
}
else
{
@@ -2960,7 +2982,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx0000011100xxxxxxx0xxxxxxx0xxxx
fmlal. */
- return 3479;
+ return 3481;
}
else
{
@@ -3015,7 +3037,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx0000011101xxxx0xx01xxxxx00xxxx
fvdotb. */
- return 3498;
+ return 3500;
}
else
{
@@ -3033,7 +3055,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx0000011101xxxxxxx0xxxxxx10xxxx
fdot. */
- return 3473;
+ return 3475;
}
}
}
@@ -3107,7 +3129,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx0000011101xxxxxxx1xxxxxx10xxxx
fvdot. */
- return 3497;
+ return 3499;
}
}
}
@@ -3187,7 +3209,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx000001110xxxxx0xx01xxxxxx1xxxx
fvdott. */
- return 3499;
+ return 3501;
}
else
{
@@ -3364,7 +3386,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x10000011x1xxxx00xx000xxxx10000x
fmlall. */
- return 3493;
+ return 3495;
}
else
{
@@ -3372,7 +3394,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x10000011x1xxxx10xx000xxxx10000x
fmlall. */
- return 3494;
+ return 3496;
}
}
}
@@ -3427,7 +3449,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001xx10xxxx0xx000xxxxx00x1x
fmlall. */
- return 3491;
+ return 3493;
}
else
{
@@ -3435,7 +3457,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001xx11xxxx0xx000xxxxx00x1x
fmlall. */
- return 3492;
+ return 3494;
}
}
}
@@ -3489,7 +3511,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x10000011x1xxxx00xx100xxxx100xxx
fdot. */
- return 3477;
+ return 3479;
}
else
{
@@ -3497,7 +3519,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x10000011x1xxxx10xx100xxxx100xxx
fdot. */
- return 3478;
+ return 3480;
}
}
}
@@ -3559,7 +3581,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001101xxxx00xx010xxxx1000xx
fmlal. */
- return 3485;
+ return 3487;
}
else
{
@@ -3567,7 +3589,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001101xxxx10xx010xxxx1000xx
fmlal. */
- return 3486;
+ return 3488;
}
}
}
@@ -3622,7 +3644,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001xx10xxxx0xx010xxxxx001xx
fmlal. */
- return 3483;
+ return 3485;
}
else
{
@@ -3630,7 +3652,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001xx11xxxx0xx010xxxxx001xx
fmlal. */
- return 3484;
+ return 3486;
}
}
}
@@ -3699,7 +3721,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001xx11xxxx0xx001xxxxx000xx
fmlall. */
- return 3490;
+ return 3492;
}
}
else
@@ -3782,7 +3804,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001xx11xxxx0xx011xxxxx00xxx
fmlal. */
- return 3482;
+ return 3484;
}
}
else
@@ -3803,7 +3825,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001xx1xx1x00xx111xxxxx00xxx
fadd. */
- return 3431;
+ return 3433;
}
}
else
@@ -3822,7 +3844,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001xx1xx1x10xx111xxxxx00xxx
fadd. */
- return 3432;
+ return 3434;
}
}
}
@@ -3948,7 +3970,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x10000011x1xxxx00xx100xxxx110xxx
fdot. */
- return 3471;
+ return 3473;
}
else
{
@@ -3956,7 +3978,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x10000011x1xxxx10xx100xxxx110xxx
fdot. */
- return 3472;
+ return 3474;
}
}
}
@@ -4247,7 +4269,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001xx10xxxx0xx100xxxxx01xxx
fdot. */
- return 3475;
+ return 3477;
}
else
{
@@ -4255,7 +4277,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001xx11xxxx0xx100xxxxx01xxx
fdot. */
- return 3476;
+ return 3478;
}
}
}
@@ -4526,7 +4548,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001xx1xx1x00xx111xxxxx01xxx
fsub. */
- return 3433;
+ return 3435;
}
}
else
@@ -4545,7 +4567,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001xx1xx1x10xx111xxxxx01xxx
fsub. */
- return 3434;
+ return 3436;
}
}
}
@@ -4607,7 +4629,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001xx10xxxx0xx100xxxxx11xxx
fdot. */
- return 3469;
+ return 3471;
}
else
{
@@ -4615,7 +4637,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001xx11xxxx0xx100xxxxx11xxx
fdot. */
- return 3470;
+ return 3472;
}
}
}
@@ -5150,7 +5172,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001xx1xxxxx101000xx1x0xxxx0
fscale. */
- return 3405;
+ return 3407;
}
}
else
@@ -5298,7 +5320,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001x0100100111000xxxx0xxxxx
fcvt. */
- return 3402;
+ return 3404;
}
else
{
@@ -5306,7 +5328,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001x1100100111000xxxx0xxxxx
bfcvt. */
- return 3397;
+ return 3399;
}
}
else
@@ -5315,7 +5337,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001xx110100111000xxxx0xxxxx
fcvt. */
- return 3403;
+ return 3405;
}
}
else
@@ -5366,7 +5388,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001xx1xx100111000xxxx1xxxxx
fcvtn. */
- return 3404;
+ return 3406;
}
}
}
@@ -5449,7 +5471,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x10000010010x110111000xxxxxxxxx0
f1cvt. */
- return 3398;
+ return 3400;
}
else
{
@@ -5457,7 +5479,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x10000011010x110111000xxxxxxxxx0
f2cvt. */
- return 3399;
+ return 3401;
}
}
else
@@ -5468,7 +5490,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x10000010110x110111000xxxxxxxxx0
bf1cvt. */
- return 3393;
+ return 3395;
}
else
{
@@ -5476,7 +5498,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x10000011110x110111000xxxxxxxxx0
bf2cvt. */
- return 3394;
+ return 3396;
}
}
}
@@ -5511,7 +5533,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001001xxx10111000xxxxxxxxx1
f1cvtl. */
- return 3400;
+ return 3402;
}
else
{
@@ -5519,7 +5541,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001101xxx10111000xxxxxxxxx1
f2cvtl. */
- return 3401;
+ return 3403;
}
}
else
@@ -5530,7 +5552,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001011xxx10111000xxxxxxxxx1
bf1cvtl. */
- return 3395;
+ return 3397;
}
else
{
@@ -5538,7 +5560,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001111xxx10111000xxxxxxxxx1
bf2cvtl. */
- return 3396;
+ return 3398;
}
}
}
@@ -5807,7 +5829,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001xx1xxxxx1x1100xx100xxxx0
fscale. */
- return 3407;
+ return 3409;
}
}
else
@@ -5983,16 +6005,16 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001xx1xxxxx1x1010xx100xxxx0
fscale. */
- return 3406;
- }
- else
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- x1000001xx1xxxxx1x1110xx100xxxx0
- fscale. */
return 3408;
}
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x1000001xx1xxxxx1x1110xx100xxxx0
+ fscale. */
+ return 3410;
+ }
}
}
else
@@ -11159,7 +11181,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x0x11010000xxxxxxx1xxxxxxxxxxxxx
addpt. */
- return 3409;
+ return 3411;
}
else
{
@@ -11167,7 +11189,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1x11010000xxxxxxx1xxxxxxxxxxxxx
subpt. */
- return 3410;
+ return 3412;
}
}
}
@@ -12085,7 +12107,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xxxx1011x11xxxxx0xxxxxxxxxxxxxxx
maddpt. */
- return 3411;
+ return 3413;
}
else
{
@@ -12093,7 +12115,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xxxx1011x11xxxxx1xxxxxxxxxxxxxxx
msubpt. */
- return 3412;
+ return 3414;
}
}
}
@@ -12178,7 +12200,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
000001x0xx000100000xxxxxxxxxxxxx
addpt. */
- return 3413;
+ return 3415;
}
else
{
@@ -12285,7 +12307,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
000001x0xx000101000xxxxxxxxxxxxx
subpt. */
- return 3415;
+ return 3417;
}
else
{
@@ -12490,7 +12512,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
000001x0xx1xxxxx000010xxxxxxxxxx
addpt. */
- return 3414;
+ return 3416;
}
else
{
@@ -12531,7 +12553,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
000001x0xx1xxxxx000011xxxxxxxxxx
subpt. */
- return 3416;
+ return 3418;
}
else
{
@@ -14189,7 +14211,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
010001x0xx0xxxxx110100xxxxxxxxxx
mlapt. */
- return 3418;
+ return 3420;
}
}
else
@@ -14219,7 +14241,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
010001x0xx0xxxxx110110xxxxxxxxxx
madpt. */
- return 3417;
+ return 3419;
}
}
}
@@ -14527,7 +14549,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
000001x0xx00x100001xxxxxxxxxxxxx
smaxqv. */
- return 3327;
+ return 3329;
}
else
{
@@ -14535,7 +14557,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
000001x0xx01x100001xxxxxxxxxxxxx
orqv. */
- return 3338;
+ return 3340;
}
}
else
@@ -14546,7 +14568,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
000001x0xx0x0101001xxxxxxxxxxxxx
addqv. */
- return 3325;
+ return 3327;
}
else
{
@@ -14556,7 +14578,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
000001x0xx001101001xxxxxxxxxxxxx
umaxqv. */
- return 3329;
+ return 3331;
}
else
{
@@ -14564,7 +14586,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
000001x0xx011101001xxxxxxxxxxxxx
eorqv. */
- return 3331;
+ return 3333;
}
}
}
@@ -14601,7 +14623,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
000001x0xx00x110001xxxxxxxxxxxxx
sminqv. */
- return 3328;
+ return 3330;
}
else
{
@@ -14609,7 +14631,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
000001x0xx01x110001xxxxxxxxxxxxx
andqv. */
- return 3326;
+ return 3328;
}
}
}
@@ -14629,7 +14651,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
000001x0xx0xx111001xxxxxxxxxxxxx
uminqv. */
- return 3330;
+ return 3332;
}
}
}
@@ -15373,7 +15395,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
110001x0x00xxxxx101xxxxxxxxxxxxx
ld1q. */
- return 3354;
+ return 3356;
}
else
{
@@ -16387,7 +16409,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
010001x0xx0xxxxx111x00xxxxxxxxxx
zipq1. */
- return 3344;
+ return 3346;
}
else
{
@@ -16397,7 +16419,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
010001x0xx0xxxxx111010xxxxxxxxxx
uzpq1. */
- return 3342;
+ return 3344;
}
else
{
@@ -16405,7 +16427,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
010001x0xx0xxxxx111110xxxxxxxxxx
tblq. */
- return 3339;
+ return 3341;
}
}
}
@@ -16417,7 +16439,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
010001x0xx0xxxxx111x01xxxxxxxxxx
zipq2. */
- return 3345;
+ return 3347;
}
else
{
@@ -16425,7 +16447,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
010001x0xx0xxxxx111x11xxxxxxxxxx
uzpq2. */
- return 3343;
+ return 3345;
}
}
}
@@ -16905,7 +16927,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
111001x0x00xxxxx000xxxxxxxxxxxxx
st3q. */
- return 3363;
+ return 3365;
}
else
{
@@ -16915,16 +16937,16 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
111001x0010xxxxx000xxxxxxxxxxxxx
st2q. */
- return 3362;
- }
- else
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- 111001x0110xxxxx000xxxxxxxxxxxxx
- st4q. */
return 3364;
}
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 111001x0110xxxxx000xxxxxxxxxxxxx
+ st4q. */
+ return 3366;
+ }
}
}
else
@@ -17370,7 +17392,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x0xx0x0000101xxxxxxxxxxxxx
faddqv. */
- return 3332;
+ return 3334;
}
else
{
@@ -17387,7 +17409,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x0xx0xx100101xxxxxxxxxxxxx
fmaxnmqv. */
- return 3333;
+ return 3335;
}
}
else
@@ -17428,7 +17450,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x0xx0xx110101xxxxxxxxxxxxx
fmaxqv. */
- return 3334;
+ return 3336;
}
}
}
@@ -17450,7 +17472,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x0xx0xx101101xxxxxxxxxxxxx
fminnmqv. */
- return 3335;
+ return 3337;
}
}
else
@@ -17469,7 +17491,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x0xx0xx111101xxxxxxxxxxxxx
fminqv. */
- return 3336;
+ return 3338;
}
}
}
@@ -17589,7 +17611,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
101001x0xx01xxxx111xxxxxxxxxxxxx
ld2q. */
- return 3355;
+ return 3357;
}
}
}
@@ -17725,7 +17747,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
101001x0xx1xxxxx100xxxxxxxxxxxxx
ld2q. */
- return 3358;
+ return 3360;
}
}
else
@@ -17870,7 +17892,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
111001x00x1xxxxx000xxxxxxxxxxxxx
st2q. */
- return 3365;
+ return 3367;
}
}
else
@@ -17913,7 +17935,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
111001x0101xxxxx000xxxxxxxxxxxxx
st3q. */
- return 3366;
+ return 3368;
}
}
else
@@ -17954,7 +17976,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
111001x0111xxxxx000xxxxxxxxxxxxx
st4q. */
- return 3367;
+ return 3369;
}
}
}
@@ -17983,7 +18005,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x0001xxxxx0100x1xxxxxxxxxx
fdot. */
- return 3454;
+ return 3456;
}
}
else
@@ -17992,7 +18014,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x0001xxxxx0101xxxxxxxxxxxx
fmlalb. */
- return 3456;
+ return 3458;
}
}
else
@@ -18033,7 +18055,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x0101xxxxx0101xxxxxxxxxxxx
fmlalt. */
- return 3466;
+ return 3468;
}
}
else
@@ -18066,7 +18088,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x0011xxxxx010xx1xxxxxxxxxx
fdot. */
- return 3452;
+ return 3454;
}
}
else
@@ -18137,7 +18159,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x11001x0001xxxxx100010xxxxxxxxxx
fmlallbb. */
- return 3457;
+ return 3459;
}
}
else
@@ -18146,7 +18168,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x11001x0001xxxxx1000x1xxxxxxxxxx
fdot. */
- return 3453;
+ return 3455;
}
}
else
@@ -18155,7 +18177,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x11001x0001xxxxx1100xxxxxxxxxxxx
fmlallbb. */
- return 3458;
+ return 3460;
}
}
else
@@ -18164,7 +18186,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x11001x0001xxxxx1x01xxxxxxxxxxxx
fmlallbt. */
- return 3459;
+ return 3461;
}
}
else
@@ -18191,7 +18213,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x0101xxxxx100010xxxxxxxxxx
fmlalb. */
- return 3455;
+ return 3457;
}
}
else
@@ -18209,7 +18231,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x0101xxxxx1100xxxxxxxxxxxx
fmlalltb. */
- return 3462;
+ return 3464;
}
}
else
@@ -18218,7 +18240,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x0101xxxxx1x01xxxxxxxxxxxx
fmlalt. */
- return 3465;
+ return 3467;
}
}
else
@@ -18251,7 +18273,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x11001x0011xxxxx100xx1xxxxxxxxxx
fdot. */
- return 3451;
+ return 3453;
}
}
else
@@ -18260,7 +18282,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x11001x0011xxxxx110xxxxxxxxxxxxx
fmlallbt. */
- return 3460;
+ return 3462;
}
}
else
@@ -18292,7 +18314,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x0111xxxxx110xxxxxxxxxxxxx
fmlalltt. */
- return 3464;
+ return 3466;
}
}
else
@@ -18591,7 +18613,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
111001x0xx1xxxxx001xxxxxxxxxxxxx
st1q. */
- return 3361;
+ return 3363;
}
}
else
@@ -18606,16 +18628,16 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x11001x0001xxxxx1010xxxxxxxxxxxx
fmlalltb. */
- return 3461;
- }
- else
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- x11001x0001xxxxx1011xxxxxxxxxxxx
- fmlalltt. */
return 3463;
}
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x11001x0001xxxxx1011xxxxxxxxxxxx
+ fmlalltt. */
+ return 3465;
+ }
}
else
{
@@ -19332,7 +19354,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
000001x1001010x0001110xxxxxxxxxx
pmov. */
- return 3346;
+ return 3348;
}
else
{
@@ -19340,7 +19362,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
000001x1001011x0001110xxxxxxxxxx
pmov. */
- return 3347;
+ return 3349;
}
}
else
@@ -19349,7 +19371,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
000001x101101xx0001110xxxxxxxxxx
pmov. */
- return 3348;
+ return 3350;
}
}
else
@@ -19358,7 +19380,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
000001x11x101xx0001110xxxxxxxxxx
pmov. */
- return 3349;
+ return 3351;
}
}
else
@@ -19404,7 +19426,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
000001x1001x10x1001110xxxxxxxxxx
pmov. */
- return 3350;
+ return 3352;
}
else
{
@@ -19412,7 +19434,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
000001x1001x11x1001110xxxxxxxxxx
pmov. */
- return 3351;
+ return 3353;
}
}
else
@@ -19421,7 +19443,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
000001x1011x1xx1001110xxxxxxxxxx
pmov. */
- return 3352;
+ return 3354;
}
}
else
@@ -19430,7 +19452,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
000001x11x1x1xx1001110xxxxxxxxxx
pmov. */
- return 3353;
+ return 3355;
}
}
}
@@ -19449,7 +19471,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
000001x1x01xxxxx001001xxxxxxxxxx
dupq. */
- return 3337;
+ return 3339;
}
else
{
@@ -19457,7 +19479,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
000001x1x11xxxxx001001xxxxxxxxxx
extq. */
- return 3341;
+ return 3343;
}
}
else
@@ -19466,7 +19488,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
000001x1xx1xxxxx001101xxxxxxxxxx
tbxq. */
- return 3340;
+ return 3342;
}
}
else
@@ -21069,7 +21091,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
010001x1xx1xxxxx101100xxxxxxxxxx
luti2. */
- return 3423;
+ return 3425;
}
}
else
@@ -21078,7 +21100,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
010001x1xx1xxxxx101x10xxxxxxxxxx
luti2. */
- return 3424;
+ return 3426;
}
}
else
@@ -21091,7 +21113,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
010001x1xx1xxxxx101001xxxxxxxxxx
luti4. */
- return 3425;
+ return 3427;
}
else
{
@@ -21099,7 +21121,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
010001x1xx1xxxxx101101xxxxxxxxxx
luti4. */
- return 3426;
+ return 3428;
}
}
else
@@ -21108,7 +21130,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
010001x1xx1xxxxx101x11xxxxxxxxxx
luti4. */
- return 3427;
+ return 3429;
}
}
}
@@ -22059,7 +22081,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x1xx001000001x00xxxxxxxxxx
f1cvt. */
- return 3385;
+ return 3387;
}
else
{
@@ -22067,7 +22089,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x1xx001000001x10xxxxxxxxxx
bf1cvt. */
- return 3381;
+ return 3383;
}
}
else
@@ -22078,7 +22100,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x1xx001000001x01xxxxxxxxxx
f2cvt. */
- return 3386;
+ return 3388;
}
else
{
@@ -22086,7 +22108,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x1xx001000001x11xxxxxxxxxx
bf2cvt. */
- return 3382;
+ return 3384;
}
}
}
@@ -22131,7 +22153,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x1xx0x1010001x00xxxxxxxxxx
fcvtn. */
- return 3390;
+ return 3392;
}
else
{
@@ -22139,7 +22161,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x1xx0x1010001x10xxxxxxxxxx
bfcvtn. */
- return 3389;
+ return 3391;
}
}
else
@@ -22150,7 +22172,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x1xx0x1010001x01xxxxxxxxxx
fcvtnb. */
- return 3391;
+ return 3393;
}
else
{
@@ -22158,7 +22180,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x1xx0x1010001x11xxxxxxxxxx
fcvtnt. */
- return 3392;
+ return 3394;
}
}
}
@@ -22219,7 +22241,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x1xx0x1001001x00xxxxxxxxxx
f1cvtlt. */
- return 3387;
+ return 3389;
}
else
{
@@ -22227,7 +22249,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x1xx0x1001001x10xxxxxxxxxx
bf1cvtlt. */
- return 3383;
+ return 3385;
}
}
else
@@ -22238,7 +22260,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x1xx0x1001001x01xxxxxxxxxx
f2cvtlt. */
- return 3388;
+ return 3390;
}
else
{
@@ -22246,7 +22268,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x1xx0x1001001x11xxxxxxxxxx
bf2cvtlt. */
- return 3384;
+ return 3386;
}
}
}
@@ -23572,7 +23594,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
101001x10x01xxxx111xxxxxxxxxxxxx
ld3q. */
- return 3356;
+ return 3358;
}
else
{
@@ -23580,7 +23602,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
101001x11x01xxxx111xxxxxxxxxxxxx
ld4q. */
- return 3357;
+ return 3359;
}
}
}
@@ -24753,7 +24775,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
101001x10x1xxxxx100xxxxxxxxxxxxx
ld3q. */
- return 3359;
+ return 3361;
}
else
{
@@ -24761,7 +24783,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
101001x11x1xxxxx100xxxxxxxxxxxxx
ld4q. */
- return 3360;
+ return 3362;
}
}
else
@@ -26826,29 +26848,29 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
0x001110100xxxxxxxx100xxxxxxxxxx
luti2. */
- return 3419;
- }
- }
- }
- else
- {
- if (((word >> 23) & 0x1) == 0)
- {
- if (((word >> 12) & 0x1) == 0)
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- 0x001110010xxxxxxxx000xxxxxxxxxx
- luti4. */
return 3421;
}
+ }
+ }
+ else
+ {
+ if (((word >> 23) & 0x1) == 0)
+ {
+ if (((word >> 12) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 0x001110010xxxxxxxx000xxxxxxxxxx
+ luti4. */
+ return 3423;
+ }
else
{
/* 33222222222211111111110000000000
10987654321098765432109876543210
0x001110010xxxxxxxx100xxxxxxxxxx
luti4. */
- return 3422;
+ return 3424;
}
}
else
@@ -26857,7 +26879,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
0x001110110xxxxxxxxx00xxxxxxxxxx
luti2. */
- return 3420;
+ return 3422;
}
}
}
@@ -26973,7 +26995,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
00001110x00xxxxxx10001xxxxxxxxxx
fmlallbb. */
- return 3443;
+ return 3445;
}
else
{
@@ -26981,7 +27003,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
01001110x00xxxxxx10001xxxxxxxxxx
fmlalltb. */
- return 3445;
+ return 3447;
}
}
else
@@ -26992,7 +27014,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
00001110x10xxxxxx10001xxxxxxxxxx
fmlallbt. */
- return 3444;
+ return 3446;
}
else
{
@@ -27000,7 +27022,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
01001110x10xxxxxx10001xxxxxxxxxx
fmlalltt. */
- return 3446;
+ return 3448;
}
}
}
@@ -27088,7 +27110,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
00001110x00xxxxxx11101xxxxxxxxxx
fcvtn. */
- return 3376;
+ return 3378;
}
else
{
@@ -27096,7 +27118,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
01001110x00xxxxxx11101xxxxxxxxxx
fcvtn2. */
- return 3377;
+ return 3379;
}
}
else
@@ -27105,7 +27127,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
0x001110x10xxxxxx11101xxxxxxxxxx
fcvtn. */
- return 3378;
+ return 3380;
}
}
}
@@ -27248,7 +27270,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
0x001110x00xxxxxx11111xxxxxxxxxx
fdot. */
- return 3435;
+ return 3437;
}
else
{
@@ -27258,7 +27280,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
0x001110010xxxxxx11111xxxxxxxxxx
fdot. */
- return 3437;
+ return 3439;
}
else
{
@@ -27268,7 +27290,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
00001110110xxxxxx11111xxxxxxxxxx
fmlalb. */
- return 3439;
+ return 3441;
}
else
{
@@ -27276,7 +27298,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
01001110110xxxxxx11111xxxxxxxxxx
fmlalt. */
- return 3440;
+ return 3442;
}
}
}
@@ -27550,7 +27572,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx101110110xxxxx0x1111xxxxxxxxxx
fscale. */
- return 3379;
+ return 3381;
}
}
}
@@ -28942,7 +28964,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x0101110001xxxx1011110xxxxxxxxxx
f1cvtl. */
- return 3372;
+ return 3374;
}
else
{
@@ -28950,7 +28972,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1101110001xxxx1011110xxxxxxxxxx
f1cvtl2. */
- return 3373;
+ return 3375;
}
}
else
@@ -28961,7 +28983,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x0101110101xxxx1011110xxxxxxxxxx
bf1cvtl. */
- return 3368;
+ return 3370;
}
else
{
@@ -28969,7 +28991,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1101110101xxxx1011110xxxxxxxxxx
bf1cvtl2. */
- return 3369;
+ return 3371;
}
}
}
@@ -28983,7 +29005,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x0101110011xxxx1011110xxxxxxxxxx
f2cvtl. */
- return 3374;
+ return 3376;
}
else
{
@@ -28991,7 +29013,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1101110011xxxx1011110xxxxxxxxxx
f2cvtl2. */
- return 3375;
+ return 3377;
}
}
else
@@ -29002,7 +29024,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x0101110111xxxx1011110xxxxxxxxxx
bf2cvtl. */
- return 3370;
+ return 3372;
}
else
{
@@ -29010,7 +29032,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1101110111xxxx1011110xxxxxxxxxx
bf2cvtl2. */
- return 3371;
+ return 3373;
}
}
}
@@ -31009,7 +31031,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx1011101x1xxxxx111111xxxxxxxxxx
fscale. */
- return 3380;
+ return 3382;
}
}
}
@@ -32725,7 +32747,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx00111100xxxxxx0000x0xxxxxxxxxx
fdot. */
- return 3436;
+ return 3438;
}
else
{
@@ -32755,7 +32777,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx00111101xxxxxx0000x0xxxxxxxxxx
fdot. */
- return 3438;
+ return 3440;
}
else
{
@@ -32765,7 +32787,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x000111111xxxxxx0000x0xxxxxxxxxx
fmlalb. */
- return 3441;
+ return 3443;
}
else
{
@@ -32773,7 +32795,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x100111111xxxxxx0000x0xxxxxxxxxx
fmlalt. */
- return 3442;
+ return 3444;
}
}
}
@@ -33315,16 +33337,16 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x010111100xxxxxx1000x0xxxxxxxxxx
fmlallbb. */
- return 3447;
- }
- else
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- x110111100xxxxxx1000x0xxxxxxxxxx
- fmlalltb. */
return 3449;
}
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x110111100xxxxxx1000x0xxxxxxxxxx
+ fmlalltb. */
+ return 3451;
+ }
}
else
{
@@ -33354,16 +33376,16 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x0101111x1xxxxxx1000x0xxxxxxxxxx
fmlallbt. */
- return 3448;
- }
- else
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- x1101111x1xxxxxx1000x0xxxxxxxxxx
- fmlalltt. */
return 3450;
}
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x1101111x1xxxxxx1000x0xxxxxxxxxx
+ fmlalltt. */
+ return 3452;
+ }
}
}
}
^ permalink raw reply [flat|nested] 12+ messages in thread* [PATCH v1 4/7] aarch64: Add support for FEAT_SME_F16F16 fmla and fmls instructions.
2024-07-12 16:35 [PATCH v1 0/7][Binutils] aarch64: Add support for FEAT_SME_F16F16 feature and instructions Srinath Parvathaneni
` (2 preceding siblings ...)
2024-07-12 16:35 ` [PATCH v1 3/7] aarch64: Add support for FEAT_SME_F16F16 fmopa and fmops instructions (regenerated files) Srinath Parvathaneni
@ 2024-07-12 16:35 ` Srinath Parvathaneni
2024-08-16 16:20 ` Andrew Carlotti
2024-07-12 16:35 ` [PATCH v1 5/7] aarch64: Add support for FEAT_SME_F16F16 fmla and fmls instructions (regenerated files) Srinath Parvathaneni
` (3 subsequent siblings)
7 siblings, 1 reply; 12+ messages in thread
From: Srinath Parvathaneni @ 2024-07-12 16:35 UTC (permalink / raw)
To: binutils; +Cc: richard.earnshaw, nickc, Srinath Parvathaneni
[-- Attachment #1: Type: text/plain, Size: 998 bytes --]
This patch adds support for FEAT_SME_F16F16 instructions fmla and fmls,
which are available on passing command line flags +sme-f16f16 and the
spec is available here[1].
[1]: https://developer.arm.com/documentation/ddi0602/2024-06/SME-Instructions?lang=en
---
gas/testsuite/gas/aarch64/sme-f16f16-3-bad.d | 4 +
gas/testsuite/gas/aarch64/sme-f16f16-3-bad.l | 141 +++++++++++++++++++
gas/testsuite/gas/aarch64/sme-f16f16-3-bad.s | 133 +++++++++++++++++
gas/testsuite/gas/aarch64/sme-f16f16-3.d | 98 +++++++++++++
gas/testsuite/gas/aarch64/sme-f16f16-3.s | 105 ++++++++++++++
opcodes/aarch64-tbl.h | 12 ++
6 files changed, 493 insertions(+)
create mode 100644 gas/testsuite/gas/aarch64/sme-f16f16-3-bad.d
create mode 100644 gas/testsuite/gas/aarch64/sme-f16f16-3-bad.l
create mode 100644 gas/testsuite/gas/aarch64/sme-f16f16-3-bad.s
create mode 100644 gas/testsuite/gas/aarch64/sme-f16f16-3.d
create mode 100644 gas/testsuite/gas/aarch64/sme-f16f16-3.s
[-- Warning: decoded text below may be mangled, UTF-8 assumed --]
[-- Attachment #2: v1-0004-aarch64-Add-support-for-FEAT_SME_F16F16-fmla-and-.patch --]
[-- Type: text/x-patch; name="v1-0004-aarch64-Add-support-for-FEAT_SME_F16F16-fmla-and-.patch", Size: 32780 bytes --]
diff --git a/gas/testsuite/gas/aarch64/sme-f16f16-3-bad.d b/gas/testsuite/gas/aarch64/sme-f16f16-3-bad.d
new file mode 100644
index 00000000000..a10f9c06be2
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sme-f16f16-3-bad.d
@@ -0,0 +1,4 @@
+#name: Test of invalid FEAT_SME_F16F16 fmla and fmls instructions.
+#as: -march=armv9.4-a+sme-f16f16
+#source: sme-f16f16-3-bad.s
+#error_output: sme-f16f16-3-bad.l
diff --git a/gas/testsuite/gas/aarch64/sme-f16f16-3-bad.l b/gas/testsuite/gas/aarch64/sme-f16f16-3-bad.l
new file mode 100644
index 00000000000..2ba361d40be
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sme-f16f16-3-bad.l
@@ -0,0 +1,141 @@
+.*: Assembler messages:
+.*: Error: invalid vector group size at operand 1 -- `fmla za.s\[w8,0,vgx3\],{z0.h-z1.h},z0.h\[0\]'
+.*: Error: invalid vector group size at operand 1 -- `fmla za.h\[w14,0,vgx3\],{z10.h-z1.h},z0.h\[0\]'
+.*: Error: invalid vector group size at operand 1 -- `fmla za.h\[w8,15,vgx3\],{z0.h-z1.h},z0.h\[0\]'
+.*: Error: invalid vector group size at operand 1 -- `fmla za.d\[w8,0,vgx3\],{z30.h-z31.h},z0.h\[0\]'
+.*: Error: invalid vector group size at operand 1 -- `fmla za.h\[w8,0,vgx3\],{z0.h-z1.h},z15.h\[0\]'
+.*: Error: invalid vector group size at operand 1 -- `fmla za.h\[w8,0,vgx3\],{z0.h-z1.h},z0.h\[7\]'
+.*: Error: expected a list of 2 registers at operand 2 -- `fmla za.h\[w8,0,vgx2\],{z0.h},z0.h\[7\]'
+.*: Error: expected a list of 2 registers at operand 2 -- `fmla za.h\[w8,0,vgx2\],{z0.h},z0.h'
+.*: Error: missing type suffix at operand 2 -- `fmla za.h\[w8,0,vgx2\],{z0-z1},z0.h\[7\]'
+.*: Error: missing type suffix at operand 2 -- `fmla za.h\[w8,0,vgx2\],{z0-z1}'
+.*: Error: invalid vector group size at operand 1 -- `fmla za.b\[w8,0,vgx1\],{z0.h-z1.h},z0.h\[0\]'
+.*: Error: invalid vector group size at operand 1 -- `fmla za.h\[w14,0,vgx1\],{z10.h-z1.h},z0.h\[0\]'
+.*: Error: invalid vector group size at operand 1 -- `fmla za.h\[w8,15,vgx1\],{z0.h-z1.h},z0.h\[0\]'
+.*: Error: invalid vector group size at operand 1 -- `fmla za.h\[w8,0,vgx1\],{z30.h-z31.h},z0.h\[0\]'
+.*: Error: invalid vector group size at operand 1 -- `fmla za.s\[w8,0,vgx1\],{z0.h-z1.h},z15.h\[0\]'
+.*: Error: invalid vector group size at operand 1 -- `fmla za.h\[w8,0,vgx1\],{z0.h-z1.h},z0.h\[7\]'
+.*: Error: expected a list of 4 registers at operand 2 -- `fmla za.h\[w8,0,vgx4\],{z0.h},z0.h\[7\]'
+.*: Error: expected a list of 4 registers at operand 2 -- `fmla za.h\[w8,0,vgx4\],{z0.h},z0.h'
+.*: Error: missing type suffix at operand 2 -- `fmla za.h\[w8,0,vgx4\],{z0-z1},z0.h\[7\]'
+.*: Error: missing type suffix at operand 2 -- `fmla za.h\[w8,0,vgx4\],{z0-z1}'
+.*: Error: invalid vector group size at operand 1 -- `fmla za.s\[w8,0,vgx3\],{z0.h-z1.h},z0.h'
+.*: Error: invalid vector group size at operand 1 -- `fmla za.h\[w14,0,vgx3\],{z10.h-z1.h},z0.h'
+.*: Error: invalid vector group size at operand 1 -- `fmla za.h\[w8,15,vgx3\],{z0.h-z1.h},z0.h'
+.*: Error: invalid vector group size at operand 1 -- `fmla za.d\[w8,0,vgx3\],{z31.h-z0.h},z0.h'
+.*: Error: invalid vector group size at operand 1 -- `fmla za.h\[w8,0,vgx3\],{z0.h-z1.h},z15.h'
+.*: Error: expected a list of 2 registers at operand 2 -- `fmla za.h\[w8,0,vgx2\],{z0.h},z15.h'
+.*: Error: operand mismatch -- `fmla za.h\[w8,0,vgx2\],{z0.h-z1.h},z15'
+.*: Info: did you mean this\?
+.*: Info: fmla za.h\[w8, 0, vgx2\], {z0.h-z1.h}, z15.h
+.*: Error: operand mismatch -- `fmla za.h\[w8,0,vgx2\],{z0.h-z1.h},z20'
+.*: Info: did you mean this\?
+.*: Info: fmla za.h\[w8, 0, vgx2\], {z0.h-z1.h}, z20.h
+.*: Error: comma expected between operands at operand 3 -- `fmla za.h\[w8,0,vgx2\],{z0.h-z1.h}'
+.*: Error: invalid vector group size at operand 1 -- `fmla za.h\[w8,0,vgx1\],{z0.h-z1.h},z0.h'
+.*: Error: invalid vector group size at operand 1 -- `fmla za.s\[w14,0,vgx1\],{z10.h-z1.h},z0.h'
+.*: Error: invalid vector group size at operand 1 -- `fmla za.h\[w8,15,vgx1\],{z0.h-z1.h},z0.h'
+.*: Error: invalid vector group size at operand 1 -- `fmla za.h\[w8,0,vgx1\],{z31.h-z2.h},z0.h'
+.*: Error: invalid vector group size at operand 1 -- `fmla za.b\[w8,0,vgx1\],{z0.h-z1.h},z15.h'
+.*: Error: expected a list of 4 registers at operand 2 -- `fmla za.h\[w8,0,vgx4\],{z0.h},z15.h'
+.*: Error: operand mismatch -- `fmla za.h\[w8,0,vgx4\],{z0.h-z1.h},z15'
+.*: Info: did you mean this\?
+.*: Info: fmla za.h\[w8, 0, vgx4\], {z0.h-z1.h}, z15.h
+.*: Error: operand mismatch -- `fmla za.h\[w8,0,vgx4\],{z0.h-z1.h},z20'
+.*: Info: did you mean this\?
+.*: Info: fmla za.h\[w8, 0, vgx4\], {z0.h-z1.h}, z20.h
+.*: Error: comma expected between operands at operand 3 -- `fmla za.h\[w8,0,vgx4\],{z0.h-z1.h}'
+.*: Error: invalid vector group size at operand 1 -- `fmla za.s\[w8,0,vgx3\],{z0.h-z1.h},{z0.h-z1.h}'
+.*: Error: invalid vector group size at operand 1 -- `fmla za.h\[w14,0,vgx3\],{z10.h-z1.h},{z0.h-z1.h}'
+.*: Error: invalid vector group size at operand 1 -- `fmla za.d\[w8,15,vgx3\],{z0.h-z1.h},{z0.h-z1.h}'
+.*: Error: invalid vector group size at operand 1 -- `fmla za.h\[w8,0,vgx3\],{z30.h-z31.h},{z0.h-z1.h}'
+.*: Error: invalid vector group size at operand 1 -- `fmla za.b\[w8,0,vgx3\],{z0.h-z1.h},{z30.h-z31.h}'
+.*: Error: expected a list of 2 registers at operand 2 -- `fmla za.h\[w8,0,vgx2\],{z0.h},{z30.h-z31.h}'
+.*: Error: expected a list of 2 registers at operand 3 -- `fmla za.h\[w8,0,vgx2\],{z0.h-z1.h},{z30.h}'
+.*: Error: expected a list of 2 registers at operand 2 -- `fmla za.h\[w8,0,vgx2\],{z0.h},{z30.h}'
+.*: Error: expected a list of 2 registers at operand 2 -- `fmla za.h\[w8,0,vgx2\],{z0.h},{z30.h}'
+.*: Error: operand mismatch -- `fmla za.b\[w8,20,vgx2\],{z0.h},{z30.h}'
+.*: Info: did you mean this\?
+.*: Info: fmla za.h\[w8, 20, vgx2\], {z0.h}, {z30.h}
+.*: Error: invalid vector group size at operand 1 -- `fmla za.s\[w8,0,vgx1\],{z0.h-z1.h},{z0.h-z3.h}'
+.*: Error: invalid vector group size at operand 1 -- `fmla za.h\[w14,0,vgx1\],{z10.h-z1.h},{z0.h-z3.h}'
+.*: Error: invalid vector group size at operand 1 -- `fmla za.s\[w8,15,vgx1\],{z0.h-z1.h},{z0.h-z3.h}'
+.*: Error: invalid vector group size at operand 1 -- `fmla za.h\[w8,0,vgx1\],{z30.h-z31.h},{z0.h-z1.h}'
+.*: Error: invalid vector group size at operand 1 -- `fmla za.b\[w8,0,vgx1\],{z0.h-z1.h},{z30.h-z31.h}'
+.*: Error: expected a list of 4 registers at operand 2 -- `fmla za.h\[w8,0,vgx4\],{z0.h},{z30.h-z31.h}'
+.*: Error: expected a list of 4 registers at operand 2 -- `fmla za.h\[w8,0,vgx4\],{z0.h-z1.h},{z30.h}'
+.*: Error: expected a list of 4 registers at operand 2 -- `fmla za.h\[w8,0,vgx4\],{z0.h},{z30.h}'
+.*: Error: expected a list of 4 registers at operand 2 -- `fmla za.h\[w8,0,vgx4\],{z0.h},{z30.h}'
+.*: Error: operand mismatch -- `fmla za.b\[w8,20,vgx4\],{z0.h},{z30.h}'
+.*: Info: did you mean this\?
+.*: Info: fmla za.h\[w8, 20, vgx4\], {z0.h}, {z30.h}
+.*: Error: invalid vector group size at operand 1 -- `fmls za.s\[w8,0,vgx3\],{z0.h-z1.h},z0.h\[0\]'
+.*: Error: invalid vector group size at operand 1 -- `fmls za.h\[w14,0,vgx3\],{z10.h-z1.h},z0.h\[0\]'
+.*: Error: invalid vector group size at operand 1 -- `fmls za.h\[w8,15,vgx3\],{z0.h-z1.h},z0.h\[0\]'
+.*: Error: invalid vector group size at operand 1 -- `fmls za.d\[w8,0,vgx3\],{z30.h-z31.h},z0.h\[0\]'
+.*: Error: invalid vector group size at operand 1 -- `fmls za.h\[w8,0,vgx3\],{z0.h-z1.h},z15.h\[0\]'
+.*: Error: invalid vector group size at operand 1 -- `fmls za.h\[w8,0,vgx3\],{z0.h-z1.h},z0.h\[7\]'
+.*: Error: expected a list of 2 registers at operand 2 -- `fmls za.h\[w8,0,vgx2\],{z0.h},z0.h\[7\]'
+.*: Error: expected a list of 2 registers at operand 2 -- `fmls za.h\[w8,0,vgx2\],{z0.h},z0.h'
+.*: Error: missing type suffix at operand 2 -- `fmls za.h\[w8,0,vgx2\],{z0-z1},z0.h\[7\]'
+.*: Error: missing type suffix at operand 2 -- `fmls za.h\[w8,0,vgx2\],{z0-z1}'
+.*: Error: invalid vector group size at operand 1 -- `fmls za.b\[w8,0,vgx1\],{z0.h-z1.h},z0.h\[0\]'
+.*: Error: invalid vector group size at operand 1 -- `fmls za.h\[w14,0,vgx1\],{z10.h-z1.h},z0.h\[0\]'
+.*: Error: invalid vector group size at operand 1 -- `fmls za.h\[w8,15,vgx1\],{z0.h-z1.h},z0.h\[0\]'
+.*: Error: invalid vector group size at operand 1 -- `fmls za.h\[w8,0,vgx1\],{z30.h-z31.h},z0.h\[0\]'
+.*: Error: invalid vector group size at operand 1 -- `fmls za.s\[w8,0,vgx1\],{z0.h-z1.h},z15.h\[0\]'
+.*: Error: invalid vector group size at operand 1 -- `fmls za.h\[w8,0,vgx1\],{z0.h-z1.h},z0.h\[7\]'
+.*: Error: expected a list of 4 registers at operand 2 -- `fmls za.h\[w8,0,vgx4\],{z0.h},z0.h\[7\]'
+.*: Error: expected a list of 4 registers at operand 2 -- `fmls za.h\[w8,0,vgx4\],{z0.h},z0.h'
+.*: Error: missing type suffix at operand 2 -- `fmls za.h\[w8,0,vgx4\],{z0-z1},z0.h\[7\]'
+.*: Error: missing type suffix at operand 2 -- `fmls za.h\[w8,0,vgx4\],{z0-z1}'
+.*: Error: invalid vector group size at operand 1 -- `fmls za.s\[w8,0,vgx3\],{z0.h-z1.h},z0.h'
+.*: Error: invalid vector group size at operand 1 -- `fmls za.h\[w14,0,vgx3\],{z10.h-z1.h},z0.h'
+.*: Error: invalid vector group size at operand 1 -- `fmls za.h\[w8,15,vgx3\],{z0.h-z1.h},z0.h'
+.*: Error: invalid vector group size at operand 1 -- `fmls za.d\[w8,0,vgx3\],{z31.h-z0.h},z0.h'
+.*: Error: invalid vector group size at operand 1 -- `fmls za.h\[w8,0,vgx3\],{z0.h-z1.h},z15.h'
+.*: Error: expected a list of 2 registers at operand 2 -- `fmls za.h\[w8,0,vgx2\],{z0.h},z15.h'
+.*: Error: operand mismatch -- `fmls za.h\[w8,0,vgx2\],{z0.h-z1.h},z15'
+.*: Info: did you mean this\?
+.*: Info: fmls za.h\[w8, 0, vgx2\], {z0.h-z1.h}, z15.h
+.*: Error: operand mismatch -- `fmls za.h\[w8,0,vgx2\],{z0.h-z1.h},z20'
+.*: Info: did you mean this\?
+.*: Info: fmls za.h\[w8, 0, vgx2\], {z0.h-z1.h}, z20.h
+.*: Error: comma expected between operands at operand 3 -- `fmls za.h\[w8,0,vgx2\],{z0.h-z1.h}'
+.*: Error: invalid vector group size at operand 1 -- `fmls za.h\[w8,0,vgx1\],{z0.h-z1.h},z0.h'
+.*: Error: invalid vector group size at operand 1 -- `fmls za.s\[w14,0,vgx1\],{z10.h-z1.h},z0.h'
+.*: Error: invalid vector group size at operand 1 -- `fmls za.h\[w8,15,vgx1\],{z0.h-z1.h},z0.h'
+.*: Error: invalid vector group size at operand 1 -- `fmls za.h\[w8,0,vgx1\],{z31.h-z2.h},z0.h'
+.*: Error: invalid vector group size at operand 1 -- `fmls za.b\[w8,0,vgx1\],{z0.h-z1.h},z15.h'
+.*: Error: expected a list of 4 registers at operand 2 -- `fmls za.h\[w8,0,vgx4\],{z0.h},z15.h'
+.*: Error: operand mismatch -- `fmls za.h\[w8,0,vgx4\],{z0.h-z1.h},z15'
+.*: Info: did you mean this\?
+.*: Info: fmls za.h\[w8, 0, vgx4\], {z0.h-z1.h}, z15.h
+.*: Error: operand mismatch -- `fmls za.h\[w8,0,vgx4\],{z0.h-z1.h},z20'
+.*: Info: did you mean this\?
+.*: Info: fmls za.h\[w8, 0, vgx4\], {z0.h-z1.h}, z20.h
+.*: Error: comma expected between operands at operand 3 -- `fmls za.h\[w8,0,vgx4\],{z0.h-z1.h}'
+.*: Error: invalid vector group size at operand 1 -- `fmls za.s\[w8,0,vgx3\],{z0.h-z1.h},{z0.h-z1.h}'
+.*: Error: invalid vector group size at operand 1 -- `fmls za.h\[w14,0,vgx3\],{z10.h-z1.h},{z0.h-z1.h}'
+.*: Error: invalid vector group size at operand 1 -- `fmls za.d\[w8,15,vgx3\],{z0.h-z1.h},{z0.h-z1.h}'
+.*: Error: invalid vector group size at operand 1 -- `fmls za.h\[w8,0,vgx3\],{z30.h-z31.h},{z0.h-z1.h}'
+.*: Error: invalid vector group size at operand 1 -- `fmls za.b\[w8,0,vgx3\],{z0.h-z1.h},{z30.h-z31.h}'
+.*: Error: expected a list of 2 registers at operand 2 -- `fmls za.h\[w8,0,vgx2\],{z0.h},{z30.h-z31.h}'
+.*: Error: expected a list of 2 registers at operand 3 -- `fmls za.h\[w8,0,vgx2\],{z0.h-z1.h},{z30.h}'
+.*: Error: expected a list of 2 registers at operand 2 -- `fmls za.h\[w8,0,vgx2\],{z0.h},{z30.h}'
+.*: Error: expected a list of 2 registers at operand 2 -- `fmls za.h\[w8,0,vgx2\],{z0.h},{z30.h}'
+.*: Error: operand mismatch -- `fmls za.b\[w8,20,vgx2\],{z0.h},{z30.h}'
+.*: Info: did you mean this\?
+.*: Info: fmls za.h\[w8, 20, vgx2\], {z0.h}, {z30.h}
+.*: Error: invalid vector group size at operand 1 -- `fmls za.s\[w8,0,vgx1\],{z0.h-z1.h},{z0.h-z3.h}'
+.*: Error: invalid vector group size at operand 1 -- `fmls za.h\[w14,0,vgx1\],{z10.h-z1.h},{z0.h-z3.h}'
+.*: Error: invalid vector group size at operand 1 -- `fmls za.s\[w8,15,vgx1\],{z0.h-z1.h},{z0.h-z3.h}'
+.*: Error: invalid vector group size at operand 1 -- `fmls za.h\[w8,0,vgx1\],{z30.h-z31.h},{z0.h-z1.h}'
+.*: Error: invalid vector group size at operand 1 -- `fmls za.b\[w8,0,vgx1\],{z0.h-z1.h},{z30.h-z31.h}'
+.*: Error: expected a list of 4 registers at operand 2 -- `fmls za.h\[w8,0,vgx4\],{z0.h},{z30.h-z31.h}'
+.*: Error: expected a list of 4 registers at operand 2 -- `fmls za.h\[w8,0,vgx4\],{z0.h-z1.h},{z30.h}'
+.*: Error: expected a list of 4 registers at operand 2 -- `fmls za.h\[w8,0,vgx4\],{z0.h},{z30.h}'
+.*: Error: expected a list of 4 registers at operand 2 -- `fmls za.h\[w8,0,vgx4\],{z0.h},{z30.h}'
+.*: Error: operand mismatch -- `fmls za.b\[w8,20,vgx4\],{z0.h},{z30.h}'
+.*: Info: did you mean this\?
+.*: Info: fmls za.h\[w8, 20, vgx4\], {z0.h}, {z30.h}
diff --git a/gas/testsuite/gas/aarch64/sme-f16f16-3-bad.s b/gas/testsuite/gas/aarch64/sme-f16f16-3-bad.s
new file mode 100644
index 00000000000..40d1efa8510
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sme-f16f16-3-bad.s
@@ -0,0 +1,133 @@
+/* FMLA (multiple and indexed vector). */
+fmla za.s[w8, 0, vgx3], {z0.h - z1.h}, z0.h[0]
+fmla za.h[w14, 0, vgx3], {z10.h - z1.h}, z0.h[0]
+fmla za.h[w8, 15, vgx3], {z0.h - z1.h}, z0.h[0]
+fmla za.d[w8, 0, vgx3], {z30.h - z31.h}, z0.h[0]
+fmla za.h[w8, 0, vgx3], {z0.h - z1.h}, z15.h[0]
+fmla za.h[w8, 0, vgx3], {z0.h - z1.h}, z0.h[7]
+fmla za.h[w8, 0, vgx2], {z0.h}, z0.h[7]
+fmla za.h[w8, 0, vgx2], {z0.h}, z0.h
+fmla za.h[w8, 0, vgx2], {z0 - z1}, z0.h[7]
+fmla za.h[w8, 0, vgx2], {z0 - z1}
+
+fmla za.b[w8, 0, vgx1], {z0.h - z1.h}, z0.h[0]
+fmla za.h[w14, 0, vgx1], {z10.h - z1.h}, z0.h[0]
+fmla za.h[w8, 15, vgx1], {z0.h - z1.h}, z0.h[0]
+fmla za.h[w8, 0, vgx1], {z30.h - z31.h}, z0.h[0]
+fmla za.s[w8, 0, vgx1], {z0.h - z1.h}, z15.h[0]
+fmla za.h[w8, 0, vgx1], {z0.h - z1.h}, z0.h[7]
+fmla za.h[w8, 0, vgx4], {z0.h}, z0.h[7]
+fmla za.h[w8, 0, vgx4], {z0.h}, z0.h
+fmla za.h[w8, 0, vgx4], {z0 - z1}, z0.h[7]
+fmla za.h[w8, 0, vgx4], {z0 - z1}
+
+/* FMLA (multiple and single vector). */
+fmla za.s[w8, 0, vgx3], {z0.h - z1.h}, z0.h
+fmla za.h[w14, 0, vgx3], {z10.h - z1.h}, z0.h
+fmla za.h[w8, 15, vgx3], {z0.h - z1.h}, z0.h
+fmla za.d[w8, 0, vgx3], {z31.h - z0.h}, z0.h
+fmla za.h[w8, 0, vgx3], {z0.h - z1.h}, z15.h
+fmla za.h[w8, 0, vgx2], {z0.h}, z15.h
+fmla za.h[w8, 0, vgx2], {z0.h -z1.h}, z15
+fmla za.h[w8, 0, vgx2], {z0.h -z1.h}, z20
+fmla za.h[w8, 0, vgx2], {z0.h -z1.h}
+
+fmla za.h[w8, 0, vgx1], {z0.h - z1.h}, z0.h
+fmla za.s[w14, 0, vgx1], {z10.h - z1.h}, z0.h
+fmla za.h[w8, 15, vgx1], {z0.h - z1.h}, z0.h
+fmla za.h[w8, 0, vgx1], {z31.h - z2.h}, z0.h
+fmla za.b[w8, 0, vgx1], {z0.h - z1.h}, z15.h
+fmla za.h[w8, 0, vgx4], {z0.h}, z15.h
+fmla za.h[w8, 0, vgx4], {z0.h -z1.h}, z15
+fmla za.h[w8, 0, vgx4], {z0.h -z1.h}, z20
+fmla za.h[w8, 0, vgx4], {z0.h -z1.h}
+
+/* FMLA (multiple vectors). */
+fmla za.s[w8, 0, vgx3], {z0.h - z1.h}, {z0.h - z1.h}
+fmla za.h[w14, 0, vgx3], {z10.h - z1.h}, {z0.h - z1.h}
+fmla za.d[w8, 15, vgx3], {z0.h - z1.h}, {z0.h - z1.h}
+fmla za.h[w8, 0, vgx3], {z30.h - z31.h}, {z0.h - z1.h}
+fmla za.b[w8, 0, vgx3], {z0.h - z1.h}, {z30.h - z31.h}
+fmla za.h[w8, 0, vgx2], {z0.h}, {z30.h - z31.h}
+fmla za.h[w8, 0, vgx2], {z0.h - z1.h}, {z30.h}
+fmla za.h[w8, 0, vgx2], {z0.h}, {z30.h}
+fmla za.h[w8, 0, vgx2], {z0.h}, {z30.h}
+fmla za.b[w8, 20, vgx2], {z0.h}, {z30.h}
+
+fmla za.s[w8, 0, vgx1], {z0.h - z1.h}, {z0.h - z3.h}
+fmla za.h[w14, 0, vgx1], {z10.h - z1.h}, {z0.h - z3.h}
+fmla za.s[w8, 15, vgx1], {z0.h - z1.h}, {z0.h - z3.h}
+fmla za.h[w8, 0, vgx1], {z30.h - z31.h}, {z0.h - z1.h}
+fmla za.b[w8, 0, vgx1], {z0.h - z1.h}, {z30.h - z31.h}
+fmla za.h[w8, 0, vgx4], {z0.h}, {z30.h - z31.h}
+fmla za.h[w8, 0, vgx4], {z0.h - z1.h}, {z30.h}
+fmla za.h[w8, 0, vgx4], {z0.h}, {z30.h}
+fmla za.h[w8, 0, vgx4], {z0.h}, {z30.h}
+fmla za.b[w8, 20, vgx4], {z0.h}, {z30.h}
+
+/* FMLS (multiple and indexed vector). */
+fmls za.s[w8, 0, vgx3], {z0.h - z1.h}, z0.h[0]
+fmls za.h[w14, 0, vgx3], {z10.h - z1.h}, z0.h[0]
+fmls za.h[w8, 15, vgx3], {z0.h - z1.h}, z0.h[0]
+fmls za.d[w8, 0, vgx3], {z30.h - z31.h}, z0.h[0]
+fmls za.h[w8, 0, vgx3], {z0.h - z1.h}, z15.h[0]
+fmls za.h[w8, 0, vgx3], {z0.h - z1.h}, z0.h[7]
+fmls za.h[w8, 0, vgx2], {z0.h}, z0.h[7]
+fmls za.h[w8, 0, vgx2], {z0.h}, z0.h
+fmls za.h[w8, 0, vgx2], {z0 - z1}, z0.h[7]
+fmls za.h[w8, 0, vgx2], {z0 - z1}
+
+fmls za.b[w8, 0, vgx1], {z0.h - z1.h}, z0.h[0]
+fmls za.h[w14, 0, vgx1], {z10.h - z1.h}, z0.h[0]
+fmls za.h[w8, 15, vgx1], {z0.h - z1.h}, z0.h[0]
+fmls za.h[w8, 0, vgx1], {z30.h - z31.h}, z0.h[0]
+fmls za.s[w8, 0, vgx1], {z0.h - z1.h}, z15.h[0]
+fmls za.h[w8, 0, vgx1], {z0.h - z1.h}, z0.h[7]
+fmls za.h[w8, 0, vgx4], {z0.h}, z0.h[7]
+fmls za.h[w8, 0, vgx4], {z0.h}, z0.h
+fmls za.h[w8, 0, vgx4], {z0 - z1}, z0.h[7]
+fmls za.h[w8, 0, vgx4], {z0 - z1}
+
+/* FMLS (multiple and single vector). */
+fmls za.s[w8, 0, vgx3], {z0.h - z1.h}, z0.h
+fmls za.h[w14, 0, vgx3], {z10.h - z1.h}, z0.h
+fmls za.h[w8, 15, vgx3], {z0.h - z1.h}, z0.h
+fmls za.d[w8, 0, vgx3], {z31.h - z0.h}, z0.h
+fmls za.h[w8, 0, vgx3], {z0.h - z1.h}, z15.h
+fmls za.h[w8, 0, vgx2], {z0.h}, z15.h
+fmls za.h[w8, 0, vgx2], {z0.h -z1.h}, z15
+fmls za.h[w8, 0, vgx2], {z0.h -z1.h}, z20
+fmls za.h[w8, 0, vgx2], {z0.h -z1.h}
+
+fmls za.h[w8, 0, vgx1], {z0.h - z1.h}, z0.h
+fmls za.s[w14, 0, vgx1], {z10.h - z1.h}, z0.h
+fmls za.h[w8, 15, vgx1], {z0.h - z1.h}, z0.h
+fmls za.h[w8, 0, vgx1], {z31.h - z2.h}, z0.h
+fmls za.b[w8, 0, vgx1], {z0.h - z1.h}, z15.h
+fmls za.h[w8, 0, vgx4], {z0.h}, z15.h
+fmls za.h[w8, 0, vgx4], {z0.h -z1.h}, z15
+fmls za.h[w8, 0, vgx4], {z0.h -z1.h}, z20
+fmls za.h[w8, 0, vgx4], {z0.h -z1.h}
+
+/* FMLS (multiple vectors). */
+fmls za.s[w8, 0, vgx3], {z0.h - z1.h}, {z0.h - z1.h}
+fmls za.h[w14, 0, vgx3], {z10.h - z1.h}, {z0.h - z1.h}
+fmls za.d[w8, 15, vgx3], {z0.h - z1.h}, {z0.h - z1.h}
+fmls za.h[w8, 0, vgx3], {z30.h - z31.h}, {z0.h - z1.h}
+fmls za.b[w8, 0, vgx3], {z0.h - z1.h}, {z30.h - z31.h}
+fmls za.h[w8, 0, vgx2], {z0.h}, {z30.h - z31.h}
+fmls za.h[w8, 0, vgx2], {z0.h - z1.h}, {z30.h}
+fmls za.h[w8, 0, vgx2], {z0.h}, {z30.h}
+fmls za.h[w8, 0, vgx2], {z0.h}, {z30.h}
+fmls za.b[w8, 20, vgx2], {z0.h}, {z30.h}
+
+fmls za.s[w8, 0, vgx1], {z0.h - z1.h}, {z0.h - z3.h}
+fmls za.h[w14, 0, vgx1], {z10.h - z1.h}, {z0.h - z3.h}
+fmls za.s[w8, 15, vgx1], {z0.h - z1.h}, {z0.h - z3.h}
+fmls za.h[w8, 0, vgx1], {z30.h - z31.h}, {z0.h - z1.h}
+fmls za.b[w8, 0, vgx1], {z0.h - z1.h}, {z30.h - z31.h}
+fmls za.h[w8, 0, vgx4], {z0.h}, {z30.h - z31.h}
+fmls za.h[w8, 0, vgx4], {z0.h - z1.h}, {z30.h}
+fmls za.h[w8, 0, vgx4], {z0.h}, {z30.h}
+fmls za.h[w8, 0, vgx4], {z0.h}, {z30.h}
+fmls za.b[w8, 20, vgx4], {z0.h}, {z30.h}
diff --git a/gas/testsuite/gas/aarch64/sme-f16f16-3.d b/gas/testsuite/gas/aarch64/sme-f16f16-3.d
new file mode 100644
index 00000000000..0cf05f2b320
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sme-f16f16-3.d
@@ -0,0 +1,98 @@
+#name: Test of FEAT_SME_F16F16 fmla and fmls instructions.
+#as: -march=armv9.4-a+sme-f16f16
+#objdump: -dr
+
+[^:]+: file format .*
+
+
+[^:]+:
+
+[^:]+:
+.*: c1101000 fmla za.h\[w8, 0, vgx2\], {z0.h-z1.h}, z0.h\[0\]
+.*: c1107000 fmla za.h\[w11, 0, vgx2\], {z0.h-z1.h}, z0.h\[0\]
+.*: c1101007 fmla za.h\[w8, 7, vgx2\], {z0.h-z1.h}, z0.h\[0\]
+.*: c11013c0 fmla za.h\[w8, 0, vgx2\], {z30.h-z31.h}, z0.h\[0\]
+.*: c11f1000 fmla za.h\[w8, 0, vgx2\], {z0.h-z1.h}, z15.h\[0\]
+.*: c1101c08 fmla za.h\[w8, 0, vgx2\], {z0.h-z1.h}, z0.h\[7\]
+.*: c11f7fcf fmla za.h\[w11, 7, vgx2\], {z30.h-z31.h}, z15.h\[7\]
+.*: c1101c0b fmla za.h\[w8, 3, vgx2\], {z0.h-z1.h}, z0.h\[7\]
+.*: c1109000 fmla za.h\[w8, 0, vgx4\], {z0.h-z3.h}, z0.h\[0\]
+.*: c110f000 fmla za.h\[w11, 0, vgx4\], {z0.h-z3.h}, z0.h\[0\]
+.*: c1109007 fmla za.h\[w8, 7, vgx4\], {z0.h-z3.h}, z0.h\[0\]
+.*: c1109380 fmla za.h\[w8, 0, vgx4\], {z28.h-z31.h}, z0.h\[0\]
+.*: c11f9000 fmla za.h\[w8, 0, vgx4\], {z0.h-z3.h}, z15.h\[0\]
+.*: c1109c08 fmla za.h\[w8, 0, vgx4\], {z0.h-z3.h}, z0.h\[7\]
+.*: c11fff8f fmla za.h\[w11, 7, vgx4\], {z28.h-z31.h}, z15.h\[7\]
+.*: c1109c0b fmla za.h\[w8, 3, vgx4\], {z0.h-z3.h}, z0.h\[7\]
+.*: c1201c00 fmla za.h\[w8, 0, vgx2\], {z0.h-z1.h}, z0.h
+.*: c1207c00 fmla za.h\[w11, 0, vgx2\], {z0.h-z1.h}, z0.h
+.*: c1201c07 fmla za.h\[w8, 7, vgx2\], {z0.h-z1.h}, z0.h
+.*: c1201fe0 fmla za.h\[w8, 0, vgx2\], {z31.h-z0.h}, z0.h
+.*: c12f1c00 fmla za.h\[w8, 0, vgx2\], {z0.h-z1.h}, z15.h
+.*: c12f7fc7 fmla za.h\[w11, 7, vgx2\], {z30.h-z31.h}, z15.h
+.*: c12f1c03 fmla za.h\[w8, 3, vgx2\], {z0.h-z1.h}, z15.h
+.*: c1301c00 fmla za.h\[w8, 0, vgx4\], {z0.h-z3.h}, z0.h
+.*: c1307c00 fmla za.h\[w11, 0, vgx4\], {z0.h-z3.h}, z0.h
+.*: c1301c07 fmla za.h\[w8, 7, vgx4\], {z0.h-z3.h}, z0.h
+.*: c1301fe0 fmla za.h\[w8, 0, vgx4\], {z31.h-z2.h}, z0.h
+.*: c13f1c00 fmla za.h\[w8, 0, vgx4\], {z0.h-z3.h}, z15.h
+.*: c13f7f87 fmla za.h\[w11, 7, vgx4\], {z28.h-z31.h}, z15.h
+.*: c13f1c03 fmla za.h\[w8, 3, vgx4\], {z0.h-z3.h}, z15.h
+.*: c1a01008 fmla za.h\[w8, 0, vgx2\], {z0.h-z1.h}, {z0.h-z1.h}
+.*: c1a07008 fmla za.h\[w11, 0, vgx2\], {z0.h-z1.h}, {z0.h-z1.h}
+.*: c1a0100f fmla za.h\[w8, 7, vgx2\], {z0.h-z1.h}, {z0.h-z1.h}
+.*: c1a013c8 fmla za.h\[w8, 0, vgx2\], {z30.h-z31.h}, {z0.h-z1.h}
+.*: c1be1008 fmla za.h\[w8, 0, vgx2\], {z0.h-z1.h}, {z30.h-z31.h}
+.*: c1be73cf fmla za.h\[w11, 7, vgx2\], {z30.h-z31.h}, {z30.h-z31.h}
+.*: c1be100b fmla za.h\[w8, 3, vgx2\], {z0.h-z1.h}, {z30.h-z31.h}
+.*: c1a11008 fmla za.h\[w8, 0, vgx4\], {z0.h-z3.h}, {z0.h-z3.h}
+.*: c1a17008 fmla za.h\[w11, 0, vgx4\], {z0.h-z3.h}, {z0.h-z3.h}
+.*: c1a1100f fmla za.h\[w8, 7, vgx4\], {z0.h-z3.h}, {z0.h-z3.h}
+.*: c1a11388 fmla za.h\[w8, 0, vgx4\], {z28.h-z31.h}, {z0.h-z3.h}
+.*: c1bd1008 fmla za.h\[w8, 0, vgx4\], {z0.h-z3.h}, {z28.h-z31.h}
+.*: c1bd738f fmla za.h\[w11, 7, vgx4\], {z28.h-z31.h}, {z28.h-z31.h}
+.*: c1bd100b fmla za.h\[w8, 3, vgx4\], {z0.h-z3.h}, {z28.h-z31.h}
+.*: c1101010 fmls za.h\[w8, 0, vgx2\], {z0.h-z1.h}, z0.h\[0\]
+.*: c1107010 fmls za.h\[w11, 0, vgx2\], {z0.h-z1.h}, z0.h\[0\]
+.*: c1101017 fmls za.h\[w8, 7, vgx2\], {z0.h-z1.h}, z0.h\[0\]
+.*: c11013d0 fmls za.h\[w8, 0, vgx2\], {z30.h-z31.h}, z0.h\[0\]
+.*: c11f1010 fmls za.h\[w8, 0, vgx2\], {z0.h-z1.h}, z15.h\[0\]
+.*: c1101c18 fmls za.h\[w8, 0, vgx2\], {z0.h-z1.h}, z0.h\[7\]
+.*: c11f7fdf fmls za.h\[w11, 7, vgx2\], {z30.h-z31.h}, z15.h\[7\]
+.*: c1101c1b fmls za.h\[w8, 3, vgx2\], {z0.h-z1.h}, z0.h\[7\]
+.*: c1109010 fmls za.h\[w8, 0, vgx4\], {z0.h-z3.h}, z0.h\[0\]
+.*: c110f010 fmls za.h\[w11, 0, vgx4\], {z0.h-z3.h}, z0.h\[0\]
+.*: c1109017 fmls za.h\[w8, 7, vgx4\], {z0.h-z3.h}, z0.h\[0\]
+.*: c1109390 fmls za.h\[w8, 0, vgx4\], {z28.h-z31.h}, z0.h\[0\]
+.*: c11f9010 fmls za.h\[w8, 0, vgx4\], {z0.h-z3.h}, z15.h\[0\]
+.*: c1109c18 fmls za.h\[w8, 0, vgx4\], {z0.h-z3.h}, z0.h\[7\]
+.*: c11fff9f fmls za.h\[w11, 7, vgx4\], {z28.h-z31.h}, z15.h\[7\]
+.*: c1109c1b fmls za.h\[w8, 3, vgx4\], {z0.h-z3.h}, z0.h\[7\]
+.*: c1201c08 fmls za.h\[w8, 0, vgx2\], {z0.h-z1.h}, z0.h
+.*: c1207c08 fmls za.h\[w11, 0, vgx2\], {z0.h-z1.h}, z0.h
+.*: c1201c0f fmls za.h\[w8, 7, vgx2\], {z0.h-z1.h}, z0.h
+.*: c1201fe8 fmls za.h\[w8, 0, vgx2\], {z31.h-z0.h}, z0.h
+.*: c12f1c08 fmls za.h\[w8, 0, vgx2\], {z0.h-z1.h}, z15.h
+.*: c12f7fcf fmls za.h\[w11, 7, vgx2\], {z30.h-z31.h}, z15.h
+.*: c12f1c0b fmls za.h\[w8, 3, vgx2\], {z0.h-z1.h}, z15.h
+.*: c1301c08 fmls za.h\[w8, 0, vgx4\], {z0.h-z3.h}, z0.h
+.*: c1307c08 fmls za.h\[w11, 0, vgx4\], {z0.h-z3.h}, z0.h
+.*: c1301c0f fmls za.h\[w8, 7, vgx4\], {z0.h-z3.h}, z0.h
+.*: c1301fe8 fmls za.h\[w8, 0, vgx4\], {z31.h-z2.h}, z0.h
+.*: c13f1c08 fmls za.h\[w8, 0, vgx4\], {z0.h-z3.h}, z15.h
+.*: c13f7f8f fmls za.h\[w11, 7, vgx4\], {z28.h-z31.h}, z15.h
+.*: c13f1c0b fmls za.h\[w8, 3, vgx4\], {z0.h-z3.h}, z15.h
+.*: c1a01018 fmls za.h\[w8, 0, vgx2\], {z0.h-z1.h}, {z0.h-z1.h}
+.*: c1a07018 fmls za.h\[w11, 0, vgx2\], {z0.h-z1.h}, {z0.h-z1.h}
+.*: c1a0101f fmls za.h\[w8, 7, vgx2\], {z0.h-z1.h}, {z0.h-z1.h}
+.*: c1a013d8 fmls za.h\[w8, 0, vgx2\], {z30.h-z31.h}, {z0.h-z1.h}
+.*: c1be1018 fmls za.h\[w8, 0, vgx2\], {z0.h-z1.h}, {z30.h-z31.h}
+.*: c1be73df fmls za.h\[w11, 7, vgx2\], {z30.h-z31.h}, {z30.h-z31.h}
+.*: c1be101b fmls za.h\[w8, 3, vgx2\], {z0.h-z1.h}, {z30.h-z31.h}
+.*: c1a11018 fmls za.h\[w8, 0, vgx4\], {z0.h-z3.h}, {z0.h-z3.h}
+.*: c1a17018 fmls za.h\[w11, 0, vgx4\], {z0.h-z3.h}, {z0.h-z3.h}
+.*: c1a1101f fmls za.h\[w8, 7, vgx4\], {z0.h-z3.h}, {z0.h-z3.h}
+.*: c1a11398 fmls za.h\[w8, 0, vgx4\], {z28.h-z31.h}, {z0.h-z3.h}
+.*: c1bd1018 fmls za.h\[w8, 0, vgx4\], {z0.h-z3.h}, {z28.h-z31.h}
+.*: c1bd739f fmls za.h\[w11, 7, vgx4\], {z28.h-z31.h}, {z28.h-z31.h}
+.*: c1bd101b fmls za.h\[w8, 3, vgx4\], {z0.h-z3.h}, {z28.h-z31.h}
diff --git a/gas/testsuite/gas/aarch64/sme-f16f16-3.s b/gas/testsuite/gas/aarch64/sme-f16f16-3.s
new file mode 100644
index 00000000000..86e39bde65a
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sme-f16f16-3.s
@@ -0,0 +1,105 @@
+/* FMLA (multiple and indexed vector). */
+fmla za.h[w8, 0, vgx2], {z0.h - z1.h}, z0.h[0]
+fmla za.h[w11, 0, vgx2], {z0.h - z1.h}, z0.h[0]
+fmla za.h[w8, 7, vgx2], {z0.h - z1.h}, z0.h[0]
+fmla za.h[w8, 0, vgx2], {z30.h - z31.h}, z0.h[0]
+fmla za.h[w8, 0, vgx2], {z0.h - z1.h}, z15.h[0]
+fmla za.h[w8, 0, vgx2], {z0.h - z1.h}, z0.h[7]
+fmla za.h[w11, 7, vgx2], {z30.h - z31.h}, z15.h[7]
+fmla za.h[w8, 3], {z0.h - z1.h}, z0.h[7]
+
+fmla za.h[w8, 0, vgx4], {z0.h - z3.h}, z0.h[0]
+fmla za.h[w11, 0, vgx4], {z0.h - z3.h}, z0.h[0]
+fmla za.h[w8, 7, vgx4], {z0.h - z3.h}, z0.h[0]
+fmla za.h[w8, 0, vgx4], {z28.h - z31.h}, z0.h[0]
+fmla za.h[w8, 0, vgx4], {z0.h - z3.h}, z15.h[0]
+fmla za.h[w8, 0, vgx4], {z0.h - z3.h}, z0.h[7]
+fmla za.h[w11, 7, vgx4], {z28.h - z31.h}, z15.h[7]
+fmla za.h[w8, 3], {z0.h - z3.h}, z0.h[7]
+
+/* FMLA (multiple and single vector). */
+fmla za.h[w8, 0, vgx2], {z0.h - z1.h}, z0.h
+fmla za.h[w11, 0, vgx2], {z0.h - z1.h}, z0.h
+fmla za.h[w8, 7, vgx2], {z0.h - z1.h}, z0.h
+fmla za.h[w8, 0, vgx2], {z31.h - z0.h}, z0.h
+fmla za.h[w8, 0, vgx2], {z0.h - z1.h}, z15.h
+fmla za.h[w11, 7, vgx2], {z30.h - z31.h}, z15.h
+fmla za.h[w8, 3], {z0.h - z1.h}, z15.h
+
+fmla za.h[w8, 0, vgx4], {z0.h - z3.h}, z0.h
+fmla za.h[w11, 0, vgx4], {z0.h - z3.h}, z0.h
+fmla za.h[w8, 7, vgx4], {z0.h - z3.h}, z0.h
+fmla za.h[w8, 0, vgx4], {z31.h - z2.h}, z0.h
+fmla za.h[w8, 0, vgx4], {z0.h - z3.h}, z15.h
+fmla za.h[w11, 7, vgx4], {z28.h - z31.h}, z15.h
+fmla za.h[w8, 3], {z0.h - z3.h}, z15.h
+
+/* FMLA (multiple vectors). */
+fmla za.h[w8, 0, vgx2], {z0.h - z1.h}, {z0.h - z1.h}
+fmla za.h[w11, 0, vgx2], {z0.h - z1.h}, {z0.h - z1.h}
+fmla za.h[w8, 7, vgx2], {z0.h - z1.h}, {z0.h - z1.h}
+fmla za.h[w8, 0, vgx2], {z30.h - z31.h}, {z0.h - z1.h}
+fmla za.h[w8, 0, vgx2], {z0.h - z1.h}, {z30.h - z31.h}
+fmla za.h[w11, 7, vgx2], {z30.h - z31.h}, {z30.h - z31.h}
+fmla za.h[w8, 3], {z0.h - z1.h}, {z30.h - z31.h}
+
+fmla za.h[w8, 0, vgx4], {z0.h - z3.h}, {z0.h - z3.h}
+fmla za.h[w11, 0, vgx4], {z0.h - z3.h}, {z0.h - z3.h}
+fmla za.h[w8, 7, vgx4], {z0.h - z3.h}, {z0.h - z3.h}
+fmla za.h[w8, 0, vgx4], {z28.h - z31.h}, {z0.h - z3.h}
+fmla za.h[w8, 0, vgx4], {z0.h - z3.h}, {z28.h - z31.h}
+fmla za.h[w11, 7, vgx4], {z28.h - z31.h}, {z28.h - z31.h}
+fmla za.h[w8, 3], {z0.h - z3.h}, {z28.h - z31.h}
+
+/* FMLS (multiple and indexed vector). */
+fmls za.h[w8, 0, vgx2], {z0.h - z1.h}, z0.h[0]
+fmls za.h[w11, 0, vgx2], {z0.h - z1.h}, z0.h[0]
+fmls za.h[w8, 7, vgx2], {z0.h - z1.h}, z0.h[0]
+fmls za.h[w8, 0, vgx2], {z30.h - z31.h}, z0.h[0]
+fmls za.h[w8, 0, vgx2], {z0.h - z1.h}, z15.h[0]
+fmls za.h[w8, 0, vgx2], {z0.h - z1.h}, z0.h[7]
+fmls za.h[w11, 7, vgx2], {z30.h - z31.h}, z15.h[7]
+fmls za.h[w8, 3], {z0.h - z1.h}, z0.h[7]
+
+fmls za.h[w8, 0, vgx4], {z0.h - z3.h}, z0.h[0]
+fmls za.h[w11, 0, vgx4], {z0.h - z3.h}, z0.h[0]
+fmls za.h[w8, 7, vgx4], {z0.h - z3.h}, z0.h[0]
+fmls za.h[w8, 0, vgx4], {z28.h - z31.h}, z0.h[0]
+fmls za.h[w8, 0, vgx4], {z0.h - z3.h}, z15.h[0]
+fmls za.h[w8, 0, vgx4], {z0.h - z3.h}, z0.h[7]
+fmls za.h[w11, 7, vgx4], {z28.h - z31.h}, z15.h[7]
+fmls za.h[w8, 3], {z0.h - z3.h}, z0.h[7]
+
+/* FMLS (multiple and single vector). */
+fmls za.h[w8, 0, vgx2], {z0.h - z1.h}, z0.h
+fmls za.h[w11, 0, vgx2], {z0.h - z1.h}, z0.h
+fmls za.h[w8, 7, vgx2], {z0.h - z1.h}, z0.h
+fmls za.h[w8, 0, vgx2], {z31.h - z0.h}, z0.h
+fmls za.h[w8, 0, vgx2], {z0.h - z1.h}, z15.h
+fmls za.h[w11, 7, vgx2], {z30.h - z31.h}, z15.h
+fmls za.h[w8, 3], {z0.h - z1.h}, z15.h
+
+fmls za.h[w8, 0, vgx4], {z0.h - z3.h}, z0.h
+fmls za.h[w11, 0, vgx4], {z0.h - z3.h}, z0.h
+fmls za.h[w8, 7, vgx4], {z0.h - z3.h}, z0.h
+fmls za.h[w8, 0, vgx4], {z31.h - z2.h}, z0.h
+fmls za.h[w8, 0, vgx4], {z0.h - z3.h}, z15.h
+fmls za.h[w11, 7, vgx4], {z28.h - z31.h}, z15.h
+fmls za.h[w8, 3], {z0.h - z3.h}, z15.h
+
+/* FMLS (multiple vectors). */
+fmls za.h[w8, 0, vgx2], {z0.h - z1.h}, {z0.h - z1.h}
+fmls za.h[w11, 0, vgx2], {z0.h - z1.h}, {z0.h - z1.h}
+fmls za.h[w8, 7, vgx2], {z0.h - z1.h}, {z0.h - z1.h}
+fmls za.h[w8, 0, vgx2], {z30.h - z31.h}, {z0.h - z1.h}
+fmls za.h[w8, 0, vgx2], {z0.h - z1.h}, {z30.h - z31.h}
+fmls za.h[w11, 7, vgx2], {z30.h - z31.h}, {z30.h - z31.h}
+fmls za.h[w8, 3], {z0.h - z1.h}, {z30.h - z31.h}
+
+fmls za.h[w8, 0, vgx4], {z0.h - z3.h}, {z0.h - z3.h}
+fmls za.h[w11, 0, vgx4], {z0.h - z3.h}, {z0.h - z3.h}
+fmls za.h[w8, 7, vgx4], {z0.h - z3.h}, {z0.h - z3.h}
+fmls za.h[w8, 0, vgx4], {z28.h - z31.h}, {z0.h - z3.h}
+fmls za.h[w8, 0, vgx4], {z0.h - z3.h}, {z28.h - z31.h}
+fmls za.h[w11, 7, vgx4], {z28.h - z31.h}, {z28.h - z31.h}
+fmls za.h[w8, 3], {z0.h - z3.h}, {z28.h - z31.h}
diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h
index cd8c8257aec..a67ab1d84da 100644
--- a/opcodes/aarch64-tbl.h
+++ b/opcodes/aarch64-tbl.h
@@ -6699,6 +6699,18 @@ const struct aarch64_opcode aarch64_opcode_table[] =
/* SME2.1 half-precision floating-point instructions. */
SME_F16F16_INSN("fmopa", 0x81800008, 0xffe0001e, sme_misc, 0, OP5 (SME_ZAda_1b, SVE_Pg3, SME_Pm, SVE_Zn, SVE_Zm_16), OP_SVE_HMMHH, 0, 0),
SME_F16F16_INSN("fmops", 0x81800018, 0xffe0001e, sme_misc, 0, OP5 (SME_ZAda_1b, SVE_Pg3, SME_Pm, SVE_Zn, SVE_Zm_16), OP_SVE_HMMHH, 0, 0),
+ SME_F16F16_INSN("fmla", 0xc1101000, 0xfff09030, sme_misc, 0, OP3 (SME_ZA_array_off3_0, SME_Znx2, SME_Zm_INDEX3_3), OP_SVE_HHH, F_OD(2), 0),
+ SME_F16F16_INSN("fmla", 0xc1109000, 0xfff09070, sme_misc, 0, OP3 (SME_ZA_array_off3_0, SME_Znx4, SME_Zm_INDEX3_3), OP_SVE_HHH, F_OD(4), 0),
+ SME_F16F16_INSN("fmla", 0xc1201c00, 0xfff09c18, sme_misc, 0, OP3 (SME_ZA_array_off3_0, SVE_ZnxN, SME_Zm), OP_SVE_HHH, F_OD (2), 0),
+ SME_F16F16_INSN("fmla", 0xc1301c00, 0xfff09c18, sme_misc, 0, OP3 (SME_ZA_array_off3_0, SVE_ZnxN, SME_Zm), OP_SVE_HHH, F_OD (4), 0),
+ SME_F16F16_INSN("fmla", 0xc1a01008, 0xffe19c38, sme_misc, 0, OP3 (SME_ZA_array_off3_0, SME_Znx2, SME_Zmx2), OP_SVE_HHH, F_OD (2), 0),
+ SME_F16F16_INSN("fmla", 0xc1a11008, 0xffe39c78, sme_misc, 0, OP3 (SME_ZA_array_off3_0, SME_Znx4, SME_Zmx4), OP_SVE_HHH, F_OD (4), 0),
+ SME_F16F16_INSN("fmls", 0xc1101010, 0xfff09030, sme_misc, 0, OP3 (SME_ZA_array_off3_0, SME_Znx2, SME_Zm_INDEX3_3), OP_SVE_HHH, F_OD(2), 0),
+ SME_F16F16_INSN("fmls", 0xc1109010, 0xfff09070, sme_misc, 0, OP3 (SME_ZA_array_off3_0, SME_Znx4, SME_Zm_INDEX3_3), OP_SVE_HHH, F_OD(4), 0),
+ SME_F16F16_INSN("fmls", 0xc1201c08, 0xfff09c18, sme_misc, 0, OP3 (SME_ZA_array_off3_0, SVE_ZnxN, SME_Zm), OP_SVE_HHH, F_OD (2), 0),
+ SME_F16F16_INSN("fmls", 0xc1301c08, 0xfff09c18, sme_misc, 0, OP3 (SME_ZA_array_off3_0, SVE_ZnxN, SME_Zm), OP_SVE_HHH, F_OD (4), 0),
+ SME_F16F16_INSN("fmls", 0xc1a01018, 0xffe19c38, sme_misc, 0, OP3 (SME_ZA_array_off3_0, SME_Znx2, SME_Zmx2), OP_SVE_HHH, F_OD (2), 0),
+ SME_F16F16_INSN("fmls", 0xc1a11018, 0xffe39c78, sme_misc, 0, OP3 (SME_ZA_array_off3_0, SME_Znx4, SME_Zmx4), OP_SVE_HHH, F_OD (4), 0),
/* SVE2p1 Instructions. */
SVE2p1_INSN("addqv",0x04052000, 0xff3fe000, sve2_urqvs, 0, OP3 (Vd, SVE_Pg3, SVE_Zn), OP_SVE_vUS_BHSD_BHSD, F_OPD_SIZE, 0),
^ permalink raw reply [flat|nested] 12+ messages in thread* Re: [PATCH v1 4/7] aarch64: Add support for FEAT_SME_F16F16 fmla and fmls instructions.
2024-07-12 16:35 ` [PATCH v1 4/7] aarch64: Add support for FEAT_SME_F16F16 fmla and fmls instructions Srinath Parvathaneni
@ 2024-08-16 16:20 ` Andrew Carlotti
0 siblings, 0 replies; 12+ messages in thread
From: Andrew Carlotti @ 2024-08-16 16:20 UTC (permalink / raw)
To: Srinath Parvathaneni; +Cc: binutils, richard.earnshaw, nickc
On Fri, Jul 12, 2024 at 05:35:34PM +0100, Srinath Parvathaneni wrote:
>
> This patch adds support for FEAT_SME_F16F16 instructions fmla and fmls,
> which are available on passing command line flags +sme-f16f16 and the
> spec is available here[1].
> [1]: https://developer.arm.com/documentation/ddi0602/2024-06/SME-Instructions?lang=en
> ---
...
> diff --git a/gas/testsuite/gas/aarch64/sme-f16f16-3.d b/gas/testsuite/gas/aarch64/sme-f16f16-3.d
> new file mode 100644
> index 00000000000..0cf05f2b320
> --- /dev/null
> +++ b/gas/testsuite/gas/aarch64/sme-f16f16-3.d
> @@ -0,0 +1,98 @@
> +#name: Test of FEAT_SME_F16F16 fmla and fmls instructions.
> +#as: -march=armv9.4-a+sme-f16f16
This could instead use -march=armv8-a+sme-f16f16 to demonstrate that the
instructions aren't gated behind any other feature enabled by armv9.4-a.
> +#objdump: -dr
> +
> +[^:]+: file format .*
> +
> +
> +[^:]+:
> +
> +[^:]+:
> +.*: c1101000 fmla za.h\[w8, 0, vgx2\], {z0.h-z1.h}, z0.h\[0\]
> +.*: c1107000 fmla za.h\[w11, 0, vgx2\], {z0.h-z1.h}, z0.h\[0\]
> +.*: c1101007 fmla za.h\[w8, 7, vgx2\], {z0.h-z1.h}, z0.h\[0\]
> +.*: c11013c0 fmla za.h\[w8, 0, vgx2\], {z30.h-z31.h}, z0.h\[0\]
> +.*: c11f1000 fmla za.h\[w8, 0, vgx2\], {z0.h-z1.h}, z15.h\[0\]
> +.*: c1101c08 fmla za.h\[w8, 0, vgx2\], {z0.h-z1.h}, z0.h\[7\]
> +.*: c11f7fcf fmla za.h\[w11, 7, vgx2\], {z30.h-z31.h}, z15.h\[7\]
> +.*: c1101c0b fmla za.h\[w8, 3, vgx2\], {z0.h-z1.h}, z0.h\[7\]
> +.*: c1109000 fmla za.h\[w8, 0, vgx4\], {z0.h-z3.h}, z0.h\[0\]
> +.*: c110f000 fmla za.h\[w11, 0, vgx4\], {z0.h-z3.h}, z0.h\[0\]
> +.*: c1109007 fmla za.h\[w8, 7, vgx4\], {z0.h-z3.h}, z0.h\[0\]
> +.*: c1109380 fmla za.h\[w8, 0, vgx4\], {z28.h-z31.h}, z0.h\[0\]
> +.*: c11f9000 fmla za.h\[w8, 0, vgx4\], {z0.h-z3.h}, z15.h\[0\]
> +.*: c1109c08 fmla za.h\[w8, 0, vgx4\], {z0.h-z3.h}, z0.h\[7\]
> +.*: c11fff8f fmla za.h\[w11, 7, vgx4\], {z28.h-z31.h}, z15.h\[7\]
> +.*: c1109c0b fmla za.h\[w8, 3, vgx4\], {z0.h-z3.h}, z0.h\[7\]
> +.*: c1201c00 fmla za.h\[w8, 0, vgx2\], {z0.h-z1.h}, z0.h
> +.*: c1207c00 fmla za.h\[w11, 0, vgx2\], {z0.h-z1.h}, z0.h
> +.*: c1201c07 fmla za.h\[w8, 7, vgx2\], {z0.h-z1.h}, z0.h
> +.*: c1201fe0 fmla za.h\[w8, 0, vgx2\], {z31.h-z0.h}, z0.h
> +.*: c12f1c00 fmla za.h\[w8, 0, vgx2\], {z0.h-z1.h}, z15.h
> +.*: c12f7fc7 fmla za.h\[w11, 7, vgx2\], {z30.h-z31.h}, z15.h
> +.*: c12f1c03 fmla za.h\[w8, 3, vgx2\], {z0.h-z1.h}, z15.h
> +.*: c1301c00 fmla za.h\[w8, 0, vgx4\], {z0.h-z3.h}, z0.h
> +.*: c1307c00 fmla za.h\[w11, 0, vgx4\], {z0.h-z3.h}, z0.h
> +.*: c1301c07 fmla za.h\[w8, 7, vgx4\], {z0.h-z3.h}, z0.h
> +.*: c1301fe0 fmla za.h\[w8, 0, vgx4\], {z31.h-z2.h}, z0.h
> +.*: c13f1c00 fmla za.h\[w8, 0, vgx4\], {z0.h-z3.h}, z15.h
> +.*: c13f7f87 fmla za.h\[w11, 7, vgx4\], {z28.h-z31.h}, z15.h
> +.*: c13f1c03 fmla za.h\[w8, 3, vgx4\], {z0.h-z3.h}, z15.h
> +.*: c1a01008 fmla za.h\[w8, 0, vgx2\], {z0.h-z1.h}, {z0.h-z1.h}
> +.*: c1a07008 fmla za.h\[w11, 0, vgx2\], {z0.h-z1.h}, {z0.h-z1.h}
> +.*: c1a0100f fmla za.h\[w8, 7, vgx2\], {z0.h-z1.h}, {z0.h-z1.h}
> +.*: c1a013c8 fmla za.h\[w8, 0, vgx2\], {z30.h-z31.h}, {z0.h-z1.h}
> +.*: c1be1008 fmla za.h\[w8, 0, vgx2\], {z0.h-z1.h}, {z30.h-z31.h}
> +.*: c1be73cf fmla za.h\[w11, 7, vgx2\], {z30.h-z31.h}, {z30.h-z31.h}
> +.*: c1be100b fmla za.h\[w8, 3, vgx2\], {z0.h-z1.h}, {z30.h-z31.h}
> +.*: c1a11008 fmla za.h\[w8, 0, vgx4\], {z0.h-z3.h}, {z0.h-z3.h}
> +.*: c1a17008 fmla za.h\[w11, 0, vgx4\], {z0.h-z3.h}, {z0.h-z3.h}
> +.*: c1a1100f fmla za.h\[w8, 7, vgx4\], {z0.h-z3.h}, {z0.h-z3.h}
> +.*: c1a11388 fmla za.h\[w8, 0, vgx4\], {z28.h-z31.h}, {z0.h-z3.h}
> +.*: c1bd1008 fmla za.h\[w8, 0, vgx4\], {z0.h-z3.h}, {z28.h-z31.h}
> +.*: c1bd738f fmla za.h\[w11, 7, vgx4\], {z28.h-z31.h}, {z28.h-z31.h}
> +.*: c1bd100b fmla za.h\[w8, 3, vgx4\], {z0.h-z3.h}, {z28.h-z31.h}
> +.*: c1101010 fmls za.h\[w8, 0, vgx2\], {z0.h-z1.h}, z0.h\[0\]
> +.*: c1107010 fmls za.h\[w11, 0, vgx2\], {z0.h-z1.h}, z0.h\[0\]
> +.*: c1101017 fmls za.h\[w8, 7, vgx2\], {z0.h-z1.h}, z0.h\[0\]
> +.*: c11013d0 fmls za.h\[w8, 0, vgx2\], {z30.h-z31.h}, z0.h\[0\]
> +.*: c11f1010 fmls za.h\[w8, 0, vgx2\], {z0.h-z1.h}, z15.h\[0\]
> +.*: c1101c18 fmls za.h\[w8, 0, vgx2\], {z0.h-z1.h}, z0.h\[7\]
> +.*: c11f7fdf fmls za.h\[w11, 7, vgx2\], {z30.h-z31.h}, z15.h\[7\]
> +.*: c1101c1b fmls za.h\[w8, 3, vgx2\], {z0.h-z1.h}, z0.h\[7\]
> +.*: c1109010 fmls za.h\[w8, 0, vgx4\], {z0.h-z3.h}, z0.h\[0\]
> +.*: c110f010 fmls za.h\[w11, 0, vgx4\], {z0.h-z3.h}, z0.h\[0\]
> +.*: c1109017 fmls za.h\[w8, 7, vgx4\], {z0.h-z3.h}, z0.h\[0\]
> +.*: c1109390 fmls za.h\[w8, 0, vgx4\], {z28.h-z31.h}, z0.h\[0\]
> +.*: c11f9010 fmls za.h\[w8, 0, vgx4\], {z0.h-z3.h}, z15.h\[0\]
> +.*: c1109c18 fmls za.h\[w8, 0, vgx4\], {z0.h-z3.h}, z0.h\[7\]
> +.*: c11fff9f fmls za.h\[w11, 7, vgx4\], {z28.h-z31.h}, z15.h\[7\]
> +.*: c1109c1b fmls za.h\[w8, 3, vgx4\], {z0.h-z3.h}, z0.h\[7\]
> +.*: c1201c08 fmls za.h\[w8, 0, vgx2\], {z0.h-z1.h}, z0.h
> +.*: c1207c08 fmls za.h\[w11, 0, vgx2\], {z0.h-z1.h}, z0.h
> +.*: c1201c0f fmls za.h\[w8, 7, vgx2\], {z0.h-z1.h}, z0.h
> +.*: c1201fe8 fmls za.h\[w8, 0, vgx2\], {z31.h-z0.h}, z0.h
> +.*: c12f1c08 fmls za.h\[w8, 0, vgx2\], {z0.h-z1.h}, z15.h
> +.*: c12f7fcf fmls za.h\[w11, 7, vgx2\], {z30.h-z31.h}, z15.h
> +.*: c12f1c0b fmls za.h\[w8, 3, vgx2\], {z0.h-z1.h}, z15.h
> +.*: c1301c08 fmls za.h\[w8, 0, vgx4\], {z0.h-z3.h}, z0.h
> +.*: c1307c08 fmls za.h\[w11, 0, vgx4\], {z0.h-z3.h}, z0.h
> +.*: c1301c0f fmls za.h\[w8, 7, vgx4\], {z0.h-z3.h}, z0.h
> +.*: c1301fe8 fmls za.h\[w8, 0, vgx4\], {z31.h-z2.h}, z0.h
> +.*: c13f1c08 fmls za.h\[w8, 0, vgx4\], {z0.h-z3.h}, z15.h
> +.*: c13f7f8f fmls za.h\[w11, 7, vgx4\], {z28.h-z31.h}, z15.h
> +.*: c13f1c0b fmls za.h\[w8, 3, vgx4\], {z0.h-z3.h}, z15.h
> +.*: c1a01018 fmls za.h\[w8, 0, vgx2\], {z0.h-z1.h}, {z0.h-z1.h}
> +.*: c1a07018 fmls za.h\[w11, 0, vgx2\], {z0.h-z1.h}, {z0.h-z1.h}
> +.*: c1a0101f fmls za.h\[w8, 7, vgx2\], {z0.h-z1.h}, {z0.h-z1.h}
> +.*: c1a013d8 fmls za.h\[w8, 0, vgx2\], {z30.h-z31.h}, {z0.h-z1.h}
> +.*: c1be1018 fmls za.h\[w8, 0, vgx2\], {z0.h-z1.h}, {z30.h-z31.h}
> +.*: c1be73df fmls za.h\[w11, 7, vgx2\], {z30.h-z31.h}, {z30.h-z31.h}
> +.*: c1be101b fmls za.h\[w8, 3, vgx2\], {z0.h-z1.h}, {z30.h-z31.h}
> +.*: c1a11018 fmls za.h\[w8, 0, vgx4\], {z0.h-z3.h}, {z0.h-z3.h}
> +.*: c1a17018 fmls za.h\[w11, 0, vgx4\], {z0.h-z3.h}, {z0.h-z3.h}
> +.*: c1a1101f fmls za.h\[w8, 7, vgx4\], {z0.h-z3.h}, {z0.h-z3.h}
> +.*: c1a11398 fmls za.h\[w8, 0, vgx4\], {z28.h-z31.h}, {z0.h-z3.h}
> +.*: c1bd1018 fmls za.h\[w8, 0, vgx4\], {z0.h-z3.h}, {z28.h-z31.h}
> +.*: c1bd739f fmls za.h\[w11, 7, vgx4\], {z28.h-z31.h}, {z28.h-z31.h}
> +.*: c1bd101b fmls za.h\[w8, 3, vgx4\], {z0.h-z3.h}, {z28.h-z31.h}
> diff --git a/gas/testsuite/gas/aarch64/sme-f16f16-3.s b/gas/testsuite/gas/aarch64/sme-f16f16-3.s
> new file mode 100644
> index 00000000000..86e39bde65a
> --- /dev/null
> +++ b/gas/testsuite/gas/aarch64/sme-f16f16-3.s
> @@ -0,0 +1,105 @@
> +/* FMLA (multiple and indexed vector). */
> +fmla za.h[w8, 0, vgx2], {z0.h - z1.h}, z0.h[0]
> +fmla za.h[w11, 0, vgx2], {z0.h - z1.h}, z0.h[0]
> +fmla za.h[w8, 7, vgx2], {z0.h - z1.h}, z0.h[0]
> +fmla za.h[w8, 0, vgx2], {z30.h - z31.h}, z0.h[0]
> +fmla za.h[w8, 0, vgx2], {z0.h - z1.h}, z15.h[0]
> +fmla za.h[w8, 0, vgx2], {z0.h - z1.h}, z0.h[7]
> +fmla za.h[w11, 7, vgx2], {z30.h - z31.h}, z15.h[7]
> +fmla za.h[w8, 3], {z0.h - z1.h}, z0.h[7]
The index is split across non-contiguous bits in the encoding, so it's
important to make sure that we don't get the bits in the wrong order by mixing
up the order of the fields. One extra test would suffice (for each opcode
table entry); any index value that isn't 0 or 7 (together with the existing 0
and 7 tests) would be enough to show that the field order is correct.
> +
> +fmla za.h[w8, 0, vgx4], {z0.h - z3.h}, z0.h[0]
> +fmla za.h[w11, 0, vgx4], {z0.h - z3.h}, z0.h[0]
> +fmla za.h[w8, 7, vgx4], {z0.h - z3.h}, z0.h[0]
> +fmla za.h[w8, 0, vgx4], {z28.h - z31.h}, z0.h[0]
> +fmla za.h[w8, 0, vgx4], {z0.h - z3.h}, z15.h[0]
> +fmla za.h[w8, 0, vgx4], {z0.h - z3.h}, z0.h[7]
> +fmla za.h[w11, 7, vgx4], {z28.h - z31.h}, z15.h[7]
> +fmla za.h[w8, 3], {z0.h - z3.h}, z0.h[7]
> +
> +/* FMLA (multiple and single vector). */
> +fmla za.h[w8, 0, vgx2], {z0.h - z1.h}, z0.h
> +fmla za.h[w11, 0, vgx2], {z0.h - z1.h}, z0.h
> +fmla za.h[w8, 7, vgx2], {z0.h - z1.h}, z0.h
> +fmla za.h[w8, 0, vgx2], {z31.h - z0.h}, z0.h
> +fmla za.h[w8, 0, vgx2], {z0.h - z1.h}, z15.h
> +fmla za.h[w11, 7, vgx2], {z30.h - z31.h}, z15.h
> +fmla za.h[w8, 3], {z0.h - z1.h}, z15.h
> +
> +fmla za.h[w8, 0, vgx4], {z0.h - z3.h}, z0.h
> +fmla za.h[w11, 0, vgx4], {z0.h - z3.h}, z0.h
> +fmla za.h[w8, 7, vgx4], {z0.h - z3.h}, z0.h
> +fmla za.h[w8, 0, vgx4], {z31.h - z2.h}, z0.h
> +fmla za.h[w8, 0, vgx4], {z0.h - z3.h}, z15.h
> +fmla za.h[w11, 7, vgx4], {z28.h - z31.h}, z15.h
> +fmla za.h[w8, 3], {z0.h - z3.h}, z15.h
> +
> +/* FMLA (multiple vectors). */
> +fmla za.h[w8, 0, vgx2], {z0.h - z1.h}, {z0.h - z1.h}
> +fmla za.h[w11, 0, vgx2], {z0.h - z1.h}, {z0.h - z1.h}
> +fmla za.h[w8, 7, vgx2], {z0.h - z1.h}, {z0.h - z1.h}
> +fmla za.h[w8, 0, vgx2], {z30.h - z31.h}, {z0.h - z1.h}
> +fmla za.h[w8, 0, vgx2], {z0.h - z1.h}, {z30.h - z31.h}
> +fmla za.h[w11, 7, vgx2], {z30.h - z31.h}, {z30.h - z31.h}
> +fmla za.h[w8, 3], {z0.h - z1.h}, {z30.h - z31.h}
> +
> +fmla za.h[w8, 0, vgx4], {z0.h - z3.h}, {z0.h - z3.h}
> +fmla za.h[w11, 0, vgx4], {z0.h - z3.h}, {z0.h - z3.h}
> +fmla za.h[w8, 7, vgx4], {z0.h - z3.h}, {z0.h - z3.h}
> +fmla za.h[w8, 0, vgx4], {z28.h - z31.h}, {z0.h - z3.h}
> +fmla za.h[w8, 0, vgx4], {z0.h - z3.h}, {z28.h - z31.h}
> +fmla za.h[w11, 7, vgx4], {z28.h - z31.h}, {z28.h - z31.h}
> +fmla za.h[w8, 3], {z0.h - z3.h}, {z28.h - z31.h}
> +
> +/* FMLS (multiple and indexed vector). */
> +fmls za.h[w8, 0, vgx2], {z0.h - z1.h}, z0.h[0]
> +fmls za.h[w11, 0, vgx2], {z0.h - z1.h}, z0.h[0]
> +fmls za.h[w8, 7, vgx2], {z0.h - z1.h}, z0.h[0]
> +fmls za.h[w8, 0, vgx2], {z30.h - z31.h}, z0.h[0]
> +fmls za.h[w8, 0, vgx2], {z0.h - z1.h}, z15.h[0]
> +fmls za.h[w8, 0, vgx2], {z0.h - z1.h}, z0.h[7]
> +fmls za.h[w11, 7, vgx2], {z30.h - z31.h}, z15.h[7]
> +fmls za.h[w8, 3], {z0.h - z1.h}, z0.h[7]
> +
> +fmls za.h[w8, 0, vgx4], {z0.h - z3.h}, z0.h[0]
> +fmls za.h[w11, 0, vgx4], {z0.h - z3.h}, z0.h[0]
> +fmls za.h[w8, 7, vgx4], {z0.h - z3.h}, z0.h[0]
> +fmls za.h[w8, 0, vgx4], {z28.h - z31.h}, z0.h[0]
> +fmls za.h[w8, 0, vgx4], {z0.h - z3.h}, z15.h[0]
> +fmls za.h[w8, 0, vgx4], {z0.h - z3.h}, z0.h[7]
> +fmls za.h[w11, 7, vgx4], {z28.h - z31.h}, z15.h[7]
> +fmls za.h[w8, 3], {z0.h - z3.h}, z0.h[7]
> +
> +/* FMLS (multiple and single vector). */
> +fmls za.h[w8, 0, vgx2], {z0.h - z1.h}, z0.h
> +fmls za.h[w11, 0, vgx2], {z0.h - z1.h}, z0.h
> +fmls za.h[w8, 7, vgx2], {z0.h - z1.h}, z0.h
> +fmls za.h[w8, 0, vgx2], {z31.h - z0.h}, z0.h
> +fmls za.h[w8, 0, vgx2], {z0.h - z1.h}, z15.h
> +fmls za.h[w11, 7, vgx2], {z30.h - z31.h}, z15.h
> +fmls za.h[w8, 3], {z0.h - z1.h}, z15.h
> +
> +fmls za.h[w8, 0, vgx4], {z0.h - z3.h}, z0.h
> +fmls za.h[w11, 0, vgx4], {z0.h - z3.h}, z0.h
> +fmls za.h[w8, 7, vgx4], {z0.h - z3.h}, z0.h
> +fmls za.h[w8, 0, vgx4], {z31.h - z2.h}, z0.h
> +fmls za.h[w8, 0, vgx4], {z0.h - z3.h}, z15.h
> +fmls za.h[w11, 7, vgx4], {z28.h - z31.h}, z15.h
> +fmls za.h[w8, 3], {z0.h - z3.h}, z15.h
> +
> +/* FMLS (multiple vectors). */
> +fmls za.h[w8, 0, vgx2], {z0.h - z1.h}, {z0.h - z1.h}
> +fmls za.h[w11, 0, vgx2], {z0.h - z1.h}, {z0.h - z1.h}
> +fmls za.h[w8, 7, vgx2], {z0.h - z1.h}, {z0.h - z1.h}
> +fmls za.h[w8, 0, vgx2], {z30.h - z31.h}, {z0.h - z1.h}
> +fmls za.h[w8, 0, vgx2], {z0.h - z1.h}, {z30.h - z31.h}
> +fmls za.h[w11, 7, vgx2], {z30.h - z31.h}, {z30.h - z31.h}
> +fmls za.h[w8, 3], {z0.h - z1.h}, {z30.h - z31.h}
> +
> +fmls za.h[w8, 0, vgx4], {z0.h - z3.h}, {z0.h - z3.h}
> +fmls za.h[w11, 0, vgx4], {z0.h - z3.h}, {z0.h - z3.h}
> +fmls za.h[w8, 7, vgx4], {z0.h - z3.h}, {z0.h - z3.h}
> +fmls za.h[w8, 0, vgx4], {z28.h - z31.h}, {z0.h - z3.h}
> +fmls za.h[w8, 0, vgx4], {z0.h - z3.h}, {z28.h - z31.h}
> +fmls za.h[w11, 7, vgx4], {z28.h - z31.h}, {z28.h - z31.h}
> +fmls za.h[w8, 3], {z0.h - z3.h}, {z28.h - z31.h}
> diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h
> index cd8c8257aec..a67ab1d84da 100644
> --- a/opcodes/aarch64-tbl.h
> +++ b/opcodes/aarch64-tbl.h
> @@ -6699,6 +6699,18 @@ const struct aarch64_opcode aarch64_opcode_table[] =
> /* SME2.1 half-precision floating-point instructions. */
> SME_F16F16_INSN("fmopa", 0x81800008, 0xffe0001e, sme_misc, 0, OP5 (SME_ZAda_1b, SVE_Pg3, SME_Pm, SVE_Zn, SVE_Zm_16), OP_SVE_HMMHH, 0, 0),
> SME_F16F16_INSN("fmops", 0x81800018, 0xffe0001e, sme_misc, 0, OP5 (SME_ZAda_1b, SVE_Pg3, SME_Pm, SVE_Zn, SVE_Zm_16), OP_SVE_HMMHH, 0, 0),
> + SME_F16F16_INSN("fmla", 0xc1101000, 0xfff09030, sme_misc, 0, OP3 (SME_ZA_array_off3_0, SME_Znx2, SME_Zm_INDEX3_3), OP_SVE_HHH, F_OD(2), 0),
> + SME_F16F16_INSN("fmla", 0xc1109000, 0xfff09070, sme_misc, 0, OP3 (SME_ZA_array_off3_0, SME_Znx4, SME_Zm_INDEX3_3), OP_SVE_HHH, F_OD(4), 0),
> + SME_F16F16_INSN("fmla", 0xc1201c00, 0xfff09c18, sme_misc, 0, OP3 (SME_ZA_array_off3_0, SVE_ZnxN, SME_Zm), OP_SVE_HHH, F_OD (2), 0),
> + SME_F16F16_INSN("fmla", 0xc1301c00, 0xfff09c18, sme_misc, 0, OP3 (SME_ZA_array_off3_0, SVE_ZnxN, SME_Zm), OP_SVE_HHH, F_OD (4), 0),
> + SME_F16F16_INSN("fmla", 0xc1a01008, 0xffe19c38, sme_misc, 0, OP3 (SME_ZA_array_off3_0, SME_Znx2, SME_Zmx2), OP_SVE_HHH, F_OD (2), 0),
> + SME_F16F16_INSN("fmla", 0xc1a11008, 0xffe39c78, sme_misc, 0, OP3 (SME_ZA_array_off3_0, SME_Znx4, SME_Zmx4), OP_SVE_HHH, F_OD (4), 0),
> + SME_F16F16_INSN("fmls", 0xc1101010, 0xfff09030, sme_misc, 0, OP3 (SME_ZA_array_off3_0, SME_Znx2, SME_Zm_INDEX3_3), OP_SVE_HHH, F_OD(2), 0),
> + SME_F16F16_INSN("fmls", 0xc1109010, 0xfff09070, sme_misc, 0, OP3 (SME_ZA_array_off3_0, SME_Znx4, SME_Zm_INDEX3_3), OP_SVE_HHH, F_OD(4), 0),
> + SME_F16F16_INSN("fmls", 0xc1201c08, 0xfff09c18, sme_misc, 0, OP3 (SME_ZA_array_off3_0, SVE_ZnxN, SME_Zm), OP_SVE_HHH, F_OD (2), 0),
> + SME_F16F16_INSN("fmls", 0xc1301c08, 0xfff09c18, sme_misc, 0, OP3 (SME_ZA_array_off3_0, SVE_ZnxN, SME_Zm), OP_SVE_HHH, F_OD (4), 0),
> + SME_F16F16_INSN("fmls", 0xc1a01018, 0xffe19c38, sme_misc, 0, OP3 (SME_ZA_array_off3_0, SME_Znx2, SME_Zmx2), OP_SVE_HHH, F_OD (2), 0),
> + SME_F16F16_INSN("fmls", 0xc1a11018, 0xffe39c78, sme_misc, 0, OP3 (SME_ZA_array_off3_0, SME_Znx4, SME_Zmx4), OP_SVE_HHH, F_OD (4), 0),
>
> /* SVE2p1 Instructions. */
> SVE2p1_INSN("addqv",0x04052000, 0xff3fe000, sve2_urqvs, 0, OP3 (Vd, SVE_Pg3, SVE_Zn), OP_SVE_vUS_BHSD_BHSD, F_OPD_SIZE, 0),
^ permalink raw reply [flat|nested] 12+ messages in thread
* [PATCH v1 5/7] aarch64: Add support for FEAT_SME_F16F16 fmla and fmls instructions (regenerated files).
2024-07-12 16:35 [PATCH v1 0/7][Binutils] aarch64: Add support for FEAT_SME_F16F16 feature and instructions Srinath Parvathaneni
` (3 preceding siblings ...)
2024-07-12 16:35 ` [PATCH v1 4/7] aarch64: Add support for FEAT_SME_F16F16 fmla and fmls instructions Srinath Parvathaneni
@ 2024-07-12 16:35 ` Srinath Parvathaneni
2024-07-12 16:35 ` [PATCH v1 6/7] aarch64: Add support for FEAT_SME_F16F16 fcvt and fcvtl instructions Srinath Parvathaneni
` (2 subsequent siblings)
7 siblings, 0 replies; 12+ messages in thread
From: Srinath Parvathaneni @ 2024-07-12 16:35 UTC (permalink / raw)
To: binutils; +Cc: richard.earnshaw, nickc, Srinath Parvathaneni
[-- Attachment #1: Type: text/plain, Size: 246 bytes --]
This patch includes the regenerated files for
aarch64: Add support for FEAT_SME_F16F16 fmla and fmls instructions.
---
opcodes/aarch64-dis-2.c | 734 ++++++++++++++++++++++++----------------
1 file changed, 433 insertions(+), 301 deletions(-)
[-- Warning: decoded text below may be mangled, UTF-8 assumed --]
[-- Attachment #2: v1-0005-aarch64-Add-support-for-FEAT_SME_F16F16-fmla-and-.patch --]
[-- Type: text/x-patch; name="v1-0005-aarch64-Add-support-for-FEAT_SME_F16F16-fmla-and-.patch", Size: 152553 bytes --]
diff --git a/opcodes/aarch64-dis-2.c b/opcodes/aarch64-dis-2.c
index f1aa790b28f..446c3b54609 100644
--- a/opcodes/aarch64-dis-2.c
+++ b/opcodes/aarch64-dis-2.c
@@ -271,7 +271,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000000x000101x00xxxxxxxxxxxxxx
luti4. */
- return 3430;
+ return 3442;
}
else
{
@@ -310,7 +310,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000000xx01101x00xxxxxxxxxxxxxx
luti4. */
- return 3431;
+ return 3443;
}
else
{
@@ -542,7 +542,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000000010011x1xxxx00xxxxxxxxxx
movt. */
- return 3432;
+ return 3444;
}
}
else
@@ -1366,7 +1366,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx000000101xxxxxxxxxxxxxxxx00xxx
fmopa. */
- return 3498;
+ return 3510;
}
else
{
@@ -1374,7 +1374,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx000000101xxxxxxxxxxxxxxxx01xxx
fmopa. */
- return 3497;
+ return 3509;
}
}
else
@@ -1722,7 +1722,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx0000010001xxxx1xx0xxxxx1000xxx
fmlall. */
- return 3491;
+ return 3503;
}
}
}
@@ -1748,11 +1748,33 @@ aarch64_opcode_lookup_1 (uint32_t word)
}
else
{
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- xx0000010001xxxxxxx1xxxxxx00xxxx
- fdot. */
- return 3476;
+ if (((word >> 15) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xx0000010001xxxx0xx1xxxxxx00xxxx
+ fmla. */
+ return 3327;
+ }
+ else
+ {
+ if (((word >> 6) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xx0000010001xxxx1xx1xxxxx000xxxx
+ fmla. */
+ return 3328;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xx0000010001xxxx1xx1xxxxx100xxxx
+ fdot. */
+ return 3488;
+ }
+ }
}
}
else
@@ -1778,11 +1800,11 @@ aarch64_opcode_lookup_1 (uint32_t word)
}
else
{
- if (((word >> 3) & 0x1) == 0)
+ if (((word >> 20) & 0x1) == 0)
{
- if (((word >> 20) & 0x1) == 0)
+ if (((word >> 2) & 0x1) == 0)
{
- if (((word >> 2) & 0x1) == 0)
+ if (((word >> 3) & 0x1) == 0)
{
/* 33222222222211111111110000000000
10987654321098765432109876543210
@@ -1794,62 +1816,84 @@ aarch64_opcode_lookup_1 (uint32_t word)
{
/* 33222222222211111111110000000000
10987654321098765432109876543210
- xx0000010000xxxxxxxxxxxxxxx101xx
- sumlall. */
- return 2848;
+ xx0000010000xxxxxxxxxxxxxxx110xx
+ umlsll. */
+ return 2906;
}
}
else
{
- if (((word >> 5) & 0x1) == 0)
- {
- if (((word >> 15) & 0x1) == 0)
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- xx0000010001xxxx0xxxxxxxxx010xxx
- umlall. */
- return 2891;
- }
- else
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- xx0000010001xxxx1xxxxxxxxx010xxx
- umlall. */
- return 2892;
- }
- }
- else
- {
- if (((word >> 15) & 0x1) == 0)
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- xx0000010001xxxx0xxxxxxxxx110xxx
- sumlall. */
- return 2849;
- }
- else
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- xx0000010001xxxx1xxxxxxxxx110xxx
- sumlall. */
- return 2850;
- }
- }
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xx0000010000xxxxxxxxxxxxxxx1x1xx
+ sumlall. */
+ return 2848;
}
}
else
{
- if (((word >> 20) & 0x1) == 0)
+ if (((word >> 5) & 0x1) == 0)
{
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- xx0000010000xxxxxxxxxxxxxxx11xxx
- umlsll. */
- return 2906;
+ if (((word >> 12) & 0x1) == 0)
+ {
+ if (((word >> 3) & 0x1) == 0)
+ {
+ if (((word >> 15) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xx0000010001xxxx0xx0xxxxxx010xxx
+ umlall. */
+ return 2891;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xx0000010001xxxx1xx0xxxxxx010xxx
+ umlall. */
+ return 2892;
+ }
+ }
+ else
+ {
+ if (((word >> 15) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xx0000010001xxxx0xx0xxxxxx011xxx
+ umlsll. */
+ return 2907;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xx0000010001xxxx1xx0xxxxxx011xxx
+ umlsll. */
+ return 2908;
+ }
+ }
+ }
+ else
+ {
+ if (((word >> 15) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xx0000010001xxxx0xx1xxxxxx01xxxx
+ fmls. */
+ return 3333;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xx0000010001xxxx1xx1xxxxxx01xxxx
+ fmls. */
+ return 3334;
+ }
+ }
}
else
{
@@ -1857,17 +1901,17 @@ aarch64_opcode_lookup_1 (uint32_t word)
{
/* 33222222222211111111110000000000
10987654321098765432109876543210
- xx0000010001xxxx0xxxxxxxxxx11xxx
- umlsll. */
- return 2907;
+ xx0000010001xxxx0xxxxxxxxx11xxxx
+ sumlall. */
+ return 2849;
}
else
{
/* 33222222222211111111110000000000
10987654321098765432109876543210
- xx0000010001xxxx1xxxxxxxxxx11xxx
- umlsll. */
- return 2908;
+ xx0000010001xxxx1xxxxxxxxx11xxxx
+ sumlall. */
+ return 2850;
}
}
}
@@ -2135,7 +2179,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x10000011001xxxxxxx0xxxxxx100xxx
fmlall. */
- return 3490;
+ return 3502;
}
}
}
@@ -2240,7 +2284,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x10000011001xxxxxxx1xxxxxx10xxxx
fmlal. */
- return 3483;
+ return 3495;
}
}
}
@@ -2424,7 +2468,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x10000011001xxxxxxx1xxxxxx11xxxx
fmlal. */
- return 3482;
+ return 3494;
}
}
}
@@ -2466,7 +2510,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx0000010100xxxxxxxxxxxxxxxx0xxx
fmlall. */
- return 3489;
+ return 3501;
}
else
{
@@ -2834,7 +2878,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xxx000010101xxxx0xx0xxxxxx111xxx
fdot. */
- return 3469;
+ return 3481;
}
else
{
@@ -2903,7 +2947,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xxx000010101xxxx1xx0xxxxxx001xxx
fdot. */
- return 3470;
+ return 3482;
}
else
{
@@ -2982,7 +3026,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx0000011100xxxxxxx0xxxxxxx0xxxx
fmlal. */
- return 3481;
+ return 3493;
}
else
{
@@ -3037,7 +3081,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx0000011101xxxx0xx01xxxxx00xxxx
fvdotb. */
- return 3500;
+ return 3512;
}
else
{
@@ -3055,7 +3099,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx0000011101xxxxxxx0xxxxxx10xxxx
fdot. */
- return 3475;
+ return 3487;
}
}
}
@@ -3129,7 +3173,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx0000011101xxxxxxx1xxxxxx10xxxx
fvdot. */
- return 3499;
+ return 3511;
}
}
}
@@ -3209,7 +3253,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx000001110xxxxx0xx01xxxxxx1xxxx
fvdott. */
- return 3501;
+ return 3513;
}
else
{
@@ -3386,7 +3430,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x10000011x1xxxx00xx000xxxx10000x
fmlall. */
- return 3495;
+ return 3507;
}
else
{
@@ -3394,7 +3438,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x10000011x1xxxx10xx000xxxx10000x
fmlall. */
- return 3496;
+ return 3508;
}
}
}
@@ -3449,7 +3493,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001xx10xxxx0xx000xxxxx00x1x
fmlall. */
- return 3493;
+ return 3505;
}
else
{
@@ -3457,7 +3501,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001xx11xxxx0xx000xxxxx00x1x
fmlall. */
- return 3494;
+ return 3506;
}
}
}
@@ -3511,7 +3555,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x10000011x1xxxx00xx100xxxx100xxx
fdot. */
- return 3479;
+ return 3491;
}
else
{
@@ -3519,7 +3563,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x10000011x1xxxx10xx100xxxx100xxx
fdot. */
- return 3480;
+ return 3492;
}
}
}
@@ -3581,7 +3625,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001101xxxx00xx010xxxx1000xx
fmlal. */
- return 3487;
+ return 3499;
}
else
{
@@ -3589,7 +3633,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001101xxxx10xx010xxxx1000xx
fmlal. */
- return 3488;
+ return 3500;
}
}
}
@@ -3644,7 +3688,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001xx10xxxx0xx010xxxxx001xx
fmlal. */
- return 3485;
+ return 3497;
}
else
{
@@ -3652,7 +3696,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001xx11xxxx0xx010xxxxx001xx
fmlal. */
- return 3486;
+ return 3498;
}
}
}
@@ -3721,7 +3765,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001xx11xxxx0xx001xxxxx000xx
fmlall. */
- return 3492;
+ return 3504;
}
}
else
@@ -3804,48 +3848,70 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001xx11xxxx0xx011xxxxx00xxx
fmlal. */
- return 3484;
+ return 3496;
}
}
else
{
- if (((word >> 16) & 0x1) == 0)
+ if (((word >> 20) & 0x1) == 0)
{
- if (((word >> 18) & 0x1) == 0)
+ if (((word >> 23) & 0x1) == 0)
{
/* 33222222222211111111110000000000
10987654321098765432109876543210
- x1000001xx1xx0x00xx111xxxxx00xxx
- fadd. */
- return 2530;
+ x10000010x10xxxx0xx111xxxxx00xxx
+ fmla. */
+ return 3329;
}
else
{
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- x1000001xx1xx1x00xx111xxxxx00xxx
- fadd. */
- return 3433;
+ if (((word >> 16) & 0x1) == 0)
+ {
+ if (((word >> 18) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x10000011x10x0x00xx111xxxxx00xxx
+ fadd. */
+ return 2530;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x10000011x10x1x00xx111xxxxx00xxx
+ fadd. */
+ return 3445;
+ }
+ }
+ else
+ {
+ if (((word >> 18) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x10000011x10x0x10xx111xxxxx00xxx
+ fadd. */
+ return 2531;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x10000011x10x1x10xx111xxxxx00xxx
+ fadd. */
+ return 3446;
+ }
+ }
}
}
else
{
- if (((word >> 18) & 0x1) == 0)
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- x1000001xx1xx0x10xx111xxxxx00xxx
- fadd. */
- return 2531;
- }
- else
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- x1000001xx1xx1x10xx111xxxxx00xxx
- fadd. */
- return 3434;
- }
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x1000001xx11xxxx0xx111xxxxx00xxx
+ fmla. */
+ return 3330;
}
}
}
@@ -3970,7 +4036,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x10000011x1xxxx00xx100xxxx110xxx
fdot. */
- return 3473;
+ return 3485;
}
else
{
@@ -3978,7 +4044,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x10000011x1xxxx10xx100xxxx110xxx
fdot. */
- return 3474;
+ return 3486;
}
}
}
@@ -4263,21 +4329,43 @@ aarch64_opcode_lookup_1 (uint32_t word)
}
else
{
- if (((word >> 20) & 0x1) == 0)
+ if (((word >> 23) & 0x1) == 0)
{
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- x1000001xx10xxxx0xx100xxxxx01xxx
- fdot. */
- return 3477;
+ if (((word >> 20) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x10000010x10xxxx0xx100xxxxx01xxx
+ fdot. */
+ return 3489;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x10000010x11xxxx0xx100xxxxx01xxx
+ fdot. */
+ return 3490;
+ }
}
else
{
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- x1000001xx11xxxx0xx100xxxxx01xxx
- fdot. */
- return 3478;
+ if (((word >> 16) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x10000011x1xxxx00xx100xxxxx01xxx
+ fmla. */
+ return 3331;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x10000011x1xxxx10xx100xxxxx01xxx
+ fmla. */
+ return 3332;
+ }
}
}
}
@@ -4532,43 +4620,65 @@ aarch64_opcode_lookup_1 (uint32_t word)
}
else
{
- if (((word >> 16) & 0x1) == 0)
+ if (((word >> 20) & 0x1) == 0)
{
- if (((word >> 18) & 0x1) == 0)
+ if (((word >> 23) & 0x1) == 0)
{
/* 33222222222211111111110000000000
10987654321098765432109876543210
- x1000001xx1xx0x00xx111xxxxx01xxx
- fsub. */
- return 2598;
+ x10000010x10xxxx0xx111xxxxx01xxx
+ fmls. */
+ return 3335;
}
else
{
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- x1000001xx1xx1x00xx111xxxxx01xxx
- fsub. */
- return 3435;
+ if (((word >> 16) & 0x1) == 0)
+ {
+ if (((word >> 18) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x10000011x10x0x00xx111xxxxx01xxx
+ fsub. */
+ return 2598;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x10000011x10x1x00xx111xxxxx01xxx
+ fsub. */
+ return 3447;
+ }
+ }
+ else
+ {
+ if (((word >> 18) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x10000011x10x0x10xx111xxxxx01xxx
+ fsub. */
+ return 2599;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x10000011x10x1x10xx111xxxxx01xxx
+ fsub. */
+ return 3448;
+ }
+ }
}
}
else
{
- if (((word >> 18) & 0x1) == 0)
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- x1000001xx1xx0x10xx111xxxxx01xxx
- fsub. */
- return 2599;
- }
- else
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- x1000001xx1xx1x10xx111xxxxx01xxx
- fsub. */
- return 3436;
- }
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x1000001xx11xxxx0xx111xxxxx01xxx
+ fmls. */
+ return 3336;
}
}
}
@@ -4623,21 +4733,43 @@ aarch64_opcode_lookup_1 (uint32_t word)
}
else
{
- if (((word >> 20) & 0x1) == 0)
+ if (((word >> 23) & 0x1) == 0)
{
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- x1000001xx10xxxx0xx100xxxxx11xxx
- fdot. */
- return 3471;
+ if (((word >> 20) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x10000010x10xxxx0xx100xxxxx11xxx
+ fdot. */
+ return 3483;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x10000010x11xxxx0xx100xxxxx11xxx
+ fdot. */
+ return 3484;
+ }
}
else
{
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- x1000001xx11xxxx0xx100xxxxx11xxx
- fdot. */
- return 3472;
+ if (((word >> 16) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x10000011x1xxxx00xx100xxxxx11xxx
+ fmls. */
+ return 3337;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x10000011x1xxxx10xx100xxxxx11xxx
+ fmls. */
+ return 3338;
+ }
}
}
}
@@ -5172,7 +5304,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001xx1xxxxx101000xx1x0xxxx0
fscale. */
- return 3407;
+ return 3419;
}
}
else
@@ -5320,7 +5452,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001x0100100111000xxxx0xxxxx
fcvt. */
- return 3404;
+ return 3416;
}
else
{
@@ -5328,7 +5460,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001x1100100111000xxxx0xxxxx
bfcvt. */
- return 3399;
+ return 3411;
}
}
else
@@ -5337,7 +5469,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001xx110100111000xxxx0xxxxx
fcvt. */
- return 3405;
+ return 3417;
}
}
else
@@ -5388,7 +5520,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001xx1xx100111000xxxx1xxxxx
fcvtn. */
- return 3406;
+ return 3418;
}
}
}
@@ -5471,7 +5603,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x10000010010x110111000xxxxxxxxx0
f1cvt. */
- return 3400;
+ return 3412;
}
else
{
@@ -5479,7 +5611,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x10000011010x110111000xxxxxxxxx0
f2cvt. */
- return 3401;
+ return 3413;
}
}
else
@@ -5490,7 +5622,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x10000010110x110111000xxxxxxxxx0
bf1cvt. */
- return 3395;
+ return 3407;
}
else
{
@@ -5498,7 +5630,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x10000011110x110111000xxxxxxxxx0
bf2cvt. */
- return 3396;
+ return 3408;
}
}
}
@@ -5533,7 +5665,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001001xxx10111000xxxxxxxxx1
f1cvtl. */
- return 3402;
+ return 3414;
}
else
{
@@ -5541,7 +5673,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001101xxx10111000xxxxxxxxx1
f2cvtl. */
- return 3403;
+ return 3415;
}
}
else
@@ -5552,7 +5684,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001011xxx10111000xxxxxxxxx1
bf1cvtl. */
- return 3397;
+ return 3409;
}
else
{
@@ -5560,7 +5692,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001111xxx10111000xxxxxxxxx1
bf2cvtl. */
- return 3398;
+ return 3410;
}
}
}
@@ -5829,7 +5961,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001xx1xxxxx1x1100xx100xxxx0
fscale. */
- return 3409;
+ return 3421;
}
}
else
@@ -6005,7 +6137,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001xx1xxxxx1x1010xx100xxxx0
fscale. */
- return 3408;
+ return 3420;
}
else
{
@@ -6013,7 +6145,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001xx1xxxxx1x1110xx100xxxx0
fscale. */
- return 3410;
+ return 3422;
}
}
}
@@ -11181,7 +11313,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x0x11010000xxxxxxx1xxxxxxxxxxxxx
addpt. */
- return 3411;
+ return 3423;
}
else
{
@@ -11189,7 +11321,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1x11010000xxxxxxx1xxxxxxxxxxxxx
subpt. */
- return 3412;
+ return 3424;
}
}
}
@@ -12107,7 +12239,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xxxx1011x11xxxxx0xxxxxxxxxxxxxxx
maddpt. */
- return 3413;
+ return 3425;
}
else
{
@@ -12115,7 +12247,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xxxx1011x11xxxxx1xxxxxxxxxxxxxxx
msubpt. */
- return 3414;
+ return 3426;
}
}
}
@@ -12200,7 +12332,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
000001x0xx000100000xxxxxxxxxxxxx
addpt. */
- return 3415;
+ return 3427;
}
else
{
@@ -12307,7 +12439,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
000001x0xx000101000xxxxxxxxxxxxx
subpt. */
- return 3417;
+ return 3429;
}
else
{
@@ -12512,7 +12644,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
000001x0xx1xxxxx000010xxxxxxxxxx
addpt. */
- return 3416;
+ return 3428;
}
else
{
@@ -12553,7 +12685,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
000001x0xx1xxxxx000011xxxxxxxxxx
subpt. */
- return 3418;
+ return 3430;
}
else
{
@@ -14211,7 +14343,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
010001x0xx0xxxxx110100xxxxxxxxxx
mlapt. */
- return 3420;
+ return 3432;
}
}
else
@@ -14241,7 +14373,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
010001x0xx0xxxxx110110xxxxxxxxxx
madpt. */
- return 3419;
+ return 3431;
}
}
}
@@ -14549,7 +14681,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
000001x0xx00x100001xxxxxxxxxxxxx
smaxqv. */
- return 3329;
+ return 3341;
}
else
{
@@ -14557,7 +14689,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
000001x0xx01x100001xxxxxxxxxxxxx
orqv. */
- return 3340;
+ return 3352;
}
}
else
@@ -14568,7 +14700,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
000001x0xx0x0101001xxxxxxxxxxxxx
addqv. */
- return 3327;
+ return 3339;
}
else
{
@@ -14578,7 +14710,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
000001x0xx001101001xxxxxxxxxxxxx
umaxqv. */
- return 3331;
+ return 3343;
}
else
{
@@ -14586,7 +14718,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
000001x0xx011101001xxxxxxxxxxxxx
eorqv. */
- return 3333;
+ return 3345;
}
}
}
@@ -14623,7 +14755,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
000001x0xx00x110001xxxxxxxxxxxxx
sminqv. */
- return 3330;
+ return 3342;
}
else
{
@@ -14631,7 +14763,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
000001x0xx01x110001xxxxxxxxxxxxx
andqv. */
- return 3328;
+ return 3340;
}
}
}
@@ -14651,7 +14783,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
000001x0xx0xx111001xxxxxxxxxxxxx
uminqv. */
- return 3332;
+ return 3344;
}
}
}
@@ -15395,7 +15527,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
110001x0x00xxxxx101xxxxxxxxxxxxx
ld1q. */
- return 3356;
+ return 3368;
}
else
{
@@ -16409,7 +16541,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
010001x0xx0xxxxx111x00xxxxxxxxxx
zipq1. */
- return 3346;
+ return 3358;
}
else
{
@@ -16419,7 +16551,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
010001x0xx0xxxxx111010xxxxxxxxxx
uzpq1. */
- return 3344;
+ return 3356;
}
else
{
@@ -16427,7 +16559,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
010001x0xx0xxxxx111110xxxxxxxxxx
tblq. */
- return 3341;
+ return 3353;
}
}
}
@@ -16439,7 +16571,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
010001x0xx0xxxxx111x01xxxxxxxxxx
zipq2. */
- return 3347;
+ return 3359;
}
else
{
@@ -16447,7 +16579,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
010001x0xx0xxxxx111x11xxxxxxxxxx
uzpq2. */
- return 3345;
+ return 3357;
}
}
}
@@ -16927,7 +17059,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
111001x0x00xxxxx000xxxxxxxxxxxxx
st3q. */
- return 3365;
+ return 3377;
}
else
{
@@ -16937,7 +17069,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
111001x0010xxxxx000xxxxxxxxxxxxx
st2q. */
- return 3364;
+ return 3376;
}
else
{
@@ -16945,7 +17077,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
111001x0110xxxxx000xxxxxxxxxxxxx
st4q. */
- return 3366;
+ return 3378;
}
}
}
@@ -17392,7 +17524,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x0xx0x0000101xxxxxxxxxxxxx
faddqv. */
- return 3334;
+ return 3346;
}
else
{
@@ -17409,7 +17541,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x0xx0xx100101xxxxxxxxxxxxx
fmaxnmqv. */
- return 3335;
+ return 3347;
}
}
else
@@ -17450,7 +17582,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x0xx0xx110101xxxxxxxxxxxxx
fmaxqv. */
- return 3336;
+ return 3348;
}
}
}
@@ -17472,7 +17604,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x0xx0xx101101xxxxxxxxxxxxx
fminnmqv. */
- return 3337;
+ return 3349;
}
}
else
@@ -17491,7 +17623,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x0xx0xx111101xxxxxxxxxxxxx
fminqv. */
- return 3338;
+ return 3350;
}
}
}
@@ -17611,7 +17743,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
101001x0xx01xxxx111xxxxxxxxxxxxx
ld2q. */
- return 3357;
+ return 3369;
}
}
}
@@ -17747,7 +17879,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
101001x0xx1xxxxx100xxxxxxxxxxxxx
ld2q. */
- return 3360;
+ return 3372;
}
}
else
@@ -17892,7 +18024,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
111001x00x1xxxxx000xxxxxxxxxxxxx
st2q. */
- return 3367;
+ return 3379;
}
}
else
@@ -17935,7 +18067,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
111001x0101xxxxx000xxxxxxxxxxxxx
st3q. */
- return 3368;
+ return 3380;
}
}
else
@@ -17976,7 +18108,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
111001x0111xxxxx000xxxxxxxxxxxxx
st4q. */
- return 3369;
+ return 3381;
}
}
}
@@ -18005,7 +18137,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x0001xxxxx0100x1xxxxxxxxxx
fdot. */
- return 3456;
+ return 3468;
}
}
else
@@ -18014,7 +18146,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x0001xxxxx0101xxxxxxxxxxxx
fmlalb. */
- return 3458;
+ return 3470;
}
}
else
@@ -18055,7 +18187,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x0101xxxxx0101xxxxxxxxxxxx
fmlalt. */
- return 3468;
+ return 3480;
}
}
else
@@ -18088,7 +18220,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x0011xxxxx010xx1xxxxxxxxxx
fdot. */
- return 3454;
+ return 3466;
}
}
else
@@ -18159,7 +18291,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x11001x0001xxxxx100010xxxxxxxxxx
fmlallbb. */
- return 3459;
+ return 3471;
}
}
else
@@ -18168,7 +18300,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x11001x0001xxxxx1000x1xxxxxxxxxx
fdot. */
- return 3455;
+ return 3467;
}
}
else
@@ -18177,7 +18309,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x11001x0001xxxxx1100xxxxxxxxxxxx
fmlallbb. */
- return 3460;
+ return 3472;
}
}
else
@@ -18186,7 +18318,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x11001x0001xxxxx1x01xxxxxxxxxxxx
fmlallbt. */
- return 3461;
+ return 3473;
}
}
else
@@ -18213,7 +18345,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x0101xxxxx100010xxxxxxxxxx
fmlalb. */
- return 3457;
+ return 3469;
}
}
else
@@ -18231,7 +18363,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x0101xxxxx1100xxxxxxxxxxxx
fmlalltb. */
- return 3464;
+ return 3476;
}
}
else
@@ -18240,7 +18372,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x0101xxxxx1x01xxxxxxxxxxxx
fmlalt. */
- return 3467;
+ return 3479;
}
}
else
@@ -18273,7 +18405,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x11001x0011xxxxx100xx1xxxxxxxxxx
fdot. */
- return 3453;
+ return 3465;
}
}
else
@@ -18282,7 +18414,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x11001x0011xxxxx110xxxxxxxxxxxxx
fmlallbt. */
- return 3462;
+ return 3474;
}
}
else
@@ -18314,7 +18446,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x0111xxxxx110xxxxxxxxxxxxx
fmlalltt. */
- return 3466;
+ return 3478;
}
}
else
@@ -18613,7 +18745,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
111001x0xx1xxxxx001xxxxxxxxxxxxx
st1q. */
- return 3363;
+ return 3375;
}
}
else
@@ -18628,7 +18760,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x11001x0001xxxxx1010xxxxxxxxxxxx
fmlalltb. */
- return 3463;
+ return 3475;
}
else
{
@@ -18636,7 +18768,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x11001x0001xxxxx1011xxxxxxxxxxxx
fmlalltt. */
- return 3465;
+ return 3477;
}
}
else
@@ -19354,7 +19486,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
000001x1001010x0001110xxxxxxxxxx
pmov. */
- return 3348;
+ return 3360;
}
else
{
@@ -19362,7 +19494,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
000001x1001011x0001110xxxxxxxxxx
pmov. */
- return 3349;
+ return 3361;
}
}
else
@@ -19371,7 +19503,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
000001x101101xx0001110xxxxxxxxxx
pmov. */
- return 3350;
+ return 3362;
}
}
else
@@ -19380,7 +19512,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
000001x11x101xx0001110xxxxxxxxxx
pmov. */
- return 3351;
+ return 3363;
}
}
else
@@ -19426,7 +19558,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
000001x1001x10x1001110xxxxxxxxxx
pmov. */
- return 3352;
+ return 3364;
}
else
{
@@ -19434,7 +19566,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
000001x1001x11x1001110xxxxxxxxxx
pmov. */
- return 3353;
+ return 3365;
}
}
else
@@ -19443,7 +19575,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
000001x1011x1xx1001110xxxxxxxxxx
pmov. */
- return 3354;
+ return 3366;
}
}
else
@@ -19452,7 +19584,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
000001x11x1x1xx1001110xxxxxxxxxx
pmov. */
- return 3355;
+ return 3367;
}
}
}
@@ -19471,7 +19603,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
000001x1x01xxxxx001001xxxxxxxxxx
dupq. */
- return 3339;
+ return 3351;
}
else
{
@@ -19479,7 +19611,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
000001x1x11xxxxx001001xxxxxxxxxx
extq. */
- return 3343;
+ return 3355;
}
}
else
@@ -19488,7 +19620,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
000001x1xx1xxxxx001101xxxxxxxxxx
tbxq. */
- return 3342;
+ return 3354;
}
}
else
@@ -21091,7 +21223,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
010001x1xx1xxxxx101100xxxxxxxxxx
luti2. */
- return 3425;
+ return 3437;
}
}
else
@@ -21100,7 +21232,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
010001x1xx1xxxxx101x10xxxxxxxxxx
luti2. */
- return 3426;
+ return 3438;
}
}
else
@@ -21113,7 +21245,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
010001x1xx1xxxxx101001xxxxxxxxxx
luti4. */
- return 3427;
+ return 3439;
}
else
{
@@ -21121,7 +21253,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
010001x1xx1xxxxx101101xxxxxxxxxx
luti4. */
- return 3428;
+ return 3440;
}
}
else
@@ -21130,7 +21262,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
010001x1xx1xxxxx101x11xxxxxxxxxx
luti4. */
- return 3429;
+ return 3441;
}
}
}
@@ -22081,7 +22213,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x1xx001000001x00xxxxxxxxxx
f1cvt. */
- return 3387;
+ return 3399;
}
else
{
@@ -22089,7 +22221,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x1xx001000001x10xxxxxxxxxx
bf1cvt. */
- return 3383;
+ return 3395;
}
}
else
@@ -22100,7 +22232,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x1xx001000001x01xxxxxxxxxx
f2cvt. */
- return 3388;
+ return 3400;
}
else
{
@@ -22108,7 +22240,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x1xx001000001x11xxxxxxxxxx
bf2cvt. */
- return 3384;
+ return 3396;
}
}
}
@@ -22153,7 +22285,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x1xx0x1010001x00xxxxxxxxxx
fcvtn. */
- return 3392;
+ return 3404;
}
else
{
@@ -22161,7 +22293,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x1xx0x1010001x10xxxxxxxxxx
bfcvtn. */
- return 3391;
+ return 3403;
}
}
else
@@ -22172,7 +22304,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x1xx0x1010001x01xxxxxxxxxx
fcvtnb. */
- return 3393;
+ return 3405;
}
else
{
@@ -22180,7 +22312,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x1xx0x1010001x11xxxxxxxxxx
fcvtnt. */
- return 3394;
+ return 3406;
}
}
}
@@ -22241,7 +22373,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x1xx0x1001001x00xxxxxxxxxx
f1cvtlt. */
- return 3389;
+ return 3401;
}
else
{
@@ -22249,7 +22381,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x1xx0x1001001x10xxxxxxxxxx
bf1cvtlt. */
- return 3385;
+ return 3397;
}
}
else
@@ -22260,7 +22392,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x1xx0x1001001x01xxxxxxxxxx
f2cvtlt. */
- return 3390;
+ return 3402;
}
else
{
@@ -22268,7 +22400,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x1xx0x1001001x11xxxxxxxxxx
bf2cvtlt. */
- return 3386;
+ return 3398;
}
}
}
@@ -23594,7 +23726,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
101001x10x01xxxx111xxxxxxxxxxxxx
ld3q. */
- return 3358;
+ return 3370;
}
else
{
@@ -23602,7 +23734,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
101001x11x01xxxx111xxxxxxxxxxxxx
ld4q. */
- return 3359;
+ return 3371;
}
}
}
@@ -24775,7 +24907,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
101001x10x1xxxxx100xxxxxxxxxxxxx
ld3q. */
- return 3361;
+ return 3373;
}
else
{
@@ -24783,7 +24915,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
101001x11x1xxxxx100xxxxxxxxxxxxx
ld4q. */
- return 3362;
+ return 3374;
}
}
else
@@ -26848,7 +26980,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
0x001110100xxxxxxxx100xxxxxxxxxx
luti2. */
- return 3421;
+ return 3433;
}
}
}
@@ -26862,7 +26994,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
0x001110010xxxxxxxx000xxxxxxxxxx
luti4. */
- return 3423;
+ return 3435;
}
else
{
@@ -26870,7 +27002,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
0x001110010xxxxxxxx100xxxxxxxxxx
luti4. */
- return 3424;
+ return 3436;
}
}
else
@@ -26879,7 +27011,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
0x001110110xxxxxxxxx00xxxxxxxxxx
luti2. */
- return 3422;
+ return 3434;
}
}
}
@@ -26995,7 +27127,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
00001110x00xxxxxx10001xxxxxxxxxx
fmlallbb. */
- return 3445;
+ return 3457;
}
else
{
@@ -27003,7 +27135,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
01001110x00xxxxxx10001xxxxxxxxxx
fmlalltb. */
- return 3447;
+ return 3459;
}
}
else
@@ -27014,7 +27146,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
00001110x10xxxxxx10001xxxxxxxxxx
fmlallbt. */
- return 3446;
+ return 3458;
}
else
{
@@ -27022,7 +27154,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
01001110x10xxxxxx10001xxxxxxxxxx
fmlalltt. */
- return 3448;
+ return 3460;
}
}
}
@@ -27110,7 +27242,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
00001110x00xxxxxx11101xxxxxxxxxx
fcvtn. */
- return 3378;
+ return 3390;
}
else
{
@@ -27118,7 +27250,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
01001110x00xxxxxx11101xxxxxxxxxx
fcvtn2. */
- return 3379;
+ return 3391;
}
}
else
@@ -27127,7 +27259,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
0x001110x10xxxxxx11101xxxxxxxxxx
fcvtn. */
- return 3380;
+ return 3392;
}
}
}
@@ -27270,7 +27402,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
0x001110x00xxxxxx11111xxxxxxxxxx
fdot. */
- return 3437;
+ return 3449;
}
else
{
@@ -27280,7 +27412,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
0x001110010xxxxxx11111xxxxxxxxxx
fdot. */
- return 3439;
+ return 3451;
}
else
{
@@ -27290,7 +27422,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
00001110110xxxxxx11111xxxxxxxxxx
fmlalb. */
- return 3441;
+ return 3453;
}
else
{
@@ -27298,7 +27430,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
01001110110xxxxxx11111xxxxxxxxxx
fmlalt. */
- return 3442;
+ return 3454;
}
}
}
@@ -27572,7 +27704,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx101110110xxxxx0x1111xxxxxxxxxx
fscale. */
- return 3381;
+ return 3393;
}
}
}
@@ -28964,7 +29096,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x0101110001xxxx1011110xxxxxxxxxx
f1cvtl. */
- return 3374;
+ return 3386;
}
else
{
@@ -28972,7 +29104,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1101110001xxxx1011110xxxxxxxxxx
f1cvtl2. */
- return 3375;
+ return 3387;
}
}
else
@@ -28983,7 +29115,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x0101110101xxxx1011110xxxxxxxxxx
bf1cvtl. */
- return 3370;
+ return 3382;
}
else
{
@@ -28991,7 +29123,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1101110101xxxx1011110xxxxxxxxxx
bf1cvtl2. */
- return 3371;
+ return 3383;
}
}
}
@@ -29005,7 +29137,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x0101110011xxxx1011110xxxxxxxxxx
f2cvtl. */
- return 3376;
+ return 3388;
}
else
{
@@ -29013,7 +29145,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1101110011xxxx1011110xxxxxxxxxx
f2cvtl2. */
- return 3377;
+ return 3389;
}
}
else
@@ -29024,7 +29156,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x0101110111xxxx1011110xxxxxxxxxx
bf2cvtl. */
- return 3372;
+ return 3384;
}
else
{
@@ -29032,7 +29164,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1101110111xxxx1011110xxxxxxxxxx
bf2cvtl2. */
- return 3373;
+ return 3385;
}
}
}
@@ -31031,7 +31163,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx1011101x1xxxxx111111xxxxxxxxxx
fscale. */
- return 3382;
+ return 3394;
}
}
}
@@ -32747,7 +32879,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx00111100xxxxxx0000x0xxxxxxxxxx
fdot. */
- return 3438;
+ return 3450;
}
else
{
@@ -32777,7 +32909,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx00111101xxxxxx0000x0xxxxxxxxxx
fdot. */
- return 3440;
+ return 3452;
}
else
{
@@ -32787,7 +32919,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x000111111xxxxxx0000x0xxxxxxxxxx
fmlalb. */
- return 3443;
+ return 3455;
}
else
{
@@ -32795,7 +32927,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x100111111xxxxxx0000x0xxxxxxxxxx
fmlalt. */
- return 3444;
+ return 3456;
}
}
}
@@ -33337,7 +33469,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x010111100xxxxxx1000x0xxxxxxxxxx
fmlallbb. */
- return 3449;
+ return 3461;
}
else
{
@@ -33345,7 +33477,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x110111100xxxxxx1000x0xxxxxxxxxx
fmlalltb. */
- return 3451;
+ return 3463;
}
}
else
@@ -33376,7 +33508,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x0101111x1xxxxxx1000x0xxxxxxxxxx
fmlallbt. */
- return 3450;
+ return 3462;
}
else
{
@@ -33384,7 +33516,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1101111x1xxxxxx1000x0xxxxxxxxxx
fmlalltt. */
- return 3452;
+ return 3464;
}
}
}
^ permalink raw reply [flat|nested] 12+ messages in thread* [PATCH v1 6/7] aarch64: Add support for FEAT_SME_F16F16 fcvt and fcvtl instructions.
2024-07-12 16:35 [PATCH v1 0/7][Binutils] aarch64: Add support for FEAT_SME_F16F16 feature and instructions Srinath Parvathaneni
` (4 preceding siblings ...)
2024-07-12 16:35 ` [PATCH v1 5/7] aarch64: Add support for FEAT_SME_F16F16 fmla and fmls instructions (regenerated files) Srinath Parvathaneni
@ 2024-07-12 16:35 ` Srinath Parvathaneni
2024-07-12 16:35 ` [PATCH v1 7/7] aarch64: Add support for FEAT_SME_F16F16 fcvt and fcvtl instructions (regenerated files) Srinath Parvathaneni
2024-08-16 16:38 ` [PATCH v1 0/7][Binutils] aarch64: Add support for FEAT_SME_F16F16 feature and instructions Andrew Carlotti
7 siblings, 0 replies; 12+ messages in thread
From: Srinath Parvathaneni @ 2024-07-12 16:35 UTC (permalink / raw)
To: binutils; +Cc: richard.earnshaw, nickc, Srinath Parvathaneni
[-- Attachment #1: Type: text/plain, Size: 996 bytes --]
This patch adds support for FEAT_SME_F16F16 instructions fcvt and fcvtl,
which are available on passing command line flags +sme-f16f16 and the
spec is available here[1].
[1]: https://developer.arm.com/documentation/ddi0602/2024-06/SME-Instructions?lang=en
---
gas/testsuite/gas/aarch64/sme-f16f16-4-bad.d | 4 +++
gas/testsuite/gas/aarch64/sme-f16f16-4-bad.l | 27 ++++++++++++++++++++
gas/testsuite/gas/aarch64/sme-f16f16-4-bad.s | 18 +++++++++++++
gas/testsuite/gas/aarch64/sme-f16f16-4.d | 24 +++++++++++++++++
gas/testsuite/gas/aarch64/sme-f16f16-4.s | 17 ++++++++++++
opcodes/aarch64-tbl.h | 6 +++++
6 files changed, 96 insertions(+)
create mode 100644 gas/testsuite/gas/aarch64/sme-f16f16-4-bad.d
create mode 100644 gas/testsuite/gas/aarch64/sme-f16f16-4-bad.l
create mode 100644 gas/testsuite/gas/aarch64/sme-f16f16-4-bad.s
create mode 100644 gas/testsuite/gas/aarch64/sme-f16f16-4.d
create mode 100644 gas/testsuite/gas/aarch64/sme-f16f16-4.s
[-- Warning: decoded text below may be mangled, UTF-8 assumed --]
[-- Attachment #2: v1-0006-aarch64-Add-support-for-FEAT_SME_F16F16-fcvt-and-.patch --]
[-- Type: text/x-patch; name="v1-0006-aarch64-Add-support-for-FEAT_SME_F16F16-fcvt-and-.patch", Size: 5784 bytes --]
diff --git a/gas/testsuite/gas/aarch64/sme-f16f16-4-bad.d b/gas/testsuite/gas/aarch64/sme-f16f16-4-bad.d
new file mode 100644
index 00000000000..7ba01ad3b45
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sme-f16f16-4-bad.d
@@ -0,0 +1,4 @@
+#name: Test of invalid FEAT_SME_F16F16 fcvt and fcvtl instructions.
+#as: -march=armv9.4-a+sme-f16f16
+#source: sme-f16f16-4-bad.s
+#error_output: sme-f16f16-4-bad.l
diff --git a/gas/testsuite/gas/aarch64/sme-f16f16-4-bad.l b/gas/testsuite/gas/aarch64/sme-f16f16-4-bad.l
new file mode 100644
index 00000000000..66a3248c485
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sme-f16f16-4-bad.l
@@ -0,0 +1,27 @@
+.*: Assembler messages:
+.*: Error: operand mismatch -- `fcvt {z0.d-z1.d},z0.h'
+.*: Info: did you mean this\?
+.*: Info: fcvt {z0.s-z1.s}, z0.h
+.*: Error: start register out of range at operand 1 -- `fcvt {z29.s-z30.s},z0.h'
+.*: Error: operand mismatch -- `fcvt {z0.s-z1.s},z31.d'
+.*: Info: did you mean this\?
+.*: Info: fcvt {z0.s-z1.s}, z31.h
+.*: Error: start register out of range at operand 1 -- `fcvt {z15.s-z16.s},z31.h'
+.*: Error: operand mismatch -- `fcvt {z14.s-z15.s},z15.b'
+.*: Info: did you mean this\?
+.*: Info: fcvt {z14.s-z15.s}, z15.h
+.*: Error: type mismatch in vector register list at operand 1 -- `fcvt {z6.s,z7.b},z7.h'
+.*: Error: missing type suffix at operand 1 -- `fcvt {z2-z3},z3.h'
+.*: Error: operand mismatch -- `fcvtl {z0.d-z1.d},z0.h'
+.*: Info: did you mean this\?
+.*: Info: fcvtl {z0.s-z1.s}, z0.h
+.*: Error: start register out of range at operand 1 -- `fcvtl {z29.s-z30.s},z0.h'
+.*: Error: operand mismatch -- `fcvtl {z0.s-z1.s},z31.d'
+.*: Info: did you mean this\?
+.*: Info: fcvtl {z0.s-z1.s}, z31.h
+.*: Error: start register out of range at operand 1 -- `fcvtl {z15.s-z16.s},z31.h'
+.*: Error: operand mismatch -- `fcvtl {z14.s-z15.s},z15.b'
+.*: Info: did you mean this\?
+.*: Info: fcvtl {z14.s-z15.s}, z15.h
+.*: Error: type mismatch in vector register list at operand 1 -- `fcvtl {z6.s,z7.b},z7.h'
+.*: Error: missing type suffix at operand 1 -- `fcvtl {z2-z3},z3.h'
diff --git a/gas/testsuite/gas/aarch64/sme-f16f16-4-bad.s b/gas/testsuite/gas/aarch64/sme-f16f16-4-bad.s
new file mode 100644
index 00000000000..046a7dece0d
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sme-f16f16-4-bad.s
@@ -0,0 +1,18 @@
+/* FCVT (widening). */
+fcvt {z0.d - z1.d}, z0.h
+fcvt {z29.s - z30.s}, z0.h
+fcvt {z0.s - z1.s}, z31.d
+fcvt {z15.s - z16.s}, z31.h
+fcvt {z14.s - z15.s}, z15.b
+fcvt {z6.s, z7.b}, z7.h
+fcvt {z2 - z3}, z3.h
+
+/* FCVTL. */
+fcvtl {z0.d - z1.d}, z0.h
+fcvtl {z29.s - z30.s}, z0.h
+fcvtl {z0.s - z1.s}, z31.d
+fcvtl {z15.s - z16.s}, z31.h
+fcvtl {z14.s - z15.s}, z15.b
+fcvtl {z6.s, z7.b}, z7.h
+fcvtl {z2 - z3}, z3.h
+
diff --git a/gas/testsuite/gas/aarch64/sme-f16f16-4.d b/gas/testsuite/gas/aarch64/sme-f16f16-4.d
new file mode 100644
index 00000000000..c34dc704c0c
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sme-f16f16-4.d
@@ -0,0 +1,24 @@
+#name: Test of FEAT_SME_F16F16 fcvt and fcvtl instructions.
+#as: -march=armv9.4-a+sme-f16f16
+#objdump: -dr
+
+[^:]+: file format .*
+
+
+[^:]+:
+
+[^:]+:
+.*: c1a0e000 fcvt {z0.s-z1.s}, z0.h
+.*: c1a0e01e fcvt {z30.s-z31.s}, z0.h
+.*: c1a0e3e0 fcvt {z0.s-z1.s}, z31.h
+.*: c1a0e3fe fcvt {z30.s-z31.s}, z31.h
+.*: c1a0e1ee fcvt {z14.s-z15.s}, z15.h
+.*: c1a0e0e6 fcvt {z6.s-z7.s}, z7.h
+.*: c1a0e062 fcvt {z2.s-z3.s}, z3.h
+.*: c1a0e001 fcvtl {z0.s-z1.s}, z0.h
+.*: c1a0e01f fcvtl {z30.s-z31.s}, z0.h
+.*: c1a0e3e1 fcvtl {z0.s-z1.s}, z31.h
+.*: c1a0e3ff fcvtl {z30.s-z31.s}, z31.h
+.*: c1a0e1ef fcvtl {z14.s-z15.s}, z15.h
+.*: c1a0e0e7 fcvtl {z6.s-z7.s}, z7.h
+.*: c1a0e063 fcvtl {z2.s-z3.s}, z3.h
diff --git a/gas/testsuite/gas/aarch64/sme-f16f16-4.s b/gas/testsuite/gas/aarch64/sme-f16f16-4.s
new file mode 100644
index 00000000000..26e76c6a81f
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sme-f16f16-4.s
@@ -0,0 +1,17 @@
+/* FCVT (widening). */
+fcvt {z0.s - z1.s}, z0.h
+fcvt {z30.s - z31.s}, z0.h
+fcvt {z0.s - z1.s}, z31.h
+fcvt {z30.s - z31.s}, z31.h
+fcvt {z14.s - z15.s}, z15.h
+fcvt {z6.s - z7.s}, z7.h
+fcvt {z2.s - z3.s}, z3.h
+
+/* FCVTL. */
+fcvtl {z0.s - z1.s}, z0.h
+fcvtl {z30.s - z31.s}, z0.h
+fcvtl {z0.s - z1.s}, z31.h
+fcvtl {z30.s - z31.s}, z31.h
+fcvtl {z14.s - z15.s}, z15.h
+fcvtl {z6.s - z7.s}, z7.h
+fcvtl {z2.s - z3.s}, z3.h
diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h
index a67ab1d84da..149571994ff 100644
--- a/opcodes/aarch64-tbl.h
+++ b/opcodes/aarch64-tbl.h
@@ -1814,6 +1814,10 @@
{ \
QLF3(S_S,P_M,S_H), \
}
+#define OP_SVE_SH \
+{ \
+ QLF2(S_S,S_H), \
+}
#define OP_SVE_SHH \
{ \
QLF3(S_S,S_H,S_H), \
@@ -6711,6 +6715,8 @@ const struct aarch64_opcode aarch64_opcode_table[] =
SME_F16F16_INSN("fmls", 0xc1301c08, 0xfff09c18, sme_misc, 0, OP3 (SME_ZA_array_off3_0, SVE_ZnxN, SME_Zm), OP_SVE_HHH, F_OD (4), 0),
SME_F16F16_INSN("fmls", 0xc1a01018, 0xffe19c38, sme_misc, 0, OP3 (SME_ZA_array_off3_0, SME_Znx2, SME_Zmx2), OP_SVE_HHH, F_OD (2), 0),
SME_F16F16_INSN("fmls", 0xc1a11018, 0xffe39c78, sme_misc, 0, OP3 (SME_ZA_array_off3_0, SME_Znx4, SME_Zmx4), OP_SVE_HHH, F_OD (4), 0),
+ SME_F16F16_INSN("fcvt", 0xc1a0e000, 0xfffffc01, sme_misc, 0, OP2 (SME_Zdnx2, SVE_Zn), OP_SVE_SH, F_OD (2), 0),
+ SME_F16F16_INSN("fcvtl", 0xc1a0e001, 0xfffffc01, sme_misc, 0, OP2 (SME_Zdnx2, SVE_Zn), OP_SVE_SH, F_OD (2), 0),
/* SVE2p1 Instructions. */
SVE2p1_INSN("addqv",0x04052000, 0xff3fe000, sve2_urqvs, 0, OP3 (Vd, SVE_Pg3, SVE_Zn), OP_SVE_vUS_BHSD_BHSD, F_OPD_SIZE, 0),
^ permalink raw reply [flat|nested] 12+ messages in thread* [PATCH v1 7/7] aarch64: Add support for FEAT_SME_F16F16 fcvt and fcvtl instructions (regenerated files).
2024-07-12 16:35 [PATCH v1 0/7][Binutils] aarch64: Add support for FEAT_SME_F16F16 feature and instructions Srinath Parvathaneni
` (5 preceding siblings ...)
2024-07-12 16:35 ` [PATCH v1 6/7] aarch64: Add support for FEAT_SME_F16F16 fcvt and fcvtl instructions Srinath Parvathaneni
@ 2024-07-12 16:35 ` Srinath Parvathaneni
2024-08-16 16:38 ` [PATCH v1 0/7][Binutils] aarch64: Add support for FEAT_SME_F16F16 feature and instructions Andrew Carlotti
7 siblings, 0 replies; 12+ messages in thread
From: Srinath Parvathaneni @ 2024-07-12 16:35 UTC (permalink / raw)
To: binutils; +Cc: richard.earnshaw, nickc, Srinath Parvathaneni
[-- Attachment #1: Type: text/plain, Size: 247 bytes --]
This patch includes the regenerated files for
aarch64: Add support for FEAT_SME_F16F16 fcvt and fcvtl instructions.
---
opcodes/aarch64-dis-2.c | 546 +++++++++++++++++++++-------------------
1 file changed, 284 insertions(+), 262 deletions(-)
[-- Warning: decoded text below may be mangled, UTF-8 assumed --]
[-- Attachment #2: v1-0007-aarch64-Add-support-for-FEAT_SME_F16F16-fcvt-and-.patch --]
[-- Type: text/x-patch; name="v1-0007-aarch64-Add-support-for-FEAT_SME_F16F16-fcvt-and-.patch", Size: 137137 bytes --]
diff --git a/opcodes/aarch64-dis-2.c b/opcodes/aarch64-dis-2.c
index 446c3b54609..edef50ef791 100644
--- a/opcodes/aarch64-dis-2.c
+++ b/opcodes/aarch64-dis-2.c
@@ -271,7 +271,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000000x000101x00xxxxxxxxxxxxxx
luti4. */
- return 3442;
+ return 3444;
}
else
{
@@ -310,7 +310,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000000xx01101x00xxxxxxxxxxxxxx
luti4. */
- return 3443;
+ return 3445;
}
else
{
@@ -542,7 +542,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000000010011x1xxxx00xxxxxxxxxx
movt. */
- return 3444;
+ return 3446;
}
}
else
@@ -1366,7 +1366,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx000000101xxxxxxxxxxxxxxxx00xxx
fmopa. */
- return 3510;
+ return 3512;
}
else
{
@@ -1374,7 +1374,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx000000101xxxxxxxxxxxxxxxx01xxx
fmopa. */
- return 3509;
+ return 3511;
}
}
else
@@ -1722,7 +1722,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx0000010001xxxx1xx0xxxxx1000xxx
fmlall. */
- return 3503;
+ return 3505;
}
}
}
@@ -1772,7 +1772,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx0000010001xxxx1xx1xxxxx100xxxx
fdot. */
- return 3488;
+ return 3490;
}
}
}
@@ -2179,7 +2179,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x10000011001xxxxxxx0xxxxxx100xxx
fmlall. */
- return 3502;
+ return 3504;
}
}
}
@@ -2284,7 +2284,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x10000011001xxxxxxx1xxxxxx10xxxx
fmlal. */
- return 3495;
+ return 3497;
}
}
}
@@ -2468,7 +2468,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x10000011001xxxxxxx1xxxxxx11xxxx
fmlal. */
- return 3494;
+ return 3496;
}
}
}
@@ -2510,7 +2510,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx0000010100xxxxxxxxxxxxxxxx0xxx
fmlall. */
- return 3501;
+ return 3503;
}
else
{
@@ -2878,7 +2878,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xxx000010101xxxx0xx0xxxxxx111xxx
fdot. */
- return 3481;
+ return 3483;
}
else
{
@@ -2947,7 +2947,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xxx000010101xxxx1xx0xxxxxx001xxx
fdot. */
- return 3482;
+ return 3484;
}
else
{
@@ -3026,7 +3026,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx0000011100xxxxxxx0xxxxxxx0xxxx
fmlal. */
- return 3493;
+ return 3495;
}
else
{
@@ -3081,7 +3081,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx0000011101xxxx0xx01xxxxx00xxxx
fvdotb. */
- return 3512;
+ return 3514;
}
else
{
@@ -3099,7 +3099,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx0000011101xxxxxxx0xxxxxx10xxxx
fdot. */
- return 3487;
+ return 3489;
}
}
}
@@ -3173,7 +3173,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx0000011101xxxxxxx1xxxxxx10xxxx
fvdot. */
- return 3511;
+ return 3513;
}
}
}
@@ -3253,7 +3253,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx000001110xxxxx0xx01xxxxxx1xxxx
fvdott. */
- return 3513;
+ return 3515;
}
else
{
@@ -3430,7 +3430,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x10000011x1xxxx00xx000xxxx10000x
fmlall. */
- return 3507;
+ return 3509;
}
else
{
@@ -3438,7 +3438,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x10000011x1xxxx10xx000xxxx10000x
fmlall. */
- return 3508;
+ return 3510;
}
}
}
@@ -3493,7 +3493,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001xx10xxxx0xx000xxxxx00x1x
fmlall. */
- return 3505;
+ return 3507;
}
else
{
@@ -3501,7 +3501,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001xx11xxxx0xx000xxxxx00x1x
fmlall. */
- return 3506;
+ return 3508;
}
}
}
@@ -3555,7 +3555,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x10000011x1xxxx00xx100xxxx100xxx
fdot. */
- return 3491;
+ return 3493;
}
else
{
@@ -3563,7 +3563,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x10000011x1xxxx10xx100xxxx100xxx
fdot. */
- return 3492;
+ return 3494;
}
}
}
@@ -3625,7 +3625,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001101xxxx00xx010xxxx1000xx
fmlal. */
- return 3499;
+ return 3501;
}
else
{
@@ -3633,7 +3633,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001101xxxx10xx010xxxx1000xx
fmlal. */
- return 3500;
+ return 3502;
}
}
}
@@ -3688,7 +3688,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001xx10xxxx0xx010xxxxx001xx
fmlal. */
- return 3497;
+ return 3499;
}
else
{
@@ -3696,7 +3696,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001xx11xxxx0xx010xxxxx001xx
fmlal. */
- return 3498;
+ return 3500;
}
}
}
@@ -3765,7 +3765,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001xx11xxxx0xx001xxxxx000xx
fmlall. */
- return 3504;
+ return 3506;
}
}
else
@@ -3848,7 +3848,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001xx11xxxx0xx011xxxxx00xxx
fmlal. */
- return 3496;
+ return 3498;
}
}
else
@@ -3881,7 +3881,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x10000011x10x1x00xx111xxxxx00xxx
fadd. */
- return 3445;
+ return 3447;
}
}
else
@@ -3900,7 +3900,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x10000011x10x1x10xx111xxxxx00xxx
fadd. */
- return 3446;
+ return 3448;
}
}
}
@@ -4036,7 +4036,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x10000011x1xxxx00xx100xxxx110xxx
fdot. */
- return 3485;
+ return 3487;
}
else
{
@@ -4044,7 +4044,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x10000011x1xxxx10xx100xxxx110xxx
fdot. */
- return 3486;
+ return 3488;
}
}
}
@@ -4337,7 +4337,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x10000010x10xxxx0xx100xxxxx01xxx
fdot. */
- return 3489;
+ return 3491;
}
else
{
@@ -4345,7 +4345,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x10000010x11xxxx0xx100xxxxx01xxx
fdot. */
- return 3490;
+ return 3492;
}
}
else
@@ -4648,7 +4648,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x10000011x10x1x00xx111xxxxx01xxx
fsub. */
- return 3447;
+ return 3449;
}
}
else
@@ -4667,7 +4667,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x10000011x10x1x10xx111xxxxx01xxx
fsub. */
- return 3448;
+ return 3450;
}
}
}
@@ -4741,7 +4741,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x10000010x10xxxx0xx100xxxxx11xxx
fdot. */
- return 3483;
+ return 3485;
}
else
{
@@ -4749,7 +4749,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x10000010x11xxxx0xx100xxxxx11xxx
fdot. */
- return 3484;
+ return 3486;
}
}
else
@@ -5304,7 +5304,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001xx1xxxxx101000xx1x0xxxx0
fscale. */
- return 3419;
+ return 3421;
}
}
else
@@ -5397,21 +5397,54 @@ aarch64_opcode_lookup_1 (uint32_t word)
{
if (((word >> 17) & 0x1) == 0)
{
- if (((word >> 5) & 0x1) == 0)
+ if (((word >> 18) & 0x1) == 0)
{
- if (((word >> 18) & 0x1) == 0)
+ if (((word >> 19) & 0x1) == 0)
{
- if (((word >> 19) & 0x1) == 0)
+ if (((word >> 22) & 0x1) == 0)
{
- if (((word >> 22) & 0x1) == 0)
+ if (((word >> 23) & 0x1) == 0)
{
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- x1000001x01x0000111000xxxx0xxxxx
- fcvt. */
- return 2534;
+ if (((word >> 5) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x1000001001x0000111000xxxx0xxxxx
+ fcvt. */
+ return 2534;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x1000001001x0000111000xxxx1xxxxx
+ fcvtn. */
+ return 2535;
+ }
}
else
+ {
+ if (((word >> 0) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x1000001101x0000111000xxxxxxxxx0
+ fcvt. */
+ return 3339;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x1000001101x0000111000xxxxxxxxx1
+ fcvtl. */
+ return 3340;
+ }
+ }
+ }
+ else
+ {
+ if (((word >> 5) & 0x1) == 0)
{
/* 33222222222211111111110000000000
10987654321098765432109876543210
@@ -5419,28 +5452,39 @@ aarch64_opcode_lookup_1 (uint32_t word)
bfcvt. */
return 2502;
}
- }
- else
- {
- if (((word >> 20) & 0x1) == 0)
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- x1000001xx101000111000xxxx0xxxxx
- frintn. */
- return 2594;
- }
else
{
/* 33222222222211111111110000000000
10987654321098765432109876543210
- x1000001xx111000111000xxxx0xxxxx
- frintn. */
- return 2595;
+ x1000001x11x0000111000xxxx1xxxxx
+ bfcvtn. */
+ return 2503;
}
}
}
else
+ {
+ if (((word >> 20) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x1000001xx101000111000xxxxxxxxxx
+ frintn. */
+ return 2594;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x1000001xx111000111000xxxxxxxxxx
+ frintn. */
+ return 2595;
+ }
+ }
+ }
+ else
+ {
+ if (((word >> 5) & 0x1) == 0)
{
if (((word >> 19) & 0x1) == 0)
{
@@ -5452,7 +5496,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001x0100100111000xxxx0xxxxx
fcvt. */
- return 3416;
+ return 3418;
}
else
{
@@ -5460,7 +5504,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001x1100100111000xxxx0xxxxx
bfcvt. */
- return 3411;
+ return 3413;
}
}
else
@@ -5469,7 +5513,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001xx110100111000xxxx0xxxxx
fcvt. */
- return 3417;
+ return 3419;
}
}
else
@@ -5492,35 +5536,13 @@ aarch64_opcode_lookup_1 (uint32_t word)
}
}
}
- }
- else
- {
- if (((word >> 18) & 0x1) == 0)
- {
- if (((word >> 22) & 0x1) == 0)
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- x1000001x01xx000111000xxxx1xxxxx
- fcvtn. */
- return 2535;
- }
- else
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- x1000001x11xx000111000xxxx1xxxxx
- bfcvtn. */
- return 2503;
- }
- }
else
{
/* 33222222222211111111110000000000
10987654321098765432109876543210
x1000001xx1xx100111000xxxx1xxxxx
fcvtn. */
- return 3418;
+ return 3420;
}
}
}
@@ -5603,7 +5625,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x10000010010x110111000xxxxxxxxx0
f1cvt. */
- return 3412;
+ return 3414;
}
else
{
@@ -5611,7 +5633,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x10000011010x110111000xxxxxxxxx0
f2cvt. */
- return 3413;
+ return 3415;
}
}
else
@@ -5622,7 +5644,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x10000010110x110111000xxxxxxxxx0
bf1cvt. */
- return 3407;
+ return 3409;
}
else
{
@@ -5630,7 +5652,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x10000011110x110111000xxxxxxxxx0
bf2cvt. */
- return 3408;
+ return 3410;
}
}
}
@@ -5665,7 +5687,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001001xxx10111000xxxxxxxxx1
f1cvtl. */
- return 3414;
+ return 3416;
}
else
{
@@ -5673,7 +5695,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001101xxx10111000xxxxxxxxx1
f2cvtl. */
- return 3415;
+ return 3417;
}
}
else
@@ -5684,7 +5706,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001011xxx10111000xxxxxxxxx1
bf1cvtl. */
- return 3409;
+ return 3411;
}
else
{
@@ -5692,7 +5714,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001111xxx10111000xxxxxxxxx1
bf2cvtl. */
- return 3410;
+ return 3412;
}
}
}
@@ -5961,7 +5983,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001xx1xxxxx1x1100xx100xxxx0
fscale. */
- return 3421;
+ return 3423;
}
}
else
@@ -6137,16 +6159,16 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001xx1xxxxx1x1010xx100xxxx0
fscale. */
- return 3420;
- }
- else
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- x1000001xx1xxxxx1x1110xx100xxxx0
- fscale. */
return 3422;
}
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x1000001xx1xxxxx1x1110xx100xxxx0
+ fscale. */
+ return 3424;
+ }
}
}
else
@@ -11313,7 +11335,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x0x11010000xxxxxxx1xxxxxxxxxxxxx
addpt. */
- return 3423;
+ return 3425;
}
else
{
@@ -11321,7 +11343,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1x11010000xxxxxxx1xxxxxxxxxxxxx
subpt. */
- return 3424;
+ return 3426;
}
}
}
@@ -12239,7 +12261,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xxxx1011x11xxxxx0xxxxxxxxxxxxxxx
maddpt. */
- return 3425;
+ return 3427;
}
else
{
@@ -12247,7 +12269,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xxxx1011x11xxxxx1xxxxxxxxxxxxxxx
msubpt. */
- return 3426;
+ return 3428;
}
}
}
@@ -12332,7 +12354,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
000001x0xx000100000xxxxxxxxxxxxx
addpt. */
- return 3427;
+ return 3429;
}
else
{
@@ -12439,7 +12461,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
000001x0xx000101000xxxxxxxxxxxxx
subpt. */
- return 3429;
+ return 3431;
}
else
{
@@ -12644,7 +12666,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
000001x0xx1xxxxx000010xxxxxxxxxx
addpt. */
- return 3428;
+ return 3430;
}
else
{
@@ -12685,7 +12707,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
000001x0xx1xxxxx000011xxxxxxxxxx
subpt. */
- return 3430;
+ return 3432;
}
else
{
@@ -14343,7 +14365,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
010001x0xx0xxxxx110100xxxxxxxxxx
mlapt. */
- return 3432;
+ return 3434;
}
}
else
@@ -14373,7 +14395,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
010001x0xx0xxxxx110110xxxxxxxxxx
madpt. */
- return 3431;
+ return 3433;
}
}
}
@@ -14681,7 +14703,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
000001x0xx00x100001xxxxxxxxxxxxx
smaxqv. */
- return 3341;
+ return 3343;
}
else
{
@@ -14689,7 +14711,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
000001x0xx01x100001xxxxxxxxxxxxx
orqv. */
- return 3352;
+ return 3354;
}
}
else
@@ -14700,7 +14722,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
000001x0xx0x0101001xxxxxxxxxxxxx
addqv. */
- return 3339;
+ return 3341;
}
else
{
@@ -14710,7 +14732,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
000001x0xx001101001xxxxxxxxxxxxx
umaxqv. */
- return 3343;
+ return 3345;
}
else
{
@@ -14718,7 +14740,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
000001x0xx011101001xxxxxxxxxxxxx
eorqv. */
- return 3345;
+ return 3347;
}
}
}
@@ -14755,7 +14777,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
000001x0xx00x110001xxxxxxxxxxxxx
sminqv. */
- return 3342;
+ return 3344;
}
else
{
@@ -14763,7 +14785,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
000001x0xx01x110001xxxxxxxxxxxxx
andqv. */
- return 3340;
+ return 3342;
}
}
}
@@ -14783,7 +14805,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
000001x0xx0xx111001xxxxxxxxxxxxx
uminqv. */
- return 3344;
+ return 3346;
}
}
}
@@ -15527,7 +15549,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
110001x0x00xxxxx101xxxxxxxxxxxxx
ld1q. */
- return 3368;
+ return 3370;
}
else
{
@@ -16541,7 +16563,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
010001x0xx0xxxxx111x00xxxxxxxxxx
zipq1. */
- return 3358;
+ return 3360;
}
else
{
@@ -16551,7 +16573,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
010001x0xx0xxxxx111010xxxxxxxxxx
uzpq1. */
- return 3356;
+ return 3358;
}
else
{
@@ -16559,7 +16581,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
010001x0xx0xxxxx111110xxxxxxxxxx
tblq. */
- return 3353;
+ return 3355;
}
}
}
@@ -16571,7 +16593,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
010001x0xx0xxxxx111x01xxxxxxxxxx
zipq2. */
- return 3359;
+ return 3361;
}
else
{
@@ -16579,7 +16601,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
010001x0xx0xxxxx111x11xxxxxxxxxx
uzpq2. */
- return 3357;
+ return 3359;
}
}
}
@@ -17059,7 +17081,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
111001x0x00xxxxx000xxxxxxxxxxxxx
st3q. */
- return 3377;
+ return 3379;
}
else
{
@@ -17069,16 +17091,16 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
111001x0010xxxxx000xxxxxxxxxxxxx
st2q. */
- return 3376;
- }
- else
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- 111001x0110xxxxx000xxxxxxxxxxxxx
- st4q. */
return 3378;
}
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 111001x0110xxxxx000xxxxxxxxxxxxx
+ st4q. */
+ return 3380;
+ }
}
}
else
@@ -17524,7 +17546,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x0xx0x0000101xxxxxxxxxxxxx
faddqv. */
- return 3346;
+ return 3348;
}
else
{
@@ -17541,7 +17563,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x0xx0xx100101xxxxxxxxxxxxx
fmaxnmqv. */
- return 3347;
+ return 3349;
}
}
else
@@ -17582,7 +17604,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x0xx0xx110101xxxxxxxxxxxxx
fmaxqv. */
- return 3348;
+ return 3350;
}
}
}
@@ -17604,7 +17626,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x0xx0xx101101xxxxxxxxxxxxx
fminnmqv. */
- return 3349;
+ return 3351;
}
}
else
@@ -17623,7 +17645,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x0xx0xx111101xxxxxxxxxxxxx
fminqv. */
- return 3350;
+ return 3352;
}
}
}
@@ -17743,7 +17765,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
101001x0xx01xxxx111xxxxxxxxxxxxx
ld2q. */
- return 3369;
+ return 3371;
}
}
}
@@ -17879,7 +17901,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
101001x0xx1xxxxx100xxxxxxxxxxxxx
ld2q. */
- return 3372;
+ return 3374;
}
}
else
@@ -18024,7 +18046,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
111001x00x1xxxxx000xxxxxxxxxxxxx
st2q. */
- return 3379;
+ return 3381;
}
}
else
@@ -18067,7 +18089,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
111001x0101xxxxx000xxxxxxxxxxxxx
st3q. */
- return 3380;
+ return 3382;
}
}
else
@@ -18108,7 +18130,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
111001x0111xxxxx000xxxxxxxxxxxxx
st4q. */
- return 3381;
+ return 3383;
}
}
}
@@ -18137,7 +18159,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x0001xxxxx0100x1xxxxxxxxxx
fdot. */
- return 3468;
+ return 3470;
}
}
else
@@ -18146,7 +18168,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x0001xxxxx0101xxxxxxxxxxxx
fmlalb. */
- return 3470;
+ return 3472;
}
}
else
@@ -18187,7 +18209,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x0101xxxxx0101xxxxxxxxxxxx
fmlalt. */
- return 3480;
+ return 3482;
}
}
else
@@ -18220,7 +18242,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x0011xxxxx010xx1xxxxxxxxxx
fdot. */
- return 3466;
+ return 3468;
}
}
else
@@ -18291,7 +18313,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x11001x0001xxxxx100010xxxxxxxxxx
fmlallbb. */
- return 3471;
+ return 3473;
}
}
else
@@ -18300,7 +18322,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x11001x0001xxxxx1000x1xxxxxxxxxx
fdot. */
- return 3467;
+ return 3469;
}
}
else
@@ -18309,7 +18331,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x11001x0001xxxxx1100xxxxxxxxxxxx
fmlallbb. */
- return 3472;
+ return 3474;
}
}
else
@@ -18318,7 +18340,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x11001x0001xxxxx1x01xxxxxxxxxxxx
fmlallbt. */
- return 3473;
+ return 3475;
}
}
else
@@ -18345,7 +18367,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x0101xxxxx100010xxxxxxxxxx
fmlalb. */
- return 3469;
+ return 3471;
}
}
else
@@ -18363,7 +18385,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x0101xxxxx1100xxxxxxxxxxxx
fmlalltb. */
- return 3476;
+ return 3478;
}
}
else
@@ -18372,7 +18394,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x0101xxxxx1x01xxxxxxxxxxxx
fmlalt. */
- return 3479;
+ return 3481;
}
}
else
@@ -18405,7 +18427,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x11001x0011xxxxx100xx1xxxxxxxxxx
fdot. */
- return 3465;
+ return 3467;
}
}
else
@@ -18414,7 +18436,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x11001x0011xxxxx110xxxxxxxxxxxxx
fmlallbt. */
- return 3474;
+ return 3476;
}
}
else
@@ -18446,7 +18468,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x0111xxxxx110xxxxxxxxxxxxx
fmlalltt. */
- return 3478;
+ return 3480;
}
}
else
@@ -18745,7 +18767,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
111001x0xx1xxxxx001xxxxxxxxxxxxx
st1q. */
- return 3375;
+ return 3377;
}
}
else
@@ -18760,16 +18782,16 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x11001x0001xxxxx1010xxxxxxxxxxxx
fmlalltb. */
- return 3475;
- }
- else
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- x11001x0001xxxxx1011xxxxxxxxxxxx
- fmlalltt. */
return 3477;
}
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x11001x0001xxxxx1011xxxxxxxxxxxx
+ fmlalltt. */
+ return 3479;
+ }
}
else
{
@@ -19486,7 +19508,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
000001x1001010x0001110xxxxxxxxxx
pmov. */
- return 3360;
+ return 3362;
}
else
{
@@ -19494,7 +19516,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
000001x1001011x0001110xxxxxxxxxx
pmov. */
- return 3361;
+ return 3363;
}
}
else
@@ -19503,7 +19525,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
000001x101101xx0001110xxxxxxxxxx
pmov. */
- return 3362;
+ return 3364;
}
}
else
@@ -19512,7 +19534,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
000001x11x101xx0001110xxxxxxxxxx
pmov. */
- return 3363;
+ return 3365;
}
}
else
@@ -19558,7 +19580,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
000001x1001x10x1001110xxxxxxxxxx
pmov. */
- return 3364;
+ return 3366;
}
else
{
@@ -19566,7 +19588,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
000001x1001x11x1001110xxxxxxxxxx
pmov. */
- return 3365;
+ return 3367;
}
}
else
@@ -19575,7 +19597,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
000001x1011x1xx1001110xxxxxxxxxx
pmov. */
- return 3366;
+ return 3368;
}
}
else
@@ -19584,7 +19606,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
000001x11x1x1xx1001110xxxxxxxxxx
pmov. */
- return 3367;
+ return 3369;
}
}
}
@@ -19603,7 +19625,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
000001x1x01xxxxx001001xxxxxxxxxx
dupq. */
- return 3351;
+ return 3353;
}
else
{
@@ -19611,7 +19633,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
000001x1x11xxxxx001001xxxxxxxxxx
extq. */
- return 3355;
+ return 3357;
}
}
else
@@ -19620,7 +19642,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
000001x1xx1xxxxx001101xxxxxxxxxx
tbxq. */
- return 3354;
+ return 3356;
}
}
else
@@ -21223,7 +21245,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
010001x1xx1xxxxx101100xxxxxxxxxx
luti2. */
- return 3437;
+ return 3439;
}
}
else
@@ -21232,7 +21254,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
010001x1xx1xxxxx101x10xxxxxxxxxx
luti2. */
- return 3438;
+ return 3440;
}
}
else
@@ -21245,7 +21267,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
010001x1xx1xxxxx101001xxxxxxxxxx
luti4. */
- return 3439;
+ return 3441;
}
else
{
@@ -21253,7 +21275,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
010001x1xx1xxxxx101101xxxxxxxxxx
luti4. */
- return 3440;
+ return 3442;
}
}
else
@@ -21262,7 +21284,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
010001x1xx1xxxxx101x11xxxxxxxxxx
luti4. */
- return 3441;
+ return 3443;
}
}
}
@@ -22213,7 +22235,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x1xx001000001x00xxxxxxxxxx
f1cvt. */
- return 3399;
+ return 3401;
}
else
{
@@ -22221,7 +22243,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x1xx001000001x10xxxxxxxxxx
bf1cvt. */
- return 3395;
+ return 3397;
}
}
else
@@ -22232,7 +22254,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x1xx001000001x01xxxxxxxxxx
f2cvt. */
- return 3400;
+ return 3402;
}
else
{
@@ -22240,7 +22262,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x1xx001000001x11xxxxxxxxxx
bf2cvt. */
- return 3396;
+ return 3398;
}
}
}
@@ -22285,7 +22307,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x1xx0x1010001x00xxxxxxxxxx
fcvtn. */
- return 3404;
+ return 3406;
}
else
{
@@ -22293,7 +22315,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x1xx0x1010001x10xxxxxxxxxx
bfcvtn. */
- return 3403;
+ return 3405;
}
}
else
@@ -22304,7 +22326,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x1xx0x1010001x01xxxxxxxxxx
fcvtnb. */
- return 3405;
+ return 3407;
}
else
{
@@ -22312,7 +22334,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x1xx0x1010001x11xxxxxxxxxx
fcvtnt. */
- return 3406;
+ return 3408;
}
}
}
@@ -22373,7 +22395,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x1xx0x1001001x00xxxxxxxxxx
f1cvtlt. */
- return 3401;
+ return 3403;
}
else
{
@@ -22381,7 +22403,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x1xx0x1001001x10xxxxxxxxxx
bf1cvtlt. */
- return 3397;
+ return 3399;
}
}
else
@@ -22392,7 +22414,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x1xx0x1001001x01xxxxxxxxxx
f2cvtlt. */
- return 3402;
+ return 3404;
}
else
{
@@ -22400,7 +22422,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x1xx0x1001001x11xxxxxxxxxx
bf2cvtlt. */
- return 3398;
+ return 3400;
}
}
}
@@ -23726,7 +23748,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
101001x10x01xxxx111xxxxxxxxxxxxx
ld3q. */
- return 3370;
+ return 3372;
}
else
{
@@ -23734,7 +23756,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
101001x11x01xxxx111xxxxxxxxxxxxx
ld4q. */
- return 3371;
+ return 3373;
}
}
}
@@ -24907,7 +24929,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
101001x10x1xxxxx100xxxxxxxxxxxxx
ld3q. */
- return 3373;
+ return 3375;
}
else
{
@@ -24915,7 +24937,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
101001x11x1xxxxx100xxxxxxxxxxxxx
ld4q. */
- return 3374;
+ return 3376;
}
}
else
@@ -26980,29 +27002,29 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
0x001110100xxxxxxxx100xxxxxxxxxx
luti2. */
- return 3433;
- }
- }
- }
- else
- {
- if (((word >> 23) & 0x1) == 0)
- {
- if (((word >> 12) & 0x1) == 0)
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- 0x001110010xxxxxxxx000xxxxxxxxxx
- luti4. */
return 3435;
}
+ }
+ }
+ else
+ {
+ if (((word >> 23) & 0x1) == 0)
+ {
+ if (((word >> 12) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 0x001110010xxxxxxxx000xxxxxxxxxx
+ luti4. */
+ return 3437;
+ }
else
{
/* 33222222222211111111110000000000
10987654321098765432109876543210
0x001110010xxxxxxxx100xxxxxxxxxx
luti4. */
- return 3436;
+ return 3438;
}
}
else
@@ -27011,7 +27033,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
0x001110110xxxxxxxxx00xxxxxxxxxx
luti2. */
- return 3434;
+ return 3436;
}
}
}
@@ -27127,7 +27149,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
00001110x00xxxxxx10001xxxxxxxxxx
fmlallbb. */
- return 3457;
+ return 3459;
}
else
{
@@ -27135,7 +27157,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
01001110x00xxxxxx10001xxxxxxxxxx
fmlalltb. */
- return 3459;
+ return 3461;
}
}
else
@@ -27146,7 +27168,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
00001110x10xxxxxx10001xxxxxxxxxx
fmlallbt. */
- return 3458;
+ return 3460;
}
else
{
@@ -27154,7 +27176,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
01001110x10xxxxxx10001xxxxxxxxxx
fmlalltt. */
- return 3460;
+ return 3462;
}
}
}
@@ -27242,7 +27264,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
00001110x00xxxxxx11101xxxxxxxxxx
fcvtn. */
- return 3390;
+ return 3392;
}
else
{
@@ -27250,7 +27272,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
01001110x00xxxxxx11101xxxxxxxxxx
fcvtn2. */
- return 3391;
+ return 3393;
}
}
else
@@ -27259,7 +27281,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
0x001110x10xxxxxx11101xxxxxxxxxx
fcvtn. */
- return 3392;
+ return 3394;
}
}
}
@@ -27402,7 +27424,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
0x001110x00xxxxxx11111xxxxxxxxxx
fdot. */
- return 3449;
+ return 3451;
}
else
{
@@ -27412,7 +27434,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
0x001110010xxxxxx11111xxxxxxxxxx
fdot. */
- return 3451;
+ return 3453;
}
else
{
@@ -27422,7 +27444,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
00001110110xxxxxx11111xxxxxxxxxx
fmlalb. */
- return 3453;
+ return 3455;
}
else
{
@@ -27430,7 +27452,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
01001110110xxxxxx11111xxxxxxxxxx
fmlalt. */
- return 3454;
+ return 3456;
}
}
}
@@ -27704,7 +27726,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx101110110xxxxx0x1111xxxxxxxxxx
fscale. */
- return 3393;
+ return 3395;
}
}
}
@@ -29096,7 +29118,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x0101110001xxxx1011110xxxxxxxxxx
f1cvtl. */
- return 3386;
+ return 3388;
}
else
{
@@ -29104,7 +29126,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1101110001xxxx1011110xxxxxxxxxx
f1cvtl2. */
- return 3387;
+ return 3389;
}
}
else
@@ -29115,7 +29137,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x0101110101xxxx1011110xxxxxxxxxx
bf1cvtl. */
- return 3382;
+ return 3384;
}
else
{
@@ -29123,7 +29145,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1101110101xxxx1011110xxxxxxxxxx
bf1cvtl2. */
- return 3383;
+ return 3385;
}
}
}
@@ -29137,7 +29159,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x0101110011xxxx1011110xxxxxxxxxx
f2cvtl. */
- return 3388;
+ return 3390;
}
else
{
@@ -29145,7 +29167,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1101110011xxxx1011110xxxxxxxxxx
f2cvtl2. */
- return 3389;
+ return 3391;
}
}
else
@@ -29156,7 +29178,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x0101110111xxxx1011110xxxxxxxxxx
bf2cvtl. */
- return 3384;
+ return 3386;
}
else
{
@@ -29164,7 +29186,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1101110111xxxx1011110xxxxxxxxxx
bf2cvtl2. */
- return 3385;
+ return 3387;
}
}
}
@@ -31163,7 +31185,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx1011101x1xxxxx111111xxxxxxxxxx
fscale. */
- return 3394;
+ return 3396;
}
}
}
@@ -32879,7 +32901,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx00111100xxxxxx0000x0xxxxxxxxxx
fdot. */
- return 3450;
+ return 3452;
}
else
{
@@ -32909,7 +32931,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx00111101xxxxxx0000x0xxxxxxxxxx
fdot. */
- return 3452;
+ return 3454;
}
else
{
@@ -32919,7 +32941,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x000111111xxxxxx0000x0xxxxxxxxxx
fmlalb. */
- return 3455;
+ return 3457;
}
else
{
@@ -32927,7 +32949,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x100111111xxxxxx0000x0xxxxxxxxxx
fmlalt. */
- return 3456;
+ return 3458;
}
}
}
@@ -33469,16 +33491,16 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x010111100xxxxxx1000x0xxxxxxxxxx
fmlallbb. */
- return 3461;
- }
- else
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- x110111100xxxxxx1000x0xxxxxxxxxx
- fmlalltb. */
return 3463;
}
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x110111100xxxxxx1000x0xxxxxxxxxx
+ fmlalltb. */
+ return 3465;
+ }
}
else
{
@@ -33508,16 +33530,16 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x0101111x1xxxxxx1000x0xxxxxxxxxx
fmlallbt. */
- return 3462;
- }
- else
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- x1101111x1xxxxxx1000x0xxxxxxxxxx
- fmlalltt. */
return 3464;
}
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x1101111x1xxxxxx1000x0xxxxxxxxxx
+ fmlalltt. */
+ return 3466;
+ }
}
}
}
^ permalink raw reply [flat|nested] 12+ messages in thread* Re: [PATCH v1 0/7][Binutils] aarch64: Add support for FEAT_SME_F16F16 feature and instructions.
2024-07-12 16:35 [PATCH v1 0/7][Binutils] aarch64: Add support for FEAT_SME_F16F16 feature and instructions Srinath Parvathaneni
` (6 preceding siblings ...)
2024-07-12 16:35 ` [PATCH v1 7/7] aarch64: Add support for FEAT_SME_F16F16 fcvt and fcvtl instructions (regenerated files) Srinath Parvathaneni
@ 2024-08-16 16:38 ` Andrew Carlotti
2024-08-16 16:50 ` Andrew Carlotti
7 siblings, 1 reply; 12+ messages in thread
From: Andrew Carlotti @ 2024-08-16 16:38 UTC (permalink / raw)
To: Srinath Parvathaneni; +Cc: binutils, richard.earnshaw, nickc
On Fri, Jul 12, 2024 at 05:35:30PM +0100, Srinath Parvathaneni wrote:
> Hi,
>
> This patch series adds the support for aarch64 FEAT_SME_F16F16 feature
> and all the instructions by "+sme-f16f16" flag to -march and the spec
> can be found here [1].
>
> Srinath Parvathaneni (7):
> aarch64: Add support for FEAT_SME_F16F16 feature.
> aarch64: Add support for FEAT_SME_F16F16 fmops and fmopa instructions.
> aarch64: Add support for FEAT_SME_F16F16 fmopa and fmops instructions
> (regenerated files).
> aarch64: Add support for FEAT_SME_F16F16 fmla and fmls instructions.
> aarch64: Add support for FEAT_SME_F16F16 fmla and fmls instructions
> (regenerated files).
> aarch64: Add support for FEAT_SME_F16F16 fcvt and fcvtl instructions.
> aarch64: Add support for FEAT_SME_F16F16 fcvt and fcvtl instructions
> (regenerated files).
>
> Regression testing for aarch64-none-elf target and found no regressions.
>
> Ok for binutils-master?
>
> [1]: https://developer.arm.com/documentation/ddi0602/2024-06/SME-Instructions?lang=en
>
> Regards,
> Srinath.
There's a couple of test gaps I've mention in reply to patch 4/7, but this
otherwise looks good to me (though I can't formally approve it).
^ permalink raw reply [flat|nested] 12+ messages in thread* Re: [PATCH v1 0/7][Binutils] aarch64: Add support for FEAT_SME_F16F16 feature and instructions.
2024-08-16 16:38 ` [PATCH v1 0/7][Binutils] aarch64: Add support for FEAT_SME_F16F16 feature and instructions Andrew Carlotti
@ 2024-08-16 16:50 ` Andrew Carlotti
2024-08-19 7:41 ` Jan Beulich
0 siblings, 1 reply; 12+ messages in thread
From: Andrew Carlotti @ 2024-08-16 16:50 UTC (permalink / raw)
To: Srinath Parvathaneni; +Cc: binutils, richard.earnshaw, nickc
On Fri, Aug 16, 2024 at 05:38:59PM +0100, Andrew Carlotti wrote:
> On Fri, Jul 12, 2024 at 05:35:30PM +0100, Srinath Parvathaneni wrote:
> > Hi,
> >
> > This patch series adds the support for aarch64 FEAT_SME_F16F16 feature
> > and all the instructions by "+sme-f16f16" flag to -march and the spec
> > can be found here [1].
> >
> > Srinath Parvathaneni (7):
> > aarch64: Add support for FEAT_SME_F16F16 feature.
> > aarch64: Add support for FEAT_SME_F16F16 fmops and fmopa instructions.
> > aarch64: Add support for FEAT_SME_F16F16 fmopa and fmops instructions
> > (regenerated files).
> > aarch64: Add support for FEAT_SME_F16F16 fmla and fmls instructions.
> > aarch64: Add support for FEAT_SME_F16F16 fmla and fmls instructions
> > (regenerated files).
> > aarch64: Add support for FEAT_SME_F16F16 fcvt and fcvtl instructions.
> > aarch64: Add support for FEAT_SME_F16F16 fcvt and fcvtl instructions
> > (regenerated files).
> >
> > Regression testing for aarch64-none-elf target and found no regressions.
> >
> > Ok for binutils-master?
> >
> > [1]: https://developer.arm.com/documentation/ddi0602/2024-06/SME-Instructions?lang=en
> >
> > Regards,
> > Srinath.
>
> There's a couple of test gaps I've mention in reply to patch 4/7, but this
> otherwise looks good to me (though I can't formally approve it).
Actually, you should also add here the whitespace parsing changes that Jan
requested elsewhere, in line with his patch [2] for existing tests.
Specifically, I think this entails adding ` ?` to the vector lists in your
error tests - e.g. `{z0\.h-z3\.h}` -> `{ ?z0\.h-z3\.h ?}`.
[2] https://sourceware.org/pipermail/binutils/2024-July/135649.html
^ permalink raw reply [flat|nested] 12+ messages in thread* Re: [PATCH v1 0/7][Binutils] aarch64: Add support for FEAT_SME_F16F16 feature and instructions.
2024-08-16 16:50 ` Andrew Carlotti
@ 2024-08-19 7:41 ` Jan Beulich
0 siblings, 0 replies; 12+ messages in thread
From: Jan Beulich @ 2024-08-19 7:41 UTC (permalink / raw)
To: Andrew Carlotti, Srinath Parvathaneni; +Cc: binutils, richard.earnshaw, nickc
On 16.08.2024 18:50, Andrew Carlotti wrote:
> On Fri, Aug 16, 2024 at 05:38:59PM +0100, Andrew Carlotti wrote:
>> On Fri, Jul 12, 2024 at 05:35:30PM +0100, Srinath Parvathaneni wrote:
>>> Hi,
>>>
>>> This patch series adds the support for aarch64 FEAT_SME_F16F16 feature
>>> and all the instructions by "+sme-f16f16" flag to -march and the spec
>>> can be found here [1].
>>>
>>> Srinath Parvathaneni (7):
>>> aarch64: Add support for FEAT_SME_F16F16 feature.
>>> aarch64: Add support for FEAT_SME_F16F16 fmops and fmopa instructions.
>>> aarch64: Add support for FEAT_SME_F16F16 fmopa and fmops instructions
>>> (regenerated files).
>>> aarch64: Add support for FEAT_SME_F16F16 fmla and fmls instructions.
>>> aarch64: Add support for FEAT_SME_F16F16 fmla and fmls instructions
>>> (regenerated files).
>>> aarch64: Add support for FEAT_SME_F16F16 fcvt and fcvtl instructions.
>>> aarch64: Add support for FEAT_SME_F16F16 fcvt and fcvtl instructions
>>> (regenerated files).
>>>
>>> Regression testing for aarch64-none-elf target and found no regressions.
>>>
>>> Ok for binutils-master?
>>>
>>> [1]: https://developer.arm.com/documentation/ddi0602/2024-06/SME-Instructions?lang=en
>>>
>>> Regards,
>>> Srinath.
>>
>> There's a couple of test gaps I've mention in reply to patch 4/7, but this
>> otherwise looks good to me (though I can't formally approve it).
>
> Actually, you should also add here the whitespace parsing changes that Jan
> requested elsewhere, in line with his patch [2] for existing tests.
> Specifically, I think this entails adding ` ?` to the vector lists in your
> error tests - e.g. `{z0\.h-z3\.h}` -> `{ ?z0\.h-z3\.h ?}`.
Right. Fundamentally the (not really new) rule is "A single space ought to
be allowed for in all places where the source has any form of whitespace."
Jan
^ permalink raw reply [flat|nested] 12+ messages in thread