* [PATCH] x86: Handle {disp32} for (%bp)/(%ebp)/(%rbp)
@ 2020-07-27 23:23 H.J. Lu
2020-07-28 10:39 ` H.J. Lu
2020-07-28 18:43 ` Jan Beulich
0 siblings, 2 replies; 15+ messages in thread
From: H.J. Lu @ 2020-07-27 23:23 UTC (permalink / raw)
To: binutils
Since (%bp)/(%ebp)/(%rbp) are encoded as 0(%bp)/0(%ebp)/0(%rbp), use
disp32/disp16 on 0(%bp)/0(%ebp)/0(%rbp) for {disp32}.
Note: Since there is no disp32 on 0(%bp), use disp16 instead.
PR gas/26305
* config/tc-i386.c (build_modrm_byte): Use disp32/disp16 on
(%bp)/(%ebp)/(%rbp) for {disp32}.
* testsuite/gas/i386/pseudos.s: Add (%bp)/(%ebp) tests.
* testsuite/gas/i386/x86-64-pseudos.s: Add (%ebp)/(%rbp) tests.
* testsuite/gas/i386/pseudos.d: Updated.
* testsuite/gas/i386/x86-64-pseudos.d: Likewise.
---
gas/config/tc-i386.c | 12 ++++++++++--
gas/testsuite/gas/i386/pseudos.d | 18 ++++++++++++++++++
gas/testsuite/gas/i386/pseudos.s | 24 ++++++++++++++++++++++++
gas/testsuite/gas/i386/x86-64-pseudos.d | 12 ++++++++++++
gas/testsuite/gas/i386/x86-64-pseudos.s | 16 ++++++++++++++++
5 files changed, 80 insertions(+), 2 deletions(-)
diff --git a/gas/config/tc-i386.c b/gas/config/tc-i386.c
index 9ab841383c..11d0e992f9 100644
--- a/gas/config/tc-i386.c
+++ b/gas/config/tc-i386.c
@@ -8151,7 +8151,12 @@ build_modrm_byte (void)
if (operand_type_check (i.types[op], disp) == 0)
{
/* fake (%bp) into 0(%bp) */
- i.types[op].bitfield.disp8 = 1;
+ if (i.disp_encoding == disp_encoding_32bit)
+ /* NB: Use disp16 since there is no disp32
+ in 16-bit mode. */
+ i.types[op].bitfield.disp16 = 1;
+ else
+ i.types[op].bitfield.disp8 = 1;
fake_zero_displacement = 1;
}
}
@@ -8196,7 +8201,10 @@ build_modrm_byte (void)
if (i.base_reg->reg_num == 5 && i.disp_operands == 0)
{
fake_zero_displacement = 1;
- i.types[op].bitfield.disp8 = 1;
+ if (i.disp_encoding == disp_encoding_32bit)
+ i.types[op].bitfield.disp32 = 1;
+ else
+ i.types[op].bitfield.disp8 = 1;
}
i.sib.scale = i.log2_scale_factor;
if (i.index_reg == 0)
diff --git a/gas/testsuite/gas/i386/pseudos.d b/gas/testsuite/gas/i386/pseudos.d
index 00c10a520b..76aae367b4 100644
--- a/gas/testsuite/gas/i386/pseudos.d
+++ b/gas/testsuite/gas/i386/pseudos.d
@@ -288,6 +288,15 @@ Disassembly of section .text:
+[a-f0-9]+: 0f 28 90 80 00 00 00 movaps 0x80\(%eax\),%xmm2
+[a-f0-9]+: 0f 28 90 80 00 00 00 movaps 0x80\(%eax\),%xmm2
+[a-f0-9]+: 0f 28 90 80 00 00 00 movaps 0x80\(%eax\),%xmm2
+ +[a-f0-9]+: 8a 45 00 mov 0x0\(%ebp\),%al
+ +[a-f0-9]+: 8a 45 00 mov 0x0\(%ebp\),%al
+ +[a-f0-9]+: 8a 85 00 00 00 00 mov 0x0\(%ebp\),%al
+ +[a-f0-9]+: 67 8a 07 mov \(%bx\),%al
+ +[a-f0-9]+: 67 8a 07 mov \(%bx\),%al
+ +[a-f0-9]+: 67 8a 07 mov \(%bx\),%al
+ +[a-f0-9]+: 67 8a 46 00 mov 0x0\(%bp\),%al
+ +[a-f0-9]+: 67 8a 46 00 mov 0x0\(%bp\),%al
+ +[a-f0-9]+: 67 8a 86 00 00 mov 0x0\(%bp\),%al
+[a-f0-9]+: c4 e1 78 28 d7 vmovaps %xmm7,%xmm2
+[a-f0-9]+: c4 e1 78 28 d7 vmovaps %xmm7,%xmm2
+[a-f0-9]+: c4 e1 78 29 fa vmovaps %xmm7,%xmm2
@@ -316,4 +325,13 @@ Disassembly of section .text:
+[a-f0-9]+: 0f 28 90 80 00 00 00 movaps 0x80\(%eax\),%xmm2
+[a-f0-9]+: 0f 28 90 80 00 00 00 movaps 0x80\(%eax\),%xmm2
+[a-f0-9]+: 0f 28 90 80 00 00 00 movaps 0x80\(%eax\),%xmm2
+ +[a-f0-9]+: 8a 45 00 mov 0x0\(%ebp\),%al
+ +[a-f0-9]+: 8a 45 00 mov 0x0\(%ebp\),%al
+ +[a-f0-9]+: 8a 85 00 00 00 00 mov 0x0\(%ebp\),%al
+ +[a-f0-9]+: 67 8a 07 mov \(%bx\),%al
+ +[a-f0-9]+: 67 8a 07 mov \(%bx\),%al
+ +[a-f0-9]+: 67 8a 07 mov \(%bx\),%al
+ +[a-f0-9]+: 67 8a 46 00 mov 0x0\(%bp\),%al
+ +[a-f0-9]+: 67 8a 46 00 mov 0x0\(%bp\),%al
+ +[a-f0-9]+: 67 8a 86 00 00 mov 0x0\(%bp\),%al
#pass
diff --git a/gas/testsuite/gas/i386/pseudos.s b/gas/testsuite/gas/i386/pseudos.s
index 19900dd7e5..bc18654ced 100644
--- a/gas/testsuite/gas/i386/pseudos.s
+++ b/gas/testsuite/gas/i386/pseudos.s
@@ -293,6 +293,18 @@ _start:
{disp8} movaps 128(%eax),%xmm2
{disp32} movaps 128(%eax),%xmm2
+ movb (%ebp),%al
+ {disp8} movb (%ebp),%al
+ {disp32} movb (%ebp),%al
+
+ movb (%bx),%al
+ {disp8} movb (%bx),%al
+ {disp32} movb (%bx),%al
+
+ movb (%bp),%al
+ {disp8} movb (%bp),%al
+ {disp32} movb (%bp),%al
+
.intel_syntax noprefix
{vex3} vmovaps xmm2,xmm7
{vex3} {load} vmovaps xmm2,xmm7
@@ -322,3 +334,15 @@ _start:
movaps xmm2,XMMWORD PTR [eax+128]
{disp8} movaps xmm2,XMMWORD PTR [eax+128]
{disp32} movaps xmm2,XMMWORD PTR [eax+128]
+
+ mov al, BYTE PTR [ebp]
+ {disp8} mov al, BYTE PTR [ebp]
+ {disp32} mov al, BYTE PTR [ebp]
+
+ mov al, BYTE PTR [bx]
+ {disp8} mov al, BYTE PTR [bx]
+ {disp32} mov al, BYTE PTR [bx]
+
+ mov al, BYTE PTR [bp]
+ {disp8} mov al, BYTE PTR [bp]
+ {disp32} mov al, BYTE PTR [bp]
diff --git a/gas/testsuite/gas/i386/x86-64-pseudos.d b/gas/testsuite/gas/i386/x86-64-pseudos.d
index d5f4e05711..0fb18a3369 100644
--- a/gas/testsuite/gas/i386/x86-64-pseudos.d
+++ b/gas/testsuite/gas/i386/x86-64-pseudos.d
@@ -315,6 +315,12 @@ Disassembly of section .text:
+[a-f0-9]+: 41 0f 28 10 movaps \(%r8\),%xmm2
+[a-f0-9]+: 40 0f 38 01 01 rex phaddw \(%rcx\),%mm0
+[a-f0-9]+: 41 0f 38 01 00 phaddw \(%r8\),%mm0
+ +[a-f0-9]+: 8a 45 00 mov 0x0\(%rbp\),%al
+ +[a-f0-9]+: 8a 45 00 mov 0x0\(%rbp\),%al
+ +[a-f0-9]+: 8a 85 00 00 00 00 mov 0x0\(%rbp\),%al
+ +[a-f0-9]+: 67 8a 45 00 mov 0x0\(%ebp\),%al
+ +[a-f0-9]+: 67 8a 45 00 mov 0x0\(%ebp\),%al
+ +[a-f0-9]+: 67 8a 85 00 00 00 00 mov 0x0\(%ebp\),%al
+[a-f0-9]+: c4 e1 78 28 d7 vmovaps %xmm7,%xmm2
+[a-f0-9]+: c4 e1 78 28 d7 vmovaps %xmm7,%xmm2
+[a-f0-9]+: c4 e1 78 29 fa vmovaps %xmm7,%xmm2
@@ -353,4 +359,10 @@ Disassembly of section .text:
+[a-f0-9]+: 41 0f 28 10 movaps \(%r8\),%xmm2
+[a-f0-9]+: 40 0f 38 01 01 rex phaddw \(%rcx\),%mm0
+[a-f0-9]+: 41 0f 38 01 00 phaddw \(%r8\),%mm0
+ +[a-f0-9]+: 8a 45 00 mov 0x0\(%rbp\),%al
+ +[a-f0-9]+: 8a 45 00 mov 0x0\(%rbp\),%al
+ +[a-f0-9]+: 8a 85 00 00 00 00 mov 0x0\(%rbp\),%al
+ +[a-f0-9]+: 67 8a 45 00 mov 0x0\(%ebp\),%al
+ +[a-f0-9]+: 67 8a 45 00 mov 0x0\(%ebp\),%al
+ +[a-f0-9]+: 67 8a 85 00 00 00 00 mov 0x0\(%ebp\),%al
#pass
diff --git a/gas/testsuite/gas/i386/x86-64-pseudos.s b/gas/testsuite/gas/i386/x86-64-pseudos.s
index 1bd8818121..3b3638cf75 100644
--- a/gas/testsuite/gas/i386/x86-64-pseudos.s
+++ b/gas/testsuite/gas/i386/x86-64-pseudos.s
@@ -320,6 +320,14 @@ _start:
{rex} phaddw (%rcx),%mm0
{rex} phaddw (%r8),%mm0
+ movb (%rbp),%al
+ {disp8} movb (%rbp),%al
+ {disp32} movb (%rbp),%al
+
+ movb (%ebp),%al
+ {disp8} movb (%ebp),%al
+ {disp32} movb (%ebp),%al
+
.intel_syntax noprefix
{vex3} vmovaps xmm2,xmm7
{vex3} {load} vmovaps xmm2,xmm7
@@ -359,3 +367,11 @@ _start:
{rex} movaps xmm2,XMMWORD PTR [r8]
{rex} phaddw mm0,QWORD PTR [rcx]
{rex} phaddw mm0,QWORD PTR [r8]
+
+ mov al, BYTE PTR [rbp]
+ {disp8} mov al, BYTE PTR [rbp]
+ {disp32} mov al, BYTE PTR [rbp]
+
+ mov al, BYTE PTR [ebp]
+ {disp8} mov al, BYTE PTR [ebp]
+ {disp32} mov al, BYTE PTR [ebp]
--
2.26.2
^ permalink raw reply [flat|nested] 15+ messages in thread* Re: [PATCH] x86: Handle {disp32} for (%bp)/(%ebp)/(%rbp) 2020-07-27 23:23 [PATCH] x86: Handle {disp32} for (%bp)/(%ebp)/(%rbp) H.J. Lu @ 2020-07-28 10:39 ` H.J. Lu 2020-07-28 18:43 ` Jan Beulich 1 sibling, 0 replies; 15+ messages in thread From: H.J. Lu @ 2020-07-28 10:39 UTC (permalink / raw) To: Binutils [-- Attachment #1: Type: text/plain, Size: 723 bytes --] On Mon, Jul 27, 2020 at 4:23 PM H.J. Lu <hjl.tools@gmail.com> wrote: > > Since (%bp)/(%ebp)/(%rbp) are encoded as 0(%bp)/0(%ebp)/0(%rbp), use > disp32/disp16 on 0(%bp)/0(%ebp)/0(%rbp) for {disp32}. > > Note: Since there is no disp32 on 0(%bp), use disp16 instead. > > PR gas/26305 > * config/tc-i386.c (build_modrm_byte): Use disp32/disp16 on > (%bp)/(%ebp)/(%rbp) for {disp32}. > * testsuite/gas/i386/pseudos.s: Add (%bp)/(%ebp) tests. > * testsuite/gas/i386/x86-64-pseudos.s: Add (%ebp)/(%rbp) tests. > * testsuite/gas/i386/pseudos.d: Updated. > * testsuite/gas/i386/x86-64-pseudos.d: Likewise. I am checking in this and will backport it to 2.35 branch. -- H.J. [-- Attachment #2: 0001-x86-Handle-disp32-for-bp-ebp-rbp.patch --] [-- Type: text/x-patch, Size: 7995 bytes --] From 9b31794493e5b8768d9df9700535f42e1e092438 Mon Sep 17 00:00:00 2001 From: "H.J. Lu" <hjl.tools@gmail.com> Date: Mon, 27 Jul 2020 16:02:54 -0700 Subject: [PATCH] x86: Handle {disp32} for (%bp)/(%ebp)/(%rbp) Since (%bp)/(%ebp)/(%rbp) are encoded as 0(%bp)/0(%ebp)/0(%rbp), use disp32/disp16 on 0(%bp)/0(%ebp)/0(%rbp) for {disp32}. Note: Since there is no disp32 on 0(%bp), use disp16 instead. PR gas/26305 * config/tc-i386.c (build_modrm_byte): Use disp32/disp16 on (%bp)/(%ebp)/(%rbp) for {disp32}. * doc/c-i386.texi: Update {disp32} documentation. * testsuite/gas/i386/pseudos.s: Add (%bp)/(%ebp) tests. * testsuite/gas/i386/x86-64-pseudos.s: Add (%ebp)/(%rbp) tests. * testsuite/gas/i386/pseudos.d: Updated. * testsuite/gas/i386/x86-64-pseudos.d: Likewise. --- gas/config/tc-i386.c | 12 ++++++++++-- gas/doc/c-i386.texi | 2 +- gas/testsuite/gas/i386/pseudos.d | 18 ++++++++++++++++++ gas/testsuite/gas/i386/pseudos.s | 24 ++++++++++++++++++++++++ gas/testsuite/gas/i386/x86-64-pseudos.d | 12 ++++++++++++ gas/testsuite/gas/i386/x86-64-pseudos.s | 16 ++++++++++++++++ 6 files changed, 81 insertions(+), 3 deletions(-) diff --git a/gas/config/tc-i386.c b/gas/config/tc-i386.c index 9ab841383c..11d0e992f9 100644 --- a/gas/config/tc-i386.c +++ b/gas/config/tc-i386.c @@ -8151,7 +8151,12 @@ build_modrm_byte (void) if (operand_type_check (i.types[op], disp) == 0) { /* fake (%bp) into 0(%bp) */ - i.types[op].bitfield.disp8 = 1; + if (i.disp_encoding == disp_encoding_32bit) + /* NB: Use disp16 since there is no disp32 + in 16-bit mode. */ + i.types[op].bitfield.disp16 = 1; + else + i.types[op].bitfield.disp8 = 1; fake_zero_displacement = 1; } } @@ -8196,7 +8201,10 @@ build_modrm_byte (void) if (i.base_reg->reg_num == 5 && i.disp_operands == 0) { fake_zero_displacement = 1; - i.types[op].bitfield.disp8 = 1; + if (i.disp_encoding == disp_encoding_32bit) + i.types[op].bitfield.disp32 = 1; + else + i.types[op].bitfield.disp8 = 1; } i.sib.scale = i.log2_scale_factor; if (i.index_reg == 0) diff --git a/gas/doc/c-i386.texi b/gas/doc/c-i386.texi index 3813f5eb59..8be708e745 100644 --- a/gas/doc/c-i386.texi +++ b/gas/doc/c-i386.texi @@ -822,7 +822,7 @@ Different encoding options can be specified via pseudo prefixes: @samp{@{disp8@}} -- prefer 8-bit displacement. @item -@samp{@{disp32@}} -- prefer 32-bit displacement. +@samp{@{disp32@}} -- prefer 32-bit (16-bit in 16-bit mode) displacement. @item @samp{@{load@}} -- prefer load-form instruction. diff --git a/gas/testsuite/gas/i386/pseudos.d b/gas/testsuite/gas/i386/pseudos.d index 00c10a520b..76aae367b4 100644 --- a/gas/testsuite/gas/i386/pseudos.d +++ b/gas/testsuite/gas/i386/pseudos.d @@ -288,6 +288,15 @@ Disassembly of section .text: +[a-f0-9]+: 0f 28 90 80 00 00 00 movaps 0x80\(%eax\),%xmm2 +[a-f0-9]+: 0f 28 90 80 00 00 00 movaps 0x80\(%eax\),%xmm2 +[a-f0-9]+: 0f 28 90 80 00 00 00 movaps 0x80\(%eax\),%xmm2 + +[a-f0-9]+: 8a 45 00 mov 0x0\(%ebp\),%al + +[a-f0-9]+: 8a 45 00 mov 0x0\(%ebp\),%al + +[a-f0-9]+: 8a 85 00 00 00 00 mov 0x0\(%ebp\),%al + +[a-f0-9]+: 67 8a 07 mov \(%bx\),%al + +[a-f0-9]+: 67 8a 07 mov \(%bx\),%al + +[a-f0-9]+: 67 8a 07 mov \(%bx\),%al + +[a-f0-9]+: 67 8a 46 00 mov 0x0\(%bp\),%al + +[a-f0-9]+: 67 8a 46 00 mov 0x0\(%bp\),%al + +[a-f0-9]+: 67 8a 86 00 00 mov 0x0\(%bp\),%al +[a-f0-9]+: c4 e1 78 28 d7 vmovaps %xmm7,%xmm2 +[a-f0-9]+: c4 e1 78 28 d7 vmovaps %xmm7,%xmm2 +[a-f0-9]+: c4 e1 78 29 fa vmovaps %xmm7,%xmm2 @@ -316,4 +325,13 @@ Disassembly of section .text: +[a-f0-9]+: 0f 28 90 80 00 00 00 movaps 0x80\(%eax\),%xmm2 +[a-f0-9]+: 0f 28 90 80 00 00 00 movaps 0x80\(%eax\),%xmm2 +[a-f0-9]+: 0f 28 90 80 00 00 00 movaps 0x80\(%eax\),%xmm2 + +[a-f0-9]+: 8a 45 00 mov 0x0\(%ebp\),%al + +[a-f0-9]+: 8a 45 00 mov 0x0\(%ebp\),%al + +[a-f0-9]+: 8a 85 00 00 00 00 mov 0x0\(%ebp\),%al + +[a-f0-9]+: 67 8a 07 mov \(%bx\),%al + +[a-f0-9]+: 67 8a 07 mov \(%bx\),%al + +[a-f0-9]+: 67 8a 07 mov \(%bx\),%al + +[a-f0-9]+: 67 8a 46 00 mov 0x0\(%bp\),%al + +[a-f0-9]+: 67 8a 46 00 mov 0x0\(%bp\),%al + +[a-f0-9]+: 67 8a 86 00 00 mov 0x0\(%bp\),%al #pass diff --git a/gas/testsuite/gas/i386/pseudos.s b/gas/testsuite/gas/i386/pseudos.s index 19900dd7e5..bc18654ced 100644 --- a/gas/testsuite/gas/i386/pseudos.s +++ b/gas/testsuite/gas/i386/pseudos.s @@ -293,6 +293,18 @@ _start: {disp8} movaps 128(%eax),%xmm2 {disp32} movaps 128(%eax),%xmm2 + movb (%ebp),%al + {disp8} movb (%ebp),%al + {disp32} movb (%ebp),%al + + movb (%bx),%al + {disp8} movb (%bx),%al + {disp32} movb (%bx),%al + + movb (%bp),%al + {disp8} movb (%bp),%al + {disp32} movb (%bp),%al + .intel_syntax noprefix {vex3} vmovaps xmm2,xmm7 {vex3} {load} vmovaps xmm2,xmm7 @@ -322,3 +334,15 @@ _start: movaps xmm2,XMMWORD PTR [eax+128] {disp8} movaps xmm2,XMMWORD PTR [eax+128] {disp32} movaps xmm2,XMMWORD PTR [eax+128] + + mov al, BYTE PTR [ebp] + {disp8} mov al, BYTE PTR [ebp] + {disp32} mov al, BYTE PTR [ebp] + + mov al, BYTE PTR [bx] + {disp8} mov al, BYTE PTR [bx] + {disp32} mov al, BYTE PTR [bx] + + mov al, BYTE PTR [bp] + {disp8} mov al, BYTE PTR [bp] + {disp32} mov al, BYTE PTR [bp] diff --git a/gas/testsuite/gas/i386/x86-64-pseudos.d b/gas/testsuite/gas/i386/x86-64-pseudos.d index d5f4e05711..0fb18a3369 100644 --- a/gas/testsuite/gas/i386/x86-64-pseudos.d +++ b/gas/testsuite/gas/i386/x86-64-pseudos.d @@ -315,6 +315,12 @@ Disassembly of section .text: +[a-f0-9]+: 41 0f 28 10 movaps \(%r8\),%xmm2 +[a-f0-9]+: 40 0f 38 01 01 rex phaddw \(%rcx\),%mm0 +[a-f0-9]+: 41 0f 38 01 00 phaddw \(%r8\),%mm0 + +[a-f0-9]+: 8a 45 00 mov 0x0\(%rbp\),%al + +[a-f0-9]+: 8a 45 00 mov 0x0\(%rbp\),%al + +[a-f0-9]+: 8a 85 00 00 00 00 mov 0x0\(%rbp\),%al + +[a-f0-9]+: 67 8a 45 00 mov 0x0\(%ebp\),%al + +[a-f0-9]+: 67 8a 45 00 mov 0x0\(%ebp\),%al + +[a-f0-9]+: 67 8a 85 00 00 00 00 mov 0x0\(%ebp\),%al +[a-f0-9]+: c4 e1 78 28 d7 vmovaps %xmm7,%xmm2 +[a-f0-9]+: c4 e1 78 28 d7 vmovaps %xmm7,%xmm2 +[a-f0-9]+: c4 e1 78 29 fa vmovaps %xmm7,%xmm2 @@ -353,4 +359,10 @@ Disassembly of section .text: +[a-f0-9]+: 41 0f 28 10 movaps \(%r8\),%xmm2 +[a-f0-9]+: 40 0f 38 01 01 rex phaddw \(%rcx\),%mm0 +[a-f0-9]+: 41 0f 38 01 00 phaddw \(%r8\),%mm0 + +[a-f0-9]+: 8a 45 00 mov 0x0\(%rbp\),%al + +[a-f0-9]+: 8a 45 00 mov 0x0\(%rbp\),%al + +[a-f0-9]+: 8a 85 00 00 00 00 mov 0x0\(%rbp\),%al + +[a-f0-9]+: 67 8a 45 00 mov 0x0\(%ebp\),%al + +[a-f0-9]+: 67 8a 45 00 mov 0x0\(%ebp\),%al + +[a-f0-9]+: 67 8a 85 00 00 00 00 mov 0x0\(%ebp\),%al #pass diff --git a/gas/testsuite/gas/i386/x86-64-pseudos.s b/gas/testsuite/gas/i386/x86-64-pseudos.s index 1bd8818121..3b3638cf75 100644 --- a/gas/testsuite/gas/i386/x86-64-pseudos.s +++ b/gas/testsuite/gas/i386/x86-64-pseudos.s @@ -320,6 +320,14 @@ _start: {rex} phaddw (%rcx),%mm0 {rex} phaddw (%r8),%mm0 + movb (%rbp),%al + {disp8} movb (%rbp),%al + {disp32} movb (%rbp),%al + + movb (%ebp),%al + {disp8} movb (%ebp),%al + {disp32} movb (%ebp),%al + .intel_syntax noprefix {vex3} vmovaps xmm2,xmm7 {vex3} {load} vmovaps xmm2,xmm7 @@ -359,3 +367,11 @@ _start: {rex} movaps xmm2,XMMWORD PTR [r8] {rex} phaddw mm0,QWORD PTR [rcx] {rex} phaddw mm0,QWORD PTR [r8] + + mov al, BYTE PTR [rbp] + {disp8} mov al, BYTE PTR [rbp] + {disp32} mov al, BYTE PTR [rbp] + + mov al, BYTE PTR [ebp] + {disp8} mov al, BYTE PTR [ebp] + {disp32} mov al, BYTE PTR [ebp] -- 2.26.2 ^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH] x86: Handle {disp32} for (%bp)/(%ebp)/(%rbp) 2020-07-27 23:23 [PATCH] x86: Handle {disp32} for (%bp)/(%ebp)/(%rbp) H.J. Lu 2020-07-28 10:39 ` H.J. Lu @ 2020-07-28 18:43 ` Jan Beulich 2020-07-28 19:02 ` H.J. Lu 1 sibling, 1 reply; 15+ messages in thread From: Jan Beulich @ 2020-07-28 18:43 UTC (permalink / raw) To: H.J. Lu; +Cc: binutils On 28.07.2020 01:23, H.J. Lu via Binutils wrote: > Since (%bp)/(%ebp)/(%rbp) are encoded as 0(%bp)/0(%ebp)/0(%rbp), use > disp32/disp16 on 0(%bp)/0(%ebp)/0(%rbp) for {disp32}. Same for (%r13d) / (%r13) afaict? > Note: Since there is no disp32 on 0(%bp), use disp16 instead. What use is it to fix the special case of (%bp) when the more general case ((%bx), (%si), etc) doesn't work? I anyway think that instead of ... > --- a/gas/config/tc-i386.c > +++ b/gas/config/tc-i386.c > @@ -8151,7 +8151,12 @@ build_modrm_byte (void) > if (operand_type_check (i.types[op], disp) == 0) > { > /* fake (%bp) into 0(%bp) */ > - i.types[op].bitfield.disp8 = 1; > + if (i.disp_encoding == disp_encoding_32bit) > + /* NB: Use disp16 since there is no disp32 > + in 16-bit mode. */ > + i.types[op].bitfield.disp16 = 1; > + else > + i.types[op].bitfield.disp8 = 1; > fake_zero_displacement = 1; > } ... the comment you add here, support for {disp16} should be added. Jan ^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH] x86: Handle {disp32} for (%bp)/(%ebp)/(%rbp) 2020-07-28 18:43 ` Jan Beulich @ 2020-07-28 19:02 ` H.J. Lu 2020-07-28 20:30 ` [PATCH] x86: Add {disp16} pseudo prefix H.J. Lu 0 siblings, 1 reply; 15+ messages in thread From: H.J. Lu @ 2020-07-28 19:02 UTC (permalink / raw) To: Jan Beulich; +Cc: Binutils On Tue, Jul 28, 2020 at 11:43 AM Jan Beulich <jbeulich@suse.com> wrote: > > On 28.07.2020 01:23, H.J. Lu via Binutils wrote: > > Since (%bp)/(%ebp)/(%rbp) are encoded as 0(%bp)/0(%ebp)/0(%rbp), use > > disp32/disp16 on 0(%bp)/0(%ebp)/0(%rbp) for {disp32}. > > Same for (%r13d) / (%r13) afaict? Yes. {disp32} works on (%r13d) / (%r13) now: [hjl@gnu-cfl-2 testsuite]$ cat x.s movb (%r13),%al {disp8} movb (%r13),%al {disp32} movb (%r13),%al movb (%r13d),%al {disp8} movb (%r13d),%al {disp32} movb (%r13d),%al [hjl@gnu-cfl-2 testsuite]$ gcc -c x.s [hjl@gnu-cfl-2 testsuite]$ objdump -dw x.o x.o: file format elf64-x86-64 Disassembly of section .text: 0000000000000000 <.text>: 0: 41 8a 45 00 mov 0x0(%r13),%al 4: 41 8a 45 00 mov 0x0(%r13),%al 8: 41 8a 45 00 mov 0x0(%r13),%al c: 67 41 8a 45 00 mov 0x0(%r13d),%al 11: 67 41 8a 45 00 mov 0x0(%r13d),%al 16: 67 41 8a 45 00 mov 0x0(%r13d),%al [hjl@gnu-cfl-2 testsuite]$ ../as-new -o x.o x.s [hjl@gnu-cfl-2 testsuite]$ objdump -dw x.o x.o: file format elf64-x86-64 Disassembly of section .text: 0000000000000000 <.text>: 0: 41 8a 45 00 mov 0x0(%r13),%al 4: 41 8a 45 00 mov 0x0(%r13),%al 8: 41 8a 85 00 00 00 00 mov 0x0(%r13),%al f: 67 41 8a 45 00 mov 0x0(%r13d),%al 14: 67 41 8a 45 00 mov 0x0(%r13d),%al 19: 67 41 8a 85 00 00 00 00 mov 0x0(%r13d),%al [hjl@gnu-cfl-2 testsuite]$ > > Note: Since there is no disp32 on 0(%bp), use disp16 instead. > > What use is it to fix the special case of (%bp) when the more general > case ((%bx), (%si), etc) doesn't work? I anyway think that instead of > ... > > > --- a/gas/config/tc-i386.c > > +++ b/gas/config/tc-i386.c > > @@ -8151,7 +8151,12 @@ build_modrm_byte (void) > > if (operand_type_check (i.types[op], disp) == 0) > > { > > /* fake (%bp) into 0(%bp) */ > > - i.types[op].bitfield.disp8 = 1; > > + if (i.disp_encoding == disp_encoding_32bit) > > + /* NB: Use disp16 since there is no disp32 > > + in 16-bit mode. */ > > + i.types[op].bitfield.disp16 = 1; > > + else > > + i.types[op].bitfield.disp8 = 1; > > fake_zero_displacement = 1; > > } > > ... the comment you add here, support for {disp16} should be added. > I will add {disp16} to master branch. -- H.J. ^ permalink raw reply [flat|nested] 15+ messages in thread
* [PATCH] x86: Add {disp16} pseudo prefix 2020-07-28 19:02 ` H.J. Lu @ 2020-07-28 20:30 ` H.J. Lu 2020-07-29 20:26 ` Jan Beulich 0 siblings, 1 reply; 15+ messages in thread From: H.J. Lu @ 2020-07-28 20:30 UTC (permalink / raw) To: Jan Beulich; +Cc: Binutils [-- Attachment #1: Type: text/plain, Size: 3027 bytes --] On Tue, Jul 28, 2020 at 12:02 PM H.J. Lu <hjl.tools@gmail.com> wrote: > > On Tue, Jul 28, 2020 at 11:43 AM Jan Beulich <jbeulich@suse.com> wrote: > > > > On 28.07.2020 01:23, H.J. Lu via Binutils wrote: > > > Since (%bp)/(%ebp)/(%rbp) are encoded as 0(%bp)/0(%ebp)/0(%rbp), use > > > disp32/disp16 on 0(%bp)/0(%ebp)/0(%rbp) for {disp32}. > > > > Same for (%r13d) / (%r13) afaict? > > Yes. {disp32} works on (%r13d) / (%r13) now: > > [hjl@gnu-cfl-2 testsuite]$ cat x.s > movb (%r13),%al > {disp8} movb (%r13),%al > {disp32} movb (%r13),%al > > movb (%r13d),%al > {disp8} movb (%r13d),%al > {disp32} movb (%r13d),%al > [hjl@gnu-cfl-2 testsuite]$ gcc -c x.s > [hjl@gnu-cfl-2 testsuite]$ objdump -dw x.o > > x.o: file format elf64-x86-64 > > > Disassembly of section .text: > > 0000000000000000 <.text>: > 0: 41 8a 45 00 mov 0x0(%r13),%al > 4: 41 8a 45 00 mov 0x0(%r13),%al > 8: 41 8a 45 00 mov 0x0(%r13),%al > c: 67 41 8a 45 00 mov 0x0(%r13d),%al > 11: 67 41 8a 45 00 mov 0x0(%r13d),%al > 16: 67 41 8a 45 00 mov 0x0(%r13d),%al > [hjl@gnu-cfl-2 testsuite]$ ../as-new -o x.o x.s > [hjl@gnu-cfl-2 testsuite]$ objdump -dw x.o > > x.o: file format elf64-x86-64 > > > Disassembly of section .text: > > 0000000000000000 <.text>: > 0: 41 8a 45 00 mov 0x0(%r13),%al > 4: 41 8a 45 00 mov 0x0(%r13),%al > 8: 41 8a 85 00 00 00 00 mov 0x0(%r13),%al > f: 67 41 8a 45 00 mov 0x0(%r13d),%al > 14: 67 41 8a 45 00 mov 0x0(%r13d),%al > 19: 67 41 8a 85 00 00 00 00 mov 0x0(%r13d),%al > [hjl@gnu-cfl-2 testsuite]$ > > > > > Note: Since there is no disp32 on 0(%bp), use disp16 instead. > > > > What use is it to fix the special case of (%bp) when the more general > > case ((%bx), (%si), etc) doesn't work? I anyway think that instead of > > ... > > > > > --- a/gas/config/tc-i386.c > > > +++ b/gas/config/tc-i386.c > > > @@ -8151,7 +8151,12 @@ build_modrm_byte (void) > > > if (operand_type_check (i.types[op], disp) == 0) > > > { > > > /* fake (%bp) into 0(%bp) */ > > > - i.types[op].bitfield.disp8 = 1; > > > + if (i.disp_encoding == disp_encoding_32bit) > > > + /* NB: Use disp16 since there is no disp32 > > > + in 16-bit mode. */ > > > + i.types[op].bitfield.disp16 = 1; > > > + else > > > + i.types[op].bitfield.disp8 = 1; > > > fake_zero_displacement = 1; > > > } > > > > ... the comment you add here, support for {disp16} should be added. > > > > I will add {disp16} to master branch. > Add {disp16} pseudo prefix and replace {disp32} pseudo prefix with {disp16} in 16-bit mode test. Check invalid {disp16}/{disp32} pseudo prefixes. Note: {disp16} can be also used on branches in 32-bit mode. -- H.J. [-- Attachment #2: 0001-x86-Add-disp16-pseudo-prefix.patch --] [-- Type: text/x-patch, Size: 13695 bytes --] From caa5adabc759b3c45cceb2170ce2c0ebb44a32de Mon Sep 17 00:00:00 2001 From: "H.J. Lu" <hjl.tools@gmail.com> Date: Tue, 28 Jul 2020 13:19:17 -0700 Subject: [PATCH] x86: Add {disp16} pseudo prefix Add {disp16} pseudo prefix and replace {disp32} pseudo prefix with {disp16} in 16-bit mode test. Check invalid {disp16}/{disp32} pseudo prefixes. Note: {disp16} can be also used on branches in 32-bit mode. gas/ PR gas/26305 * config/tc-i386.c (_i386_insn::disp_encoding): Add disp_encoding_16bit. (parse_insn): Handle {disp16}. (build_modrm_byte): Handle {disp16}. (i386_index_check): Check invalid {disp16} and {disp32} pseudo prefixes. * doc/c-i386.texi: Update {disp32} documentation and document {disp16}. * testsuite/gas/i386/inval-pseudo.s: Add {disp32}/{disp16} tests. * testsuite/gas/i386/pseudos.s: Add {disp16} tests. * testsuite/gas/i386/x86-64-pseudos.s: Add (%r13)/(%r13d) tests. * testsuite/gas/i386/inval-pseudo.l: Updated. * testsuite/gas/i386/pseudos.d: Likewise. * testsuite/gas/i386/x86-64-pseudos.d: Likewise. opcodes/ PR gas/26305 * i386-opc.tbl: Add {disp16}. * i386-tbl.h: Regenerated. --- gas/config/tc-i386.c | 32 +++++++++++++++++++++---- gas/doc/c-i386.texi | 5 +++- gas/testsuite/gas/i386/inval-pseudo.l | 11 ++++++++- gas/testsuite/gas/i386/inval-pseudo.s | 5 ++++ gas/testsuite/gas/i386/pseudos.d | 20 ++++++++++++---- gas/testsuite/gas/i386/pseudos.s | 24 +++++++++++++++---- gas/testsuite/gas/i386/x86-64-pseudos.d | 12 ++++++++++ gas/testsuite/gas/i386/x86-64-pseudos.s | 16 +++++++++++++ opcodes/i386-opc.tbl | 1 + opcodes/i386-tbl.h | 12 ++++++++++ 10 files changed, 124 insertions(+), 14 deletions(-) diff --git a/gas/config/tc-i386.c b/gas/config/tc-i386.c index 11d0e992f9..9e96656e95 100644 --- a/gas/config/tc-i386.c +++ b/gas/config/tc-i386.c @@ -409,11 +409,12 @@ struct _i386_insn dir_encoding_swap } dir_encoding; - /* Prefer 8bit or 32bit displacement in encoding. */ + /* Prefer 8bit, 16bit, 32bit displacement in encoding. */ enum { disp_encoding_default = 0, disp_encoding_8bit, + disp_encoding_16bit, disp_encoding_32bit } disp_encoding; @@ -5155,6 +5156,10 @@ parse_insn (char *line, char *mnemonic) /* {nooptimize} */ i.no_optimize = TRUE; break; + case 0x9: + /* {disp16} */ + i.disp_encoding = disp_encoding_16bit; + break; default: abort (); } @@ -8151,9 +8156,7 @@ build_modrm_byte (void) if (operand_type_check (i.types[op], disp) == 0) { /* fake (%bp) into 0(%bp) */ - if (i.disp_encoding == disp_encoding_32bit) - /* NB: Use disp16 since there is no disp32 - in 16-bit mode. */ + if (i.disp_encoding == disp_encoding_16bit) i.types[op].bitfield.disp16 = 1; else i.types[op].bitfield.disp8 = 1; @@ -8166,6 +8169,16 @@ build_modrm_byte (void) default: /* (%si) -> 4 or (%di) -> 5 */ i.rm.regmem = i.base_reg->reg_num - 6 + 4; } + if (!fake_zero_displacement + && !i.disp_operands + && i.disp_encoding) + { + fake_zero_displacement = 1; + if (i.disp_encoding == disp_encoding_8bit) + i.types[op].bitfield.disp8 = 1; + else + i.types[op].bitfield.disp16 = 1; + } i.rm.mode = mode_from_disp_size (i.types[op]); } else /* i.base_reg and 32/64 bit mode */ @@ -11012,6 +11025,14 @@ i386_index_check (const char *operand_string) if (addr_mode != CODE_16BIT) { /* 32-bit/64-bit checks. */ + if (i.disp_encoding == disp_encoding_16bit) + { + bad_disp: + as_bad (_("invalid `%s' prefix"), + addr_mode == CODE_16BIT ? "{disp32}" : "{disp16}"); + return 0; + } + if ((i.base_reg && ((addr_mode == CODE_64BIT ? !i.base_reg->reg_type.bitfield.qword @@ -11049,6 +11070,9 @@ i386_index_check (const char *operand_string) else { /* 16-bit checks. */ + if (i.disp_encoding == disp_encoding_32bit) + goto bad_disp; + if ((i.base_reg && (!i.base_reg->reg_type.bitfield.word || !i.base_reg->reg_type.bitfield.baseindex)) diff --git a/gas/doc/c-i386.texi b/gas/doc/c-i386.texi index 8be708e745..64a563aacb 100644 --- a/gas/doc/c-i386.texi +++ b/gas/doc/c-i386.texi @@ -822,7 +822,10 @@ Different encoding options can be specified via pseudo prefixes: @samp{@{disp8@}} -- prefer 8-bit displacement. @item -@samp{@{disp32@}} -- prefer 32-bit (16-bit in 16-bit mode) displacement. +@samp{@{disp32@}} -- prefer 32-bit displacement. + +@item +@samp{@{disp16@}} -- prefer 16-bit displacement. @item @samp{@{load@}} -- prefer load-form instruction. diff --git a/gas/testsuite/gas/i386/inval-pseudo.l b/gas/testsuite/gas/i386/inval-pseudo.l index cf344f6986..dbffa301a8 100644 --- a/gas/testsuite/gas/i386/inval-pseudo.l +++ b/gas/testsuite/gas/i386/inval-pseudo.l @@ -1,5 +1,9 @@ .*: Assembler messages: .*:3: Error: .* +.*:5: Error: .* +.*:6: Error: .* +.*:8: Error: .* +.*:9: Error: .* GAS LISTING .* @@ -7,5 +11,10 @@ GAS LISTING .* [ ]*2[ ]+\?\?\?\? 90 nop [ ]*3[ ]+\{disp32\} [ ]*4[ ]+\?\?\?\? 90 nop -[ ]*5[ ]+\?\?\?\? 00000000 \.p2align 4,0 +[ ]*5[ ]+\{disp32\} movb \(%bp\),%al +[ ]*6[ ]+\{disp16\} movb \(%ebp\),%al +[ ]*7[ ]+\.code64 +[ ]*8[ ]+\{disp16\} movb \(%ebp\),%al +[ ]*9[ ]+\{disp16\} movb \(%rbp\),%al +[ ]*10[ ]+\?\?\?\? 00000000 \.p2align 4,0 #... diff --git a/gas/testsuite/gas/i386/inval-pseudo.s b/gas/testsuite/gas/i386/inval-pseudo.s index a40362b8f9..2c4b3c3766 100644 --- a/gas/testsuite/gas/i386/inval-pseudo.s +++ b/gas/testsuite/gas/i386/inval-pseudo.s @@ -2,4 +2,9 @@ nop {disp32} nop + {disp32} movb (%bp),%al + {disp16} movb (%ebp),%al + .code64 + {disp16} movb (%ebp),%al + {disp16} movb (%rbp),%al .p2align 4,0 diff --git a/gas/testsuite/gas/i386/pseudos.d b/gas/testsuite/gas/i386/pseudos.d index 76aae367b4..4457f3642d 100644 --- a/gas/testsuite/gas/i386/pseudos.d +++ b/gas/testsuite/gas/i386/pseudos.d @@ -291,9 +291,15 @@ Disassembly of section .text: +[a-f0-9]+: 8a 45 00 mov 0x0\(%ebp\),%al +[a-f0-9]+: 8a 45 00 mov 0x0\(%ebp\),%al +[a-f0-9]+: 8a 85 00 00 00 00 mov 0x0\(%ebp\),%al + +[a-f0-9]+: 67 8a 04 mov \(%si\),%al + +[a-f0-9]+: 67 8a 44 00 mov 0x0\(%si\),%al + +[a-f0-9]+: 67 8a 84 00 00 mov 0x0\(%si\),%al + +[a-f0-9]+: 67 8a 05 mov \(%di\),%al + +[a-f0-9]+: 67 8a 45 00 mov 0x0\(%di\),%al + +[a-f0-9]+: 67 8a 85 00 00 mov 0x0\(%di\),%al +[a-f0-9]+: 67 8a 07 mov \(%bx\),%al - +[a-f0-9]+: 67 8a 07 mov \(%bx\),%al - +[a-f0-9]+: 67 8a 07 mov \(%bx\),%al + +[a-f0-9]+: 67 8a 47 00 mov 0x0\(%bx\),%al + +[a-f0-9]+: 67 8a 87 00 00 mov 0x0\(%bx\),%al +[a-f0-9]+: 67 8a 46 00 mov 0x0\(%bp\),%al +[a-f0-9]+: 67 8a 46 00 mov 0x0\(%bp\),%al +[a-f0-9]+: 67 8a 86 00 00 mov 0x0\(%bp\),%al @@ -328,9 +334,15 @@ Disassembly of section .text: +[a-f0-9]+: 8a 45 00 mov 0x0\(%ebp\),%al +[a-f0-9]+: 8a 45 00 mov 0x0\(%ebp\),%al +[a-f0-9]+: 8a 85 00 00 00 00 mov 0x0\(%ebp\),%al + +[a-f0-9]+: 67 8a 04 mov \(%si\),%al + +[a-f0-9]+: 67 8a 44 00 mov 0x0\(%si\),%al + +[a-f0-9]+: 67 8a 84 00 00 mov 0x0\(%si\),%al + +[a-f0-9]+: 67 8a 05 mov \(%di\),%al + +[a-f0-9]+: 67 8a 45 00 mov 0x0\(%di\),%al + +[a-f0-9]+: 67 8a 85 00 00 mov 0x0\(%di\),%al +[a-f0-9]+: 67 8a 07 mov \(%bx\),%al - +[a-f0-9]+: 67 8a 07 mov \(%bx\),%al - +[a-f0-9]+: 67 8a 07 mov \(%bx\),%al + +[a-f0-9]+: 67 8a 47 00 mov 0x0\(%bx\),%al + +[a-f0-9]+: 67 8a 87 00 00 mov 0x0\(%bx\),%al +[a-f0-9]+: 67 8a 46 00 mov 0x0\(%bp\),%al +[a-f0-9]+: 67 8a 46 00 mov 0x0\(%bp\),%al +[a-f0-9]+: 67 8a 86 00 00 mov 0x0\(%bp\),%al diff --git a/gas/testsuite/gas/i386/pseudos.s b/gas/testsuite/gas/i386/pseudos.s index bc18654ced..3fd2da16bd 100644 --- a/gas/testsuite/gas/i386/pseudos.s +++ b/gas/testsuite/gas/i386/pseudos.s @@ -297,13 +297,21 @@ _start: {disp8} movb (%ebp),%al {disp32} movb (%ebp),%al + movb (%si),%al + {disp8} movb (%si),%al + {disp16} movb (%si),%al + + movb (%di),%al + {disp8} movb (%di),%al + {disp16} movb (%di),%al + movb (%bx),%al {disp8} movb (%bx),%al - {disp32} movb (%bx),%al + {disp16} movb (%bx),%al movb (%bp),%al {disp8} movb (%bp),%al - {disp32} movb (%bp),%al + {disp16} movb (%bp),%al .intel_syntax noprefix {vex3} vmovaps xmm2,xmm7 @@ -339,10 +347,18 @@ _start: {disp8} mov al, BYTE PTR [ebp] {disp32} mov al, BYTE PTR [ebp] + mov al, BYTE PTR [si] + {disp8} mov al, BYTE PTR [si] + {disp16} mov al, BYTE PTR [si] + + mov al, BYTE PTR [di] + {disp8} mov al, BYTE PTR [di] + {disp16} mov al, BYTE PTR [di] + mov al, BYTE PTR [bx] {disp8} mov al, BYTE PTR [bx] - {disp32} mov al, BYTE PTR [bx] + {disp16} mov al, BYTE PTR [bx] mov al, BYTE PTR [bp] {disp8} mov al, BYTE PTR [bp] - {disp32} mov al, BYTE PTR [bp] + {disp16} mov al, BYTE PTR [bp] diff --git a/gas/testsuite/gas/i386/x86-64-pseudos.d b/gas/testsuite/gas/i386/x86-64-pseudos.d index 0fb18a3369..55a12b9261 100644 --- a/gas/testsuite/gas/i386/x86-64-pseudos.d +++ b/gas/testsuite/gas/i386/x86-64-pseudos.d @@ -321,6 +321,12 @@ Disassembly of section .text: +[a-f0-9]+: 67 8a 45 00 mov 0x0\(%ebp\),%al +[a-f0-9]+: 67 8a 45 00 mov 0x0\(%ebp\),%al +[a-f0-9]+: 67 8a 85 00 00 00 00 mov 0x0\(%ebp\),%al + +[a-f0-9]+: 41 8a 45 00 mov 0x0\(%r13\),%al + +[a-f0-9]+: 41 8a 45 00 mov 0x0\(%r13\),%al + +[a-f0-9]+: 41 8a 85 00 00 00 00 mov 0x0\(%r13\),%al + +[a-f0-9]+: 67 41 8a 45 00 mov 0x0\(%r13d\),%al + +[a-f0-9]+: 67 41 8a 45 00 mov 0x0\(%r13d\),%al + +[a-f0-9]+: 67 41 8a 85 00 00 00 00 mov 0x0\(%r13d\),%al +[a-f0-9]+: c4 e1 78 28 d7 vmovaps %xmm7,%xmm2 +[a-f0-9]+: c4 e1 78 28 d7 vmovaps %xmm7,%xmm2 +[a-f0-9]+: c4 e1 78 29 fa vmovaps %xmm7,%xmm2 @@ -365,4 +371,10 @@ Disassembly of section .text: +[a-f0-9]+: 67 8a 45 00 mov 0x0\(%ebp\),%al +[a-f0-9]+: 67 8a 45 00 mov 0x0\(%ebp\),%al +[a-f0-9]+: 67 8a 85 00 00 00 00 mov 0x0\(%ebp\),%al + +[a-f0-9]+: 41 8a 45 00 mov 0x0\(%r13\),%al + +[a-f0-9]+: 41 8a 45 00 mov 0x0\(%r13\),%al + +[a-f0-9]+: 41 8a 85 00 00 00 00 mov 0x0\(%r13\),%al + +[a-f0-9]+: 41 8a 45 00 mov 0x0\(%r13\),%al + +[a-f0-9]+: 67 41 8a 45 00 mov 0x0\(%r13d\),%al + +[a-f0-9]+: 67 41 8a 85 00 00 00 00 mov 0x0\(%r13d\),%al #pass diff --git a/gas/testsuite/gas/i386/x86-64-pseudos.s b/gas/testsuite/gas/i386/x86-64-pseudos.s index 3b3638cf75..5f5fe5c574 100644 --- a/gas/testsuite/gas/i386/x86-64-pseudos.s +++ b/gas/testsuite/gas/i386/x86-64-pseudos.s @@ -328,6 +328,14 @@ _start: {disp8} movb (%ebp),%al {disp32} movb (%ebp),%al + movb (%r13),%al + {disp8} movb (%r13),%al + {disp32} movb (%r13),%al + + movb (%r13d),%al + {disp8} movb (%r13d),%al + {disp32} movb (%r13d),%al + .intel_syntax noprefix {vex3} vmovaps xmm2,xmm7 {vex3} {load} vmovaps xmm2,xmm7 @@ -375,3 +383,11 @@ _start: mov al, BYTE PTR [ebp] {disp8} mov al, BYTE PTR [ebp] {disp32} mov al, BYTE PTR [ebp] + + mov al, BYTE PTR [r13] + {disp8} mov al, BYTE PTR [r13] + {disp32} mov al, BYTE PTR [r13] + + mov al, BYTE PTR [r13] + {disp8} mov al, BYTE PTR [r13d] + {disp32} mov al, BYTE PTR [r13d] diff --git a/opcodes/i386-opc.tbl b/opcodes/i386-opc.tbl index bb7fb02dde..56601707b0 100644 --- a/opcodes/i386-opc.tbl +++ b/opcodes/i386-opc.tbl @@ -845,6 +845,7 @@ rex.wrxb, 0, 0x4f, None, 1, Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ld {evex}, 0, 0x6, None, 0, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsPrefix, { 0 } {rex}, 0, 0x7, None, 0, Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsPrefix, { 0 } {nooptimize}, 0, 0x8, None, 0, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsPrefix, { 0 } +{disp16}, 0, 0x9, None, 0, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsPrefix, { 0 } // 486 extensions. diff --git a/opcodes/i386-tbl.h b/opcodes/i386-tbl.h index a3aa69175a..e4e7a3ed58 100644 --- a/opcodes/i386-tbl.h +++ b/opcodes/i386-tbl.h @@ -7704,6 +7704,18 @@ const insn_template i386_optab[] = 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } } }, + { "{disp16}", 0x9, None, 0, 0, + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, + { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, + { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0 } } } }, { "bswap", 0xfc8, None, 2, 1, { { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, -- 2.26.2 ^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH] x86: Add {disp16} pseudo prefix 2020-07-28 20:30 ` [PATCH] x86: Add {disp16} pseudo prefix H.J. Lu @ 2020-07-29 20:26 ` Jan Beulich 2020-07-29 22:53 ` H.J. Lu 0 siblings, 1 reply; 15+ messages in thread From: Jan Beulich @ 2020-07-29 20:26 UTC (permalink / raw) To: H.J. Lu; +Cc: Binutils On 28.07.2020 22:30, H.J. Lu wrote: > On Tue, Jul 28, 2020 at 12:02 PM H.J. Lu <hjl.tools@gmail.com> wrote: >> >> On Tue, Jul 28, 2020 at 11:43 AM Jan Beulich <jbeulich@suse.com> wrote: >>> >>> On 28.07.2020 01:23, H.J. Lu via Binutils wrote: >>>> Since (%bp)/(%ebp)/(%rbp) are encoded as 0(%bp)/0(%ebp)/0(%rbp), use >>>> disp32/disp16 on 0(%bp)/0(%ebp)/0(%rbp) for {disp32}. >>> >>> Same for (%r13d) / (%r13) afaict? >> >> Yes. {disp32} works on (%r13d) / (%r13) now: >> >> [hjl@gnu-cfl-2 testsuite]$ cat x.s >> movb (%r13),%al >> {disp8} movb (%r13),%al >> {disp32} movb (%r13),%al >> >> movb (%r13d),%al >> {disp8} movb (%r13d),%al >> {disp32} movb (%r13d),%al >> [hjl@gnu-cfl-2 testsuite]$ gcc -c x.s >> [hjl@gnu-cfl-2 testsuite]$ objdump -dw x.o >> >> x.o: file format elf64-x86-64 >> >> >> Disassembly of section .text: >> >> 0000000000000000 <.text>: >> 0: 41 8a 45 00 mov 0x0(%r13),%al >> 4: 41 8a 45 00 mov 0x0(%r13),%al >> 8: 41 8a 45 00 mov 0x0(%r13),%al >> c: 67 41 8a 45 00 mov 0x0(%r13d),%al >> 11: 67 41 8a 45 00 mov 0x0(%r13d),%al >> 16: 67 41 8a 45 00 mov 0x0(%r13d),%al >> [hjl@gnu-cfl-2 testsuite]$ ../as-new -o x.o x.s >> [hjl@gnu-cfl-2 testsuite]$ objdump -dw x.o >> >> x.o: file format elf64-x86-64 >> >> >> Disassembly of section .text: >> >> 0000000000000000 <.text>: >> 0: 41 8a 45 00 mov 0x0(%r13),%al >> 4: 41 8a 45 00 mov 0x0(%r13),%al >> 8: 41 8a 85 00 00 00 00 mov 0x0(%r13),%al >> f: 67 41 8a 45 00 mov 0x0(%r13d),%al >> 14: 67 41 8a 45 00 mov 0x0(%r13d),%al >> 19: 67 41 8a 85 00 00 00 00 mov 0x0(%r13d),%al >> [hjl@gnu-cfl-2 testsuite]$ >> >> >>>> Note: Since there is no disp32 on 0(%bp), use disp16 instead. >>> >>> What use is it to fix the special case of (%bp) when the more general >>> case ((%bx), (%si), etc) doesn't work? I anyway think that instead of >>> ... >>> >>>> --- a/gas/config/tc-i386.c >>>> +++ b/gas/config/tc-i386.c >>>> @@ -8151,7 +8151,12 @@ build_modrm_byte (void) >>>> if (operand_type_check (i.types[op], disp) == 0) >>>> { >>>> /* fake (%bp) into 0(%bp) */ >>>> - i.types[op].bitfield.disp8 = 1; >>>> + if (i.disp_encoding == disp_encoding_32bit) >>>> + /* NB: Use disp16 since there is no disp32 >>>> + in 16-bit mode. */ >>>> + i.types[op].bitfield.disp16 = 1; >>>> + else >>>> + i.types[op].bitfield.disp8 = 1; >>>> fake_zero_displacement = 1; >>>> } >>> >>> ... the comment you add here, support for {disp16} should be added. >>> >> >> I will add {disp16} to master branch. >> > > Add {disp16} pseudo prefix and replace {disp32} pseudo prefix with > {disp16} in 16-bit mode test. Check invalid {disp16}/{disp32} pseudo > prefixes. The inval-pseudo test is a 32-bit one; you shouldn't use .code64 there, or you'll cause FAILs on 32-bit only builds. > Note: {disp16} can be also used on branches in 32-bit mode. But you don't add any tests to this effect, so it's hard to see what exactly this means. To be honest I'm not sure this is helpful: A means to widen the default displacement may be useful, but one to narrow not just the displacement, but also the resulting new IP? I was also wanting to ask that you group the new pseudo prefix with its sibling ones in the opcode table, but I realize the use of hard coded numbers makes this cumbersome. Time to do away with that? I also have a tangential question: Shouldn't e.g. {disp8} vmovaps %xmm0,128(%eax) be taken as a request to use EVEX encoding, to satisfy the pseudo prefix? Unless {vex} was also specified, at which point things become "interesting" (but the way they're documented I think {vex} has to have more wight here). Jan ^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH] x86: Add {disp16} pseudo prefix 2020-07-29 20:26 ` Jan Beulich @ 2020-07-29 22:53 ` H.J. Lu 2020-07-29 23:39 ` V2 " H.J. Lu 2020-07-31 6:22 ` Jan Beulich 0 siblings, 2 replies; 15+ messages in thread From: H.J. Lu @ 2020-07-29 22:53 UTC (permalink / raw) To: Jan Beulich; +Cc: Binutils On Wed, Jul 29, 2020 at 1:26 PM Jan Beulich <jbeulich@suse.com> wrote: > > On 28.07.2020 22:30, H.J. Lu wrote: > > On Tue, Jul 28, 2020 at 12:02 PM H.J. Lu <hjl.tools@gmail.com> wrote: > >> > >> On Tue, Jul 28, 2020 at 11:43 AM Jan Beulich <jbeulich@suse.com> wrote: > >>> > >>> On 28.07.2020 01:23, H.J. Lu via Binutils wrote: > >>>> Since (%bp)/(%ebp)/(%rbp) are encoded as 0(%bp)/0(%ebp)/0(%rbp), use > >>>> disp32/disp16 on 0(%bp)/0(%ebp)/0(%rbp) for {disp32}. > >>> > >>> Same for (%r13d) / (%r13) afaict? > >> > >> Yes. {disp32} works on (%r13d) / (%r13) now: > >> > >> [hjl@gnu-cfl-2 testsuite]$ cat x.s > >> movb (%r13),%al > >> {disp8} movb (%r13),%al > >> {disp32} movb (%r13),%al > >> > >> movb (%r13d),%al > >> {disp8} movb (%r13d),%al > >> {disp32} movb (%r13d),%al > >> [hjl@gnu-cfl-2 testsuite]$ gcc -c x.s > >> [hjl@gnu-cfl-2 testsuite]$ objdump -dw x.o > >> > >> x.o: file format elf64-x86-64 > >> > >> > >> Disassembly of section .text: > >> > >> 0000000000000000 <.text>: > >> 0: 41 8a 45 00 mov 0x0(%r13),%al > >> 4: 41 8a 45 00 mov 0x0(%r13),%al > >> 8: 41 8a 45 00 mov 0x0(%r13),%al > >> c: 67 41 8a 45 00 mov 0x0(%r13d),%al > >> 11: 67 41 8a 45 00 mov 0x0(%r13d),%al > >> 16: 67 41 8a 45 00 mov 0x0(%r13d),%al > >> [hjl@gnu-cfl-2 testsuite]$ ../as-new -o x.o x.s > >> [hjl@gnu-cfl-2 testsuite]$ objdump -dw x.o > >> > >> x.o: file format elf64-x86-64 > >> > >> > >> Disassembly of section .text: > >> > >> 0000000000000000 <.text>: > >> 0: 41 8a 45 00 mov 0x0(%r13),%al > >> 4: 41 8a 45 00 mov 0x0(%r13),%al > >> 8: 41 8a 85 00 00 00 00 mov 0x0(%r13),%al > >> f: 67 41 8a 45 00 mov 0x0(%r13d),%al > >> 14: 67 41 8a 45 00 mov 0x0(%r13d),%al > >> 19: 67 41 8a 85 00 00 00 00 mov 0x0(%r13d),%al > >> [hjl@gnu-cfl-2 testsuite]$ > >> > >> > >>>> Note: Since there is no disp32 on 0(%bp), use disp16 instead. > >>> > >>> What use is it to fix the special case of (%bp) when the more general > >>> case ((%bx), (%si), etc) doesn't work? I anyway think that instead of > >>> ... > >>> > >>>> --- a/gas/config/tc-i386.c > >>>> +++ b/gas/config/tc-i386.c > >>>> @@ -8151,7 +8151,12 @@ build_modrm_byte (void) > >>>> if (operand_type_check (i.types[op], disp) == 0) > >>>> { > >>>> /* fake (%bp) into 0(%bp) */ > >>>> - i.types[op].bitfield.disp8 = 1; > >>>> + if (i.disp_encoding == disp_encoding_32bit) > >>>> + /* NB: Use disp16 since there is no disp32 > >>>> + in 16-bit mode. */ > >>>> + i.types[op].bitfield.disp16 = 1; > >>>> + else > >>>> + i.types[op].bitfield.disp8 = 1; > >>>> fake_zero_displacement = 1; > >>>> } > >>> > >>> ... the comment you add here, support for {disp16} should be added. > >>> > >> > >> I will add {disp16} to master branch. > >> > > > > Add {disp16} pseudo prefix and replace {disp32} pseudo prefix with > > {disp16} in 16-bit mode test. Check invalid {disp16}/{disp32} pseudo > > prefixes. > > The inval-pseudo test is a 32-bit one; you shouldn't use .code64 there, > or you'll cause FAILs on 32-bit only builds. I will fix it. > > Note: {disp16} can be also used on branches in 32-bit mode. > > But you don't add any tests to this effect, so it's hard to see what > exactly this means. To be honest I'm not sure this is helpful: A means > to widen the default displacement may be useful, but one to narrow not > just the displacement, but also the resulting new IP? {disp16} can be used to generate "branch rel16". But implementation may be non-trivial. > I was also wanting to ask that you group the new pseudo prefix with > its sibling ones in the opcode table, but I realize the use of > hard coded numbers makes this cumbersome. Time to do away with that? I will take a look. > I also have a tangential question: Shouldn't e.g. > > {disp8} vmovaps %xmm0,128(%eax) > > be taken as a request to use EVEX encoding, to satisfy the pseudo > prefix? Unless {vex} was also specified, at which point things > become "interesting" (but the way they're documented I think > {vex} has to have more wight here). > {disp8} is a hint for VEX. It shouldn't change to EVEX. -- H.J. ^ permalink raw reply [flat|nested] 15+ messages in thread
* V2 [PATCH] x86: Add {disp16} pseudo prefix 2020-07-29 22:53 ` H.J. Lu @ 2020-07-29 23:39 ` H.J. Lu 2020-07-31 7:03 ` Jan Beulich 2020-08-04 12:36 ` H.J. Lu 2020-07-31 6:22 ` Jan Beulich 1 sibling, 2 replies; 15+ messages in thread From: H.J. Lu @ 2020-07-29 23:39 UTC (permalink / raw) To: Jan Beulich; +Cc: Binutils [-- Attachment #1: Type: text/plain, Size: 4826 bytes --] On Wed, Jul 29, 2020 at 3:53 PM H.J. Lu <hjl.tools@gmail.com> wrote: > > On Wed, Jul 29, 2020 at 1:26 PM Jan Beulich <jbeulich@suse.com> wrote: > > > > On 28.07.2020 22:30, H.J. Lu wrote: > > > On Tue, Jul 28, 2020 at 12:02 PM H.J. Lu <hjl.tools@gmail.com> wrote: > > >> > > >> On Tue, Jul 28, 2020 at 11:43 AM Jan Beulich <jbeulich@suse.com> wrote: > > >>> > > >>> On 28.07.2020 01:23, H.J. Lu via Binutils wrote: > > >>>> Since (%bp)/(%ebp)/(%rbp) are encoded as 0(%bp)/0(%ebp)/0(%rbp), use > > >>>> disp32/disp16 on 0(%bp)/0(%ebp)/0(%rbp) for {disp32}. > > >>> > > >>> Same for (%r13d) / (%r13) afaict? > > >> > > >> Yes. {disp32} works on (%r13d) / (%r13) now: > > >> > > >> [hjl@gnu-cfl-2 testsuite]$ cat x.s > > >> movb (%r13),%al > > >> {disp8} movb (%r13),%al > > >> {disp32} movb (%r13),%al > > >> > > >> movb (%r13d),%al > > >> {disp8} movb (%r13d),%al > > >> {disp32} movb (%r13d),%al > > >> [hjl@gnu-cfl-2 testsuite]$ gcc -c x.s > > >> [hjl@gnu-cfl-2 testsuite]$ objdump -dw x.o > > >> > > >> x.o: file format elf64-x86-64 > > >> > > >> > > >> Disassembly of section .text: > > >> > > >> 0000000000000000 <.text>: > > >> 0: 41 8a 45 00 mov 0x0(%r13),%al > > >> 4: 41 8a 45 00 mov 0x0(%r13),%al > > >> 8: 41 8a 45 00 mov 0x0(%r13),%al > > >> c: 67 41 8a 45 00 mov 0x0(%r13d),%al > > >> 11: 67 41 8a 45 00 mov 0x0(%r13d),%al > > >> 16: 67 41 8a 45 00 mov 0x0(%r13d),%al > > >> [hjl@gnu-cfl-2 testsuite]$ ../as-new -o x.o x.s > > >> [hjl@gnu-cfl-2 testsuite]$ objdump -dw x.o > > >> > > >> x.o: file format elf64-x86-64 > > >> > > >> > > >> Disassembly of section .text: > > >> > > >> 0000000000000000 <.text>: > > >> 0: 41 8a 45 00 mov 0x0(%r13),%al > > >> 4: 41 8a 45 00 mov 0x0(%r13),%al > > >> 8: 41 8a 85 00 00 00 00 mov 0x0(%r13),%al > > >> f: 67 41 8a 45 00 mov 0x0(%r13d),%al > > >> 14: 67 41 8a 45 00 mov 0x0(%r13d),%al > > >> 19: 67 41 8a 85 00 00 00 00 mov 0x0(%r13d),%al > > >> [hjl@gnu-cfl-2 testsuite]$ > > >> > > >> > > >>>> Note: Since there is no disp32 on 0(%bp), use disp16 instead. > > >>> > > >>> What use is it to fix the special case of (%bp) when the more general > > >>> case ((%bx), (%si), etc) doesn't work? I anyway think that instead of > > >>> ... > > >>> > > >>>> --- a/gas/config/tc-i386.c > > >>>> +++ b/gas/config/tc-i386.c > > >>>> @@ -8151,7 +8151,12 @@ build_modrm_byte (void) > > >>>> if (operand_type_check (i.types[op], disp) == 0) > > >>>> { > > >>>> /* fake (%bp) into 0(%bp) */ > > >>>> - i.types[op].bitfield.disp8 = 1; > > >>>> + if (i.disp_encoding == disp_encoding_32bit) > > >>>> + /* NB: Use disp16 since there is no disp32 > > >>>> + in 16-bit mode. */ > > >>>> + i.types[op].bitfield.disp16 = 1; > > >>>> + else > > >>>> + i.types[op].bitfield.disp8 = 1; > > >>>> fake_zero_displacement = 1; > > >>>> } > > >>> > > >>> ... the comment you add here, support for {disp16} should be added. > > >>> > > >> > > >> I will add {disp16} to master branch. > > >> > > > > > > Add {disp16} pseudo prefix and replace {disp32} pseudo prefix with > > > {disp16} in 16-bit mode test. Check invalid {disp16}/{disp32} pseudo > > > prefixes. > > > > The inval-pseudo test is a 32-bit one; you shouldn't use .code64 there, > > or you'll cause FAILs on 32-bit only builds. > > I will fix it. > > > > Note: {disp16} can be also used on branches in 32-bit mode. > > > > But you don't add any tests to this effect, so it's hard to see what > > exactly this means. To be honest I'm not sure this is helpful: A means > > to widen the default displacement may be useful, but one to narrow not > > just the displacement, but also the resulting new IP? > > {disp16} can be used to generate "branch rel16". But implementation > may be non-trivial. > > > I was also wanting to ask that you group the new pseudo prefix with > > its sibling ones in the opcode table, but I realize the use of > > hard coded numbers makes this cumbersome. Time to do away with that? > > I will take a look. > > > I also have a tangential question: Shouldn't e.g. > > > > {disp8} vmovaps %xmm0,128(%eax) > > > > be taken as a request to use EVEX encoding, to satisfy the pseudo > > prefix? Unless {vex} was also specified, at which point things > > become "interesting" (but the way they're documented I think > > {vex} has to have more wight here). > > > > {disp8} is a hint for VEX. It shouldn't change to EVEX. > Here is the updated patch. -- H.J. [-- Attachment #2: 0001-x86-Add-disp16-pseudo-prefix.patch --] [-- Type: text/x-patch, Size: 28654 bytes --] From 0cc9077962b4373d39be8de25b1e9c46e63a3e28 Mon Sep 17 00:00:00 2001 From: "H.J. Lu" <hjl.tools@gmail.com> Date: Tue, 28 Jul 2020 13:19:17 -0700 Subject: [PATCH] x86: Add {disp16} pseudo prefix Use Prefix_XXX for pseudo prefixes. Add {disp16} pseudo prefix and replace {disp32} pseudo prefix with {disp16} in 16-bit mode test. Check invalid {disp16}/{disp32} pseudo prefixes. gas/ PR gas/26305 * config/tc-i386.c (_i386_insn::disp_encoding): Add disp_encoding_16bit. (parse_insn): Check Prefix_XXX for pseudo prefixes. Handle {disp16}. (build_modrm_byte): Handle {disp16}. (i386_index_check): Check invalid {disp16} and {disp32} pseudo prefixes. * doc/c-i386.texi: Update {disp32} documentation and document {disp16}. * testsuite/gas/i386/i386.exp: Run x86-64-inval-pseudo. * testsuite/gas/i386/inval-pseudo.s: Add {disp32}/{disp16} tests. * testsuite/gas/i386/pseudos.s: Add {disp8}/{disp32} vmovaps tests with 128-byte displacement. Add {disp16} tests. * testsuite/gas/i386/x86-64-pseudos.s: Add {disp8}/{disp32} vmovaps test. Add (%r13)/(%r13d) tests. * testsuite/gas/i386/x86-64-inval-pseudo.l: New file. * testsuite/gas/i386/x86-64-inval-pseudo.s: Likewise. * testsuite/gas/i386/inval-pseudo.l: Updated. * testsuite/gas/i386/pseudos.d: Likewise. * testsuite/gas/i386/x86-64-pseudos.d: Likewise. opcodes/ PR gas/26305 * i386-opc.h (Prefix_Disp8): New. (Prefix_Disp16): Likewise. (Prefix_Disp32): Likewise. (Prefix_Load): Likewise. (Prefix_Store): Likewise. (Prefix_VEX): Likewise. (Prefix_VEX3): Likewise. (Prefix_EVEX): Likewise. (Prefix_REX): Likewise. (Prefix_NoOptimize): Likewise. * i386-opc.tbl: Use Prefix_XXX on pseudo prefixes. Add {disp16}. * i386-tbl.h: Regenerated. --- gas/config/tc-i386.c | 50 +++++++++++++++----- gas/doc/c-i386.texi | 5 +- gas/testsuite/gas/i386/i386.exp | 1 + gas/testsuite/gas/i386/inval-pseudo.l | 6 ++- gas/testsuite/gas/i386/inval-pseudo.s | 2 + gas/testsuite/gas/i386/pseudos.d | 28 +++++++++-- gas/testsuite/gas/i386/pseudos.s | 35 ++++++++++++-- gas/testsuite/gas/i386/x86-64-inval-pseudo.l | 10 ++++ gas/testsuite/gas/i386/x86-64-inval-pseudo.s | 4 ++ gas/testsuite/gas/i386/x86-64-pseudos.d | 22 ++++++++- gas/testsuite/gas/i386/x86-64-pseudos.s | 27 +++++++++++ opcodes/i386-opc.h | 12 +++++ opcodes/i386-opc.tbl | 21 ++++---- opcodes/i386-tbl.h | 32 +++++++++---- 14 files changed, 211 insertions(+), 44 deletions(-) create mode 100644 gas/testsuite/gas/i386/x86-64-inval-pseudo.l create mode 100644 gas/testsuite/gas/i386/x86-64-inval-pseudo.s diff --git a/gas/config/tc-i386.c b/gas/config/tc-i386.c index 11d0e992f9..7c21df8d9a 100644 --- a/gas/config/tc-i386.c +++ b/gas/config/tc-i386.c @@ -409,11 +409,12 @@ struct _i386_insn dir_encoding_swap } dir_encoding; - /* Prefer 8bit or 32bit displacement in encoding. */ + /* Prefer 8bit, 16bit, 32bit displacement in encoding. */ enum { disp_encoding_default = 0, disp_encoding_8bit, + disp_encoding_16bit, disp_encoding_32bit } disp_encoding; @@ -5119,39 +5120,43 @@ parse_insn (char *line, char *mnemonic) /* Handle pseudo prefixes. */ switch (current_templates->start->base_opcode) { - case 0x0: + case Prefix_Disp8: /* {disp8} */ i.disp_encoding = disp_encoding_8bit; break; - case 0x1: + case Prefix_Disp16: + /* {disp16} */ + i.disp_encoding = disp_encoding_16bit; + break; + case Prefix_Disp32: /* {disp32} */ i.disp_encoding = disp_encoding_32bit; break; - case 0x2: + case Prefix_Load: /* {load} */ i.dir_encoding = dir_encoding_load; break; - case 0x3: + case Prefix_Store: /* {store} */ i.dir_encoding = dir_encoding_store; break; - case 0x4: + case Prefix_VEX: /* {vex} */ i.vec_encoding = vex_encoding_vex; break; - case 0x5: + case Prefix_VEX3: /* {vex3} */ i.vec_encoding = vex_encoding_vex3; break; - case 0x6: + case Prefix_EVEX: /* {evex} */ i.vec_encoding = vex_encoding_evex; break; - case 0x7: + case Prefix_REX: /* {rex} */ i.rex_encoding = TRUE; break; - case 0x8: + case Prefix_NoOptimize: /* {nooptimize} */ i.no_optimize = TRUE; break; @@ -8151,9 +8156,7 @@ build_modrm_byte (void) if (operand_type_check (i.types[op], disp) == 0) { /* fake (%bp) into 0(%bp) */ - if (i.disp_encoding == disp_encoding_32bit) - /* NB: Use disp16 since there is no disp32 - in 16-bit mode. */ + if (i.disp_encoding == disp_encoding_16bit) i.types[op].bitfield.disp16 = 1; else i.types[op].bitfield.disp8 = 1; @@ -8166,6 +8169,16 @@ build_modrm_byte (void) default: /* (%si) -> 4 or (%di) -> 5 */ i.rm.regmem = i.base_reg->reg_num - 6 + 4; } + if (!fake_zero_displacement + && !i.disp_operands + && i.disp_encoding) + { + fake_zero_displacement = 1; + if (i.disp_encoding == disp_encoding_8bit) + i.types[op].bitfield.disp8 = 1; + else + i.types[op].bitfield.disp16 = 1; + } i.rm.mode = mode_from_disp_size (i.types[op]); } else /* i.base_reg and 32/64 bit mode */ @@ -11012,6 +11025,14 @@ i386_index_check (const char *operand_string) if (addr_mode != CODE_16BIT) { /* 32-bit/64-bit checks. */ + if (i.disp_encoding == disp_encoding_16bit) + { + bad_disp: + as_bad (_("invalid `%s' prefix"), + addr_mode == CODE_16BIT ? "{disp32}" : "{disp16}"); + return 0; + } + if ((i.base_reg && ((addr_mode == CODE_64BIT ? !i.base_reg->reg_type.bitfield.qword @@ -11049,6 +11070,9 @@ i386_index_check (const char *operand_string) else { /* 16-bit checks. */ + if (i.disp_encoding == disp_encoding_32bit) + goto bad_disp; + if ((i.base_reg && (!i.base_reg->reg_type.bitfield.word || !i.base_reg->reg_type.bitfield.baseindex)) diff --git a/gas/doc/c-i386.texi b/gas/doc/c-i386.texi index 8be708e745..64a563aacb 100644 --- a/gas/doc/c-i386.texi +++ b/gas/doc/c-i386.texi @@ -822,7 +822,10 @@ Different encoding options can be specified via pseudo prefixes: @samp{@{disp8@}} -- prefer 8-bit displacement. @item -@samp{@{disp32@}} -- prefer 32-bit (16-bit in 16-bit mode) displacement. +@samp{@{disp32@}} -- prefer 32-bit displacement. + +@item +@samp{@{disp16@}} -- prefer 16-bit displacement. @item @samp{@{load@}} -- prefer load-form instruction. diff --git a/gas/testsuite/gas/i386/i386.exp b/gas/testsuite/gas/i386/i386.exp index 0ac9c1f129..0a863ff3bd 100644 --- a/gas/testsuite/gas/i386/i386.exp +++ b/gas/testsuite/gas/i386/i386.exp @@ -1105,6 +1105,7 @@ if [expr ([istarget "i*86-*-*"] || [istarget "x86_64-*-*"]) && [gas_64_check]] t run_list_test "x86-64-cet-shstk-inval" run_dump_test "x86-64-pseudos" run_list_test "x86-64-pseudos-bad" + run_list_test "x86-64-inval-pseudo" "-al" run_dump_test "x86-64-notrack" run_dump_test "x86-64-notrack-intel" run_list_test "x86-64-notrackbad" "-al" diff --git a/gas/testsuite/gas/i386/inval-pseudo.l b/gas/testsuite/gas/i386/inval-pseudo.l index cf344f6986..9df0a9851f 100644 --- a/gas/testsuite/gas/i386/inval-pseudo.l +++ b/gas/testsuite/gas/i386/inval-pseudo.l @@ -1,5 +1,7 @@ .*: Assembler messages: .*:3: Error: .* +.*:5: Error: .* +.*:6: Error: .* GAS LISTING .* @@ -7,5 +9,7 @@ GAS LISTING .* [ ]*2[ ]+\?\?\?\? 90 nop [ ]*3[ ]+\{disp32\} [ ]*4[ ]+\?\?\?\? 90 nop -[ ]*5[ ]+\?\?\?\? 00000000 \.p2align 4,0 +[ ]*5[ ]+\{disp32\} movb \(%bp\),%al +[ ]*6[ ]+\{disp16\} movb \(%ebp\),%al +[ ]*7[ ]+\?\?\?\? 00000000 \.p2align 4,0 #... diff --git a/gas/testsuite/gas/i386/inval-pseudo.s b/gas/testsuite/gas/i386/inval-pseudo.s index a40362b8f9..b5a6233eb1 100644 --- a/gas/testsuite/gas/i386/inval-pseudo.s +++ b/gas/testsuite/gas/i386/inval-pseudo.s @@ -2,4 +2,6 @@ nop {disp32} nop + {disp32} movb (%bp),%al + {disp16} movb (%ebp),%al .p2align 4,0 diff --git a/gas/testsuite/gas/i386/pseudos.d b/gas/testsuite/gas/i386/pseudos.d index 76aae367b4..4f029f154b 100644 --- a/gas/testsuite/gas/i386/pseudos.d +++ b/gas/testsuite/gas/i386/pseudos.d @@ -22,6 +22,10 @@ Disassembly of section .text: +[a-f0-9]+: c5 f8 28 90 00 00 00 00 vmovaps 0x0\(%eax\),%xmm2 +[a-f0-9]+: 62 f1 7c 08 28 50 00 vmovaps 0x0\(%eax\),%xmm2 +[a-f0-9]+: 62 f1 7c 08 28 90 00 00 00 00 vmovaps 0x0\(%eax\),%xmm2 + +[a-f0-9]+: c5 f8 28 90 80 00 00 00 vmovaps 0x80\(%eax\),%xmm2 + +[a-f0-9]+: c5 f8 28 90 80 00 00 00 vmovaps 0x80\(%eax\),%xmm2 + +[a-f0-9]+: 62 f1 7c 08 28 50 08 vmovaps 0x80\(%eax\),%xmm2 + +[a-f0-9]+: 62 f1 7c 08 28 90 80 00 00 00 vmovaps 0x80\(%eax\),%xmm2 +[a-f0-9]+: 89 c8 mov %ecx,%eax +[a-f0-9]+: 8b c1 mov %ecx,%eax +[a-f0-9]+: 89 c8 mov %ecx,%eax @@ -291,9 +295,15 @@ Disassembly of section .text: +[a-f0-9]+: 8a 45 00 mov 0x0\(%ebp\),%al +[a-f0-9]+: 8a 45 00 mov 0x0\(%ebp\),%al +[a-f0-9]+: 8a 85 00 00 00 00 mov 0x0\(%ebp\),%al + +[a-f0-9]+: 67 8a 04 mov \(%si\),%al + +[a-f0-9]+: 67 8a 44 00 mov 0x0\(%si\),%al + +[a-f0-9]+: 67 8a 84 00 00 mov 0x0\(%si\),%al + +[a-f0-9]+: 67 8a 05 mov \(%di\),%al + +[a-f0-9]+: 67 8a 45 00 mov 0x0\(%di\),%al + +[a-f0-9]+: 67 8a 85 00 00 mov 0x0\(%di\),%al +[a-f0-9]+: 67 8a 07 mov \(%bx\),%al - +[a-f0-9]+: 67 8a 07 mov \(%bx\),%al - +[a-f0-9]+: 67 8a 07 mov \(%bx\),%al + +[a-f0-9]+: 67 8a 47 00 mov 0x0\(%bx\),%al + +[a-f0-9]+: 67 8a 87 00 00 mov 0x0\(%bx\),%al +[a-f0-9]+: 67 8a 46 00 mov 0x0\(%bp\),%al +[a-f0-9]+: 67 8a 46 00 mov 0x0\(%bp\),%al +[a-f0-9]+: 67 8a 86 00 00 mov 0x0\(%bp\),%al @@ -311,6 +321,10 @@ Disassembly of section .text: +[a-f0-9]+: c5 f8 28 90 00 00 00 00 vmovaps 0x0\(%eax\),%xmm2 +[a-f0-9]+: 62 f1 7c 08 28 50 00 vmovaps 0x0\(%eax\),%xmm2 +[a-f0-9]+: 62 f1 7c 08 28 90 00 00 00 00 vmovaps 0x0\(%eax\),%xmm2 + +[a-f0-9]+: c5 f8 28 90 80 00 00 00 vmovaps 0x80\(%eax\),%xmm2 + +[a-f0-9]+: c5 f8 28 90 80 00 00 00 vmovaps 0x80\(%eax\),%xmm2 + +[a-f0-9]+: 62 f1 7c 08 28 50 08 vmovaps 0x80\(%eax\),%xmm2 + +[a-f0-9]+: 62 f1 7c 08 28 90 80 00 00 00 vmovaps 0x80\(%eax\),%xmm2 +[a-f0-9]+: 89 c8 mov %ecx,%eax +[a-f0-9]+: 8b c1 mov %ecx,%eax +[a-f0-9]+: 89 c8 mov %ecx,%eax @@ -328,9 +342,15 @@ Disassembly of section .text: +[a-f0-9]+: 8a 45 00 mov 0x0\(%ebp\),%al +[a-f0-9]+: 8a 45 00 mov 0x0\(%ebp\),%al +[a-f0-9]+: 8a 85 00 00 00 00 mov 0x0\(%ebp\),%al + +[a-f0-9]+: 67 8a 04 mov \(%si\),%al + +[a-f0-9]+: 67 8a 44 00 mov 0x0\(%si\),%al + +[a-f0-9]+: 67 8a 84 00 00 mov 0x0\(%si\),%al + +[a-f0-9]+: 67 8a 05 mov \(%di\),%al + +[a-f0-9]+: 67 8a 45 00 mov 0x0\(%di\),%al + +[a-f0-9]+: 67 8a 85 00 00 mov 0x0\(%di\),%al +[a-f0-9]+: 67 8a 07 mov \(%bx\),%al - +[a-f0-9]+: 67 8a 07 mov \(%bx\),%al - +[a-f0-9]+: 67 8a 07 mov \(%bx\),%al + +[a-f0-9]+: 67 8a 47 00 mov 0x0\(%bx\),%al + +[a-f0-9]+: 67 8a 87 00 00 mov 0x0\(%bx\),%al +[a-f0-9]+: 67 8a 46 00 mov 0x0\(%bp\),%al +[a-f0-9]+: 67 8a 46 00 mov 0x0\(%bp\),%al +[a-f0-9]+: 67 8a 86 00 00 mov 0x0\(%bp\),%al diff --git a/gas/testsuite/gas/i386/pseudos.s b/gas/testsuite/gas/i386/pseudos.s index bc18654ced..603e112ac8 100644 --- a/gas/testsuite/gas/i386/pseudos.s +++ b/gas/testsuite/gas/i386/pseudos.s @@ -17,6 +17,11 @@ _start: {evex} {disp8} vmovaps (%eax),%xmm2 {evex} {disp32} vmovaps (%eax),%xmm2 + {vex} {disp8} vmovaps 128(%eax),%xmm2 + {vex} {disp32} vmovaps 128(%eax),%xmm2 + {evex} {disp8} vmovaps 128(%eax),%xmm2 + {evex} {disp32} vmovaps 128(%eax),%xmm2 + mov %ecx, %eax {load} mov %ecx, %eax {store} mov %ecx, %eax @@ -297,13 +302,21 @@ _start: {disp8} movb (%ebp),%al {disp32} movb (%ebp),%al + movb (%si),%al + {disp8} movb (%si),%al + {disp16} movb (%si),%al + + movb (%di),%al + {disp8} movb (%di),%al + {disp16} movb (%di),%al + movb (%bx),%al {disp8} movb (%bx),%al - {disp32} movb (%bx),%al + {disp16} movb (%bx),%al movb (%bp),%al {disp8} movb (%bp),%al - {disp32} movb (%bp),%al + {disp16} movb (%bp),%al .intel_syntax noprefix {vex3} vmovaps xmm2,xmm7 @@ -320,6 +333,12 @@ _start: {disp32} vmovaps xmm2,XMMWORD PTR [eax] {evex} {disp8} vmovaps xmm2,XMMWORD PTR [eax] {evex} {disp32} vmovaps xmm2,XMMWORD PTR [eax] + + {vex} {disp8} vmovaps xmm2,XMMWORD PTR [eax+128] + {vex} {disp32} vmovaps xmm2,XMMWORD PTR [eax+128] + {evex} {disp8} vmovaps xmm2,XMMWORD PTR [eax+128] + {evex} {disp32} vmovaps xmm2,XMMWORD PTR [eax+128] + mov eax,ecx {load} mov eax,ecx {store} mov eax,ecx @@ -339,10 +358,18 @@ _start: {disp8} mov al, BYTE PTR [ebp] {disp32} mov al, BYTE PTR [ebp] + mov al, BYTE PTR [si] + {disp8} mov al, BYTE PTR [si] + {disp16} mov al, BYTE PTR [si] + + mov al, BYTE PTR [di] + {disp8} mov al, BYTE PTR [di] + {disp16} mov al, BYTE PTR [di] + mov al, BYTE PTR [bx] {disp8} mov al, BYTE PTR [bx] - {disp32} mov al, BYTE PTR [bx] + {disp16} mov al, BYTE PTR [bx] mov al, BYTE PTR [bp] {disp8} mov al, BYTE PTR [bp] - {disp32} mov al, BYTE PTR [bp] + {disp16} mov al, BYTE PTR [bp] diff --git a/gas/testsuite/gas/i386/x86-64-inval-pseudo.l b/gas/testsuite/gas/i386/x86-64-inval-pseudo.l new file mode 100644 index 0000000000..13ad0fb768 --- /dev/null +++ b/gas/testsuite/gas/i386/x86-64-inval-pseudo.l @@ -0,0 +1,10 @@ +.*: Assembler messages: +.*:2: Error: .* +.*:3: Error: .* +GAS LISTING .* + + +[ ]*1[ ]+\.text +[ ]*2[ ]+\{disp16\} movb \(%ebp\),%al +[ ]*3[ ]+\{disp16\} movb \(%rbp\),%al +#... diff --git a/gas/testsuite/gas/i386/x86-64-inval-pseudo.s b/gas/testsuite/gas/i386/x86-64-inval-pseudo.s new file mode 100644 index 0000000000..c10b14c209 --- /dev/null +++ b/gas/testsuite/gas/i386/x86-64-inval-pseudo.s @@ -0,0 +1,4 @@ + .text + {disp16} movb (%ebp),%al + {disp16} movb (%rbp),%al + .p2align 4,0 diff --git a/gas/testsuite/gas/i386/x86-64-pseudos.d b/gas/testsuite/gas/i386/x86-64-pseudos.d index 0fb18a3369..5d039dc6f9 100644 --- a/gas/testsuite/gas/i386/x86-64-pseudos.d +++ b/gas/testsuite/gas/i386/x86-64-pseudos.d @@ -22,6 +22,10 @@ Disassembly of section .text: +[a-f0-9]+: c5 f8 28 90 00 00 00 00 vmovaps 0x0\(%rax\),%xmm2 +[a-f0-9]+: 62 f1 7c 08 28 50 00 vmovaps 0x0\(%rax\),%xmm2 +[a-f0-9]+: 62 f1 7c 08 28 90 00 00 00 00 vmovaps 0x0\(%rax\),%xmm2 + +[a-f0-9]+: c5 f8 28 90 80 00 00 00 vmovaps 0x80\(%rax\),%xmm2 + +[a-f0-9]+: c5 f8 28 90 80 00 00 00 vmovaps 0x80\(%rax\),%xmm2 + +[a-f0-9]+: 62 f1 7c 08 28 50 08 vmovaps 0x80\(%rax\),%xmm2 + +[a-f0-9]+: 62 f1 7c 08 28 90 80 00 00 00 vmovaps 0x80\(%rax\),%xmm2 +[a-f0-9]+: 48 89 c8 mov %rcx,%rax +[a-f0-9]+: 48 8b c1 mov %rcx,%rax +[a-f0-9]+: 48 89 c8 mov %rcx,%rax @@ -304,7 +308,7 @@ Disassembly of section .text: +[a-f0-9]+: 40 d3 e0 rex shl %cl,%eax +[a-f0-9]+: 40 a0 01 00 00 00 00 00 00 00 rex movabs 0x1,%al +[a-f0-9]+: 40 38 ca rex cmp %cl,%dl - +[a-f0-9]+: 40 b3 01 rex mov \$(0x)?1,%bl + +[a-f0-9]+: 40 b3 01 rex mov \$(0x)1,%bl +[a-f0-9]+: f2 40 0f 38 f0 c1 rex crc32 %cl,%eax +[a-f0-9]+: 40 89 c3 rex mov %eax,%ebx +[a-f0-9]+: 41 89 c6 mov %eax,%r14d @@ -321,6 +325,12 @@ Disassembly of section .text: +[a-f0-9]+: 67 8a 45 00 mov 0x0\(%ebp\),%al +[a-f0-9]+: 67 8a 45 00 mov 0x0\(%ebp\),%al +[a-f0-9]+: 67 8a 85 00 00 00 00 mov 0x0\(%ebp\),%al + +[a-f0-9]+: 41 8a 45 00 mov 0x0\(%r13\),%al + +[a-f0-9]+: 41 8a 45 00 mov 0x0\(%r13\),%al + +[a-f0-9]+: 41 8a 85 00 00 00 00 mov 0x0\(%r13\),%al + +[a-f0-9]+: 67 41 8a 45 00 mov 0x0\(%r13d\),%al + +[a-f0-9]+: 67 41 8a 45 00 mov 0x0\(%r13d\),%al + +[a-f0-9]+: 67 41 8a 85 00 00 00 00 mov 0x0\(%r13d\),%al +[a-f0-9]+: c4 e1 78 28 d7 vmovaps %xmm7,%xmm2 +[a-f0-9]+: c4 e1 78 28 d7 vmovaps %xmm7,%xmm2 +[a-f0-9]+: c4 e1 78 29 fa vmovaps %xmm7,%xmm2 @@ -335,6 +345,10 @@ Disassembly of section .text: +[a-f0-9]+: c5 f8 28 90 00 00 00 00 vmovaps 0x0\(%rax\),%xmm2 +[a-f0-9]+: 62 f1 7c 08 28 50 00 vmovaps 0x0\(%rax\),%xmm2 +[a-f0-9]+: 62 f1 7c 08 28 90 00 00 00 00 vmovaps 0x0\(%rax\),%xmm2 + +[a-f0-9]+: c5 f8 28 90 80 00 00 00 vmovaps 0x80\(%rax\),%xmm2 + +[a-f0-9]+: c5 f8 28 90 80 00 00 00 vmovaps 0x80\(%rax\),%xmm2 + +[a-f0-9]+: 62 f1 7c 08 28 50 08 vmovaps 0x80\(%rax\),%xmm2 + +[a-f0-9]+: 62 f1 7c 08 28 90 80 00 00 00 vmovaps 0x80\(%rax\),%xmm2 +[a-f0-9]+: 48 89 c8 mov %rcx,%rax +[a-f0-9]+: 48 8b c1 mov %rcx,%rax +[a-f0-9]+: 48 89 c8 mov %rcx,%rax @@ -365,4 +379,10 @@ Disassembly of section .text: +[a-f0-9]+: 67 8a 45 00 mov 0x0\(%ebp\),%al +[a-f0-9]+: 67 8a 45 00 mov 0x0\(%ebp\),%al +[a-f0-9]+: 67 8a 85 00 00 00 00 mov 0x0\(%ebp\),%al + +[a-f0-9]+: 41 8a 45 00 mov 0x0\(%r13\),%al + +[a-f0-9]+: 41 8a 45 00 mov 0x0\(%r13\),%al + +[a-f0-9]+: 41 8a 85 00 00 00 00 mov 0x0\(%r13\),%al + +[a-f0-9]+: 41 8a 45 00 mov 0x0\(%r13\),%al + +[a-f0-9]+: 67 41 8a 45 00 mov 0x0\(%r13d\),%al + +[a-f0-9]+: 67 41 8a 85 00 00 00 00 mov 0x0\(%r13d\),%al #pass diff --git a/gas/testsuite/gas/i386/x86-64-pseudos.s b/gas/testsuite/gas/i386/x86-64-pseudos.s index 3b3638cf75..3818df9708 100644 --- a/gas/testsuite/gas/i386/x86-64-pseudos.s +++ b/gas/testsuite/gas/i386/x86-64-pseudos.s @@ -17,6 +17,11 @@ _start: {evex} {disp8} vmovaps (%rax),%xmm2 {evex} {disp32} vmovaps (%rax),%xmm2 + {vex} {disp8} vmovaps 128(%rax),%xmm2 + {vex} {disp32} vmovaps 128(%rax),%xmm2 + {evex} {disp8} vmovaps 128(%rax),%xmm2 + {evex} {disp32} vmovaps 128(%rax),%xmm2 + mov %rcx, %rax {load} mov %rcx, %rax {store} mov %rcx, %rax @@ -328,6 +333,14 @@ _start: {disp8} movb (%ebp),%al {disp32} movb (%ebp),%al + movb (%r13),%al + {disp8} movb (%r13),%al + {disp32} movb (%r13),%al + + movb (%r13d),%al + {disp8} movb (%r13d),%al + {disp32} movb (%r13d),%al + .intel_syntax noprefix {vex3} vmovaps xmm2,xmm7 {vex3} {load} vmovaps xmm2,xmm7 @@ -343,6 +356,12 @@ _start: {disp32} vmovaps xmm2,XMMWORD PTR [rax] {evex} {disp8} vmovaps xmm2,XMMWORD PTR [rax] {evex} {disp32} vmovaps xmm2,XMMWORD PTR [rax] + + {vex} {disp8} vmovaps xmm2,XMMWORD PTR [rax+128] + {vex} {disp32} vmovaps xmm2,XMMWORD PTR [rax+128] + {evex} {disp8} vmovaps xmm2,XMMWORD PTR [rax+128] + {evex} {disp32} vmovaps xmm2,XMMWORD PTR [rax+128] + mov rax,rcx {load} mov rax,rcx {store} mov rax,rcx @@ -375,3 +394,11 @@ _start: mov al, BYTE PTR [ebp] {disp8} mov al, BYTE PTR [ebp] {disp32} mov al, BYTE PTR [ebp] + + mov al, BYTE PTR [r13] + {disp8} mov al, BYTE PTR [r13] + {disp32} mov al, BYTE PTR [r13] + + mov al, BYTE PTR [r13] + {disp8} mov al, BYTE PTR [r13d] + {disp32} mov al, BYTE PTR [r13d] diff --git a/opcodes/i386-opc.h b/opcodes/i386-opc.h index b8a6dfc25c..09ee615db1 100644 --- a/opcodes/i386-opc.h +++ b/opcodes/i386-opc.h @@ -889,6 +889,18 @@ typedef struct insn_template #define Opcode_SIMD_FloatD 0x1 /* Direction bit for SIMD fp insns. */ #define Opcode_SIMD_IntD 0x10 /* Direction bit for SIMD int insns. */ +/* Pseudo prefixes. */ +#define Prefix_Disp8 0 /* {disp8} */ +#define Prefix_Disp16 1 /* {disp16} */ +#define Prefix_Disp32 2 /* {disp32} */ +#define Prefix_Load 3 /* {load} */ +#define Prefix_Store 4 /* {store} */ +#define Prefix_VEX 5 /* {vex} */ +#define Prefix_VEX3 6 /* {vex3} */ +#define Prefix_EVEX 7 /* {evex} */ +#define Prefix_REX 8 /* {rex} */ +#define Prefix_NoOptimize 9 /* {nooptimize} */ + /* extension_opcode is the 3 bit extension for group <n> insns. This field is also used to store the 8-bit opcode suffix for the AMD 3DNow! instructions. diff --git a/opcodes/i386-opc.tbl b/opcodes/i386-opc.tbl index bb7fb02dde..181d0df1ce 100644 --- a/opcodes/i386-opc.tbl +++ b/opcodes/i386-opc.tbl @@ -835,16 +835,17 @@ rex.wrxb, 0, 0x4f, None, 1, Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ld // Pseudo prefixes (opcode_length == 0) -{disp8}, 0, 0x0, None, 0, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsPrefix, { 0 } -{disp32}, 0, 0x1, None, 0, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsPrefix, { 0 } -{load}, 0, 0x2, None, 0, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsPrefix, { 0 } -{store}, 0, 0x3, None, 0, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsPrefix, { 0 } -{vex}, 0, 0x4, None, 0, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsPrefix, { 0 } -{vex2}, 0, 0x4, None, 0, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsPrefix, { 0 } -{vex3}, 0, 0x5, None, 0, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsPrefix, { 0 } -{evex}, 0, 0x6, None, 0, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsPrefix, { 0 } -{rex}, 0, 0x7, None, 0, Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsPrefix, { 0 } -{nooptimize}, 0, 0x8, None, 0, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsPrefix, { 0 } +{disp8}, 0, Prefix_Disp8, None, 0, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsPrefix, { 0 } +{disp16}, 0, Prefix_Disp16, None, 0, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsPrefix, { 0 } +{disp32}, 0, Prefix_Disp32, None, 0, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsPrefix, { 0 } +{load}, 0, Prefix_Load, None, 0, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsPrefix, { 0 } +{store}, 0, Prefix_Store, None, 0, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsPrefix, { 0 } +{vex}, 0, Prefix_VEX, None, 0, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsPrefix, { 0 } +{vex2}, 0, Prefix_VEX, None, 0, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsPrefix, { 0 } +{vex3}, 0, Prefix_VEX3, None, 0, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsPrefix, { 0 } +{evex}, 0, Prefix_EVEX, None, 0, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsPrefix, { 0 } +{rex}, 0, Prefix_REX, None, 0, Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsPrefix, { 0 } +{nooptimize}, 0, Prefix_NoOptimize, None, 0, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsPrefix, { 0 } // 486 extensions. diff --git a/opcodes/i386-tbl.h b/opcodes/i386-tbl.h index a3aa69175a..413c730f86 100644 --- a/opcodes/i386-tbl.h +++ b/opcodes/i386-tbl.h @@ -7584,7 +7584,7 @@ const insn_template i386_optab[] = 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } } }, - { "{disp8}", 0x0, None, 0, 0, + { "{disp8}", 0, None, 0, 0, { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, @@ -7596,7 +7596,7 @@ const insn_template i386_optab[] = 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } } }, - { "{disp32}", 0x1, None, 0, 0, + { "{disp16}", 1, None, 0, 0, { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, @@ -7608,7 +7608,7 @@ const insn_template i386_optab[] = 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } } }, - { "{load}", 0x2, None, 0, 0, + { "{disp32}", 2, None, 0, 0, { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, @@ -7620,7 +7620,7 @@ const insn_template i386_optab[] = 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } } }, - { "{store}", 0x3, None, 0, 0, + { "{load}", 3, None, 0, 0, { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, @@ -7632,7 +7632,7 @@ const insn_template i386_optab[] = 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } } }, - { "{vex}", 0x4, None, 0, 0, + { "{store}", 4, None, 0, 0, { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, @@ -7644,7 +7644,7 @@ const insn_template i386_optab[] = 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } } }, - { "{vex2}", 0x4, None, 0, 0, + { "{vex}", 5, None, 0, 0, { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, @@ -7656,7 +7656,7 @@ const insn_template i386_optab[] = 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } } }, - { "{vex3}", 0x5, None, 0, 0, + { "{vex2}", 5, None, 0, 0, { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, @@ -7668,7 +7668,7 @@ const insn_template i386_optab[] = 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } } }, - { "{evex}", 0x6, None, 0, 0, + { "{vex3}", 6, None, 0, 0, { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, @@ -7680,7 +7680,19 @@ const insn_template i386_optab[] = 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } } }, - { "{rex}", 0x7, None, 0, 0, + { "{evex}", 7, None, 0, 0, + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, + { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, + { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0 } } } }, + { "{rex}", 8, None, 0, 0, { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, @@ -7692,7 +7704,7 @@ const insn_template i386_optab[] = 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } } }, - { "{nooptimize}", 0x8, None, 0, 0, + { "{nooptimize}", 9, None, 0, 0, { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, -- 2.26.2 ^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: V2 [PATCH] x86: Add {disp16} pseudo prefix 2020-07-29 23:39 ` V2 " H.J. Lu @ 2020-07-31 7:03 ` Jan Beulich 2020-07-31 11:52 ` H.J. Lu 2020-08-04 12:36 ` H.J. Lu 1 sibling, 1 reply; 15+ messages in thread From: Jan Beulich @ 2020-07-31 7:03 UTC (permalink / raw) To: H.J. Lu; +Cc: Binutils On 30.07.2020 01:39, H.J. Lu wrote: > Here is the updated patch. Just one more thing: Wouldn't it make sense to mark {disp16} CpuNo64, at least as long as it's not usable for controlling branch displacements (which, as said, I think it shouldn't get enabled for)? Jan ^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: V2 [PATCH] x86: Add {disp16} pseudo prefix 2020-07-31 7:03 ` Jan Beulich @ 2020-07-31 11:52 ` H.J. Lu 2020-07-31 12:28 ` Jan Beulich 0 siblings, 1 reply; 15+ messages in thread From: H.J. Lu @ 2020-07-31 11:52 UTC (permalink / raw) To: Jan Beulich; +Cc: Binutils On Fri, Jul 31, 2020 at 12:03 AM Jan Beulich <jbeulich@suse.com> wrote: > > On 30.07.2020 01:39, H.J. Lu wrote: > > Here is the updated patch. > > Just one more thing: Wouldn't it make sense to mark {disp16} CpuNo64, > at least as long as it's not usable for controlling branch displacements > (which, as said, I think it shouldn't get enabled for)? Since {disp16} can only be used for memory reference in 16-bit mode, CpuNo64 isn't appropriate here. -- H.J. ^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: V2 [PATCH] x86: Add {disp16} pseudo prefix 2020-07-31 11:52 ` H.J. Lu @ 2020-07-31 12:28 ` Jan Beulich 2020-07-31 12:34 ` H.J. Lu 0 siblings, 1 reply; 15+ messages in thread From: Jan Beulich @ 2020-07-31 12:28 UTC (permalink / raw) To: H.J. Lu; +Cc: Binutils On 31.07.2020 13:52, H.J. Lu wrote: > On Fri, Jul 31, 2020 at 12:03 AM Jan Beulich <jbeulich@suse.com> wrote: >> >> On 30.07.2020 01:39, H.J. Lu wrote: >>> Here is the updated patch. >> >> Just one more thing: Wouldn't it make sense to mark {disp16} CpuNo64, >> at least as long as it's not usable for controlling branch displacements >> (which, as said, I think it shouldn't get enabled for)? > > Since {disp16} can only be used for memory reference in 16-bit mode, > CpuNo64 isn't appropriate here. Wouldn't the diagnostic be more to the point? (The prefix isn't limited to 16-bit mode, but to 16-bit addressing, which can also be used from 32-bit mode, but not from 64-bit mode.) Jan ^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: V2 [PATCH] x86: Add {disp16} pseudo prefix 2020-07-31 12:28 ` Jan Beulich @ 2020-07-31 12:34 ` H.J. Lu 0 siblings, 0 replies; 15+ messages in thread From: H.J. Lu @ 2020-07-31 12:34 UTC (permalink / raw) To: Jan Beulich; +Cc: Binutils On Fri, Jul 31, 2020 at 5:28 AM Jan Beulich <jbeulich@suse.com> wrote: > > On 31.07.2020 13:52, H.J. Lu wrote: > > On Fri, Jul 31, 2020 at 12:03 AM Jan Beulich <jbeulich@suse.com> wrote: > >> > >> On 30.07.2020 01:39, H.J. Lu wrote: > >>> Here is the updated patch. > >> > >> Just one more thing: Wouldn't it make sense to mark {disp16} CpuNo64, > >> at least as long as it's not usable for controlling branch displacements > >> (which, as said, I think it shouldn't get enabled for)? > > > > Since {disp16} can only be used for memory reference in 16-bit mode, > > CpuNo64 isn't appropriate here. > > Wouldn't the diagnostic be more to the point? (The prefix isn't limited > to 16-bit mode, but to 16-bit addressing, which can also be used from > 32-bit mode, but not from 64-bit mode.) It is checked with /* 32-bit/64-bit checks. */ if (i.disp_encoding == disp_encoding_16bit) { bad_disp: as_bad (_("invalid `%s' prefix"), addr_mode == CODE_16BIT ? "{disp32}" : "{disp16}"); return 0; } and testcases are added. -- H.J. ^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: V2 [PATCH] x86: Add {disp16} pseudo prefix 2020-07-29 23:39 ` V2 " H.J. Lu 2020-07-31 7:03 ` Jan Beulich @ 2020-08-04 12:36 ` H.J. Lu 1 sibling, 0 replies; 15+ messages in thread From: H.J. Lu @ 2020-08-04 12:36 UTC (permalink / raw) To: Jan Beulich, Nick Clifton; +Cc: Binutils On Wed, Jul 29, 2020 at 4:39 PM H.J. Lu <hjl.tools@gmail.com> wrote: > > On Wed, Jul 29, 2020 at 3:53 PM H.J. Lu <hjl.tools@gmail.com> wrote: > > > > On Wed, Jul 29, 2020 at 1:26 PM Jan Beulich <jbeulich@suse.com> wrote: > > > > > > On 28.07.2020 22:30, H.J. Lu wrote: > > > > On Tue, Jul 28, 2020 at 12:02 PM H.J. Lu <hjl.tools@gmail.com> wrote: > > > >> > > > >> On Tue, Jul 28, 2020 at 11:43 AM Jan Beulich <jbeulich@suse.com> wrote: > > > >>> > > > >>> On 28.07.2020 01:23, H.J. Lu via Binutils wrote: > > > >>>> Since (%bp)/(%ebp)/(%rbp) are encoded as 0(%bp)/0(%ebp)/0(%rbp), use > > > >>>> disp32/disp16 on 0(%bp)/0(%ebp)/0(%rbp) for {disp32}. > > > >>> > > > >>> Same for (%r13d) / (%r13) afaict? > > > >> > > > >> Yes. {disp32} works on (%r13d) / (%r13) now: > > > >> > > > >> [hjl@gnu-cfl-2 testsuite]$ cat x.s > > > >> movb (%r13),%al > > > >> {disp8} movb (%r13),%al > > > >> {disp32} movb (%r13),%al > > > >> > > > >> movb (%r13d),%al > > > >> {disp8} movb (%r13d),%al > > > >> {disp32} movb (%r13d),%al > > > >> [hjl@gnu-cfl-2 testsuite]$ gcc -c x.s > > > >> [hjl@gnu-cfl-2 testsuite]$ objdump -dw x.o > > > >> > > > >> x.o: file format elf64-x86-64 > > > >> > > > >> > > > >> Disassembly of section .text: > > > >> > > > >> 0000000000000000 <.text>: > > > >> 0: 41 8a 45 00 mov 0x0(%r13),%al > > > >> 4: 41 8a 45 00 mov 0x0(%r13),%al > > > >> 8: 41 8a 45 00 mov 0x0(%r13),%al > > > >> c: 67 41 8a 45 00 mov 0x0(%r13d),%al > > > >> 11: 67 41 8a 45 00 mov 0x0(%r13d),%al > > > >> 16: 67 41 8a 45 00 mov 0x0(%r13d),%al > > > >> [hjl@gnu-cfl-2 testsuite]$ ../as-new -o x.o x.s > > > >> [hjl@gnu-cfl-2 testsuite]$ objdump -dw x.o > > > >> > > > >> x.o: file format elf64-x86-64 > > > >> > > > >> > > > >> Disassembly of section .text: > > > >> > > > >> 0000000000000000 <.text>: > > > >> 0: 41 8a 45 00 mov 0x0(%r13),%al > > > >> 4: 41 8a 45 00 mov 0x0(%r13),%al > > > >> 8: 41 8a 85 00 00 00 00 mov 0x0(%r13),%al > > > >> f: 67 41 8a 45 00 mov 0x0(%r13d),%al > > > >> 14: 67 41 8a 45 00 mov 0x0(%r13d),%al > > > >> 19: 67 41 8a 85 00 00 00 00 mov 0x0(%r13d),%al > > > >> [hjl@gnu-cfl-2 testsuite]$ > > > >> > > > >> > > > >>>> Note: Since there is no disp32 on 0(%bp), use disp16 instead. > > > >>> > > > >>> What use is it to fix the special case of (%bp) when the more general > > > >>> case ((%bx), (%si), etc) doesn't work? I anyway think that instead of > > > >>> ... > > > >>> > > > >>>> --- a/gas/config/tc-i386.c > > > >>>> +++ b/gas/config/tc-i386.c > > > >>>> @@ -8151,7 +8151,12 @@ build_modrm_byte (void) > > > >>>> if (operand_type_check (i.types[op], disp) == 0) > > > >>>> { > > > >>>> /* fake (%bp) into 0(%bp) */ > > > >>>> - i.types[op].bitfield.disp8 = 1; > > > >>>> + if (i.disp_encoding == disp_encoding_32bit) > > > >>>> + /* NB: Use disp16 since there is no disp32 > > > >>>> + in 16-bit mode. */ > > > >>>> + i.types[op].bitfield.disp16 = 1; > > > >>>> + else > > > >>>> + i.types[op].bitfield.disp8 = 1; > > > >>>> fake_zero_displacement = 1; > > > >>>> } > > > >>> > > > >>> ... the comment you add here, support for {disp16} should be added. > > > >>> > > > >> > > > >> I will add {disp16} to master branch. > > > >> > > > > > > > > Add {disp16} pseudo prefix and replace {disp32} pseudo prefix with > > > > {disp16} in 16-bit mode test. Check invalid {disp16}/{disp32} pseudo > > > > prefixes. > > > > > > The inval-pseudo test is a 32-bit one; you shouldn't use .code64 there, > > > or you'll cause FAILs on 32-bit only builds. > > > > I will fix it. > > > > > > Note: {disp16} can be also used on branches in 32-bit mode. > > > > > > But you don't add any tests to this effect, so it's hard to see what > > > exactly this means. To be honest I'm not sure this is helpful: A means > > > to widen the default displacement may be useful, but one to narrow not > > > just the displacement, but also the resulting new IP? > > > > {disp16} can be used to generate "branch rel16". But implementation > > may be non-trivial. > > > > > I was also wanting to ask that you group the new pseudo prefix with > > > its sibling ones in the opcode table, but I realize the use of > > > hard coded numbers makes this cumbersome. Time to do away with that? > > > > I will take a look. > > > > > I also have a tangential question: Shouldn't e.g. > > > > > > {disp8} vmovaps %xmm0,128(%eax) > > > > > > be taken as a request to use EVEX encoding, to satisfy the pseudo > > > prefix? Unless {vex} was also specified, at which point things > > > become "interesting" (but the way they're documented I think > > > {vex} has to have more wight here). > > > > > > > {disp8} is a hint for VEX. It shouldn't change to EVEX. > > > > Here is the updated patch. > > -- > H.J. I am backporting it to 2.35 branch. -- H.J. ^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH] x86: Add {disp16} pseudo prefix 2020-07-29 22:53 ` H.J. Lu 2020-07-29 23:39 ` V2 " H.J. Lu @ 2020-07-31 6:22 ` Jan Beulich 2020-07-31 11:44 ` H.J. Lu 1 sibling, 1 reply; 15+ messages in thread From: Jan Beulich @ 2020-07-31 6:22 UTC (permalink / raw) To: H.J. Lu; +Cc: Binutils On 30.07.2020 00:53, H.J. Lu wrote: > On Wed, Jul 29, 2020 at 1:26 PM Jan Beulich <jbeulich@suse.com> wrote: >> On 28.07.2020 22:30, H.J. Lu wrote: >>> Note: {disp16} can be also used on branches in 32-bit mode. >> >> But you don't add any tests to this effect, so it's hard to see what >> exactly this means. To be honest I'm not sure this is helpful: A means >> to widen the default displacement may be useful, but one to narrow not >> just the displacement, but also the resulting new IP? > > {disp16} can be used to generate "branch rel16". But implementation > may be non-trivial. Oh, so you mean it could be used in principle, not that it now can be used right with the introduction of the new pseudo prefix? If so, I simply misunderstood your use of "can", sorry. Jan ^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH] x86: Add {disp16} pseudo prefix 2020-07-31 6:22 ` Jan Beulich @ 2020-07-31 11:44 ` H.J. Lu 0 siblings, 0 replies; 15+ messages in thread From: H.J. Lu @ 2020-07-31 11:44 UTC (permalink / raw) To: Jan Beulich; +Cc: Binutils On Thu, Jul 30, 2020 at 11:22 PM Jan Beulich <jbeulich@suse.com> wrote: > > On 30.07.2020 00:53, H.J. Lu wrote: > > On Wed, Jul 29, 2020 at 1:26 PM Jan Beulich <jbeulich@suse.com> wrote: > >> On 28.07.2020 22:30, H.J. Lu wrote: > >>> Note: {disp16} can be also used on branches in 32-bit mode. > >> > >> But you don't add any tests to this effect, so it's hard to see what > >> exactly this means. To be honest I'm not sure this is helpful: A means > >> to widen the default displacement may be useful, but one to narrow not > >> just the displacement, but also the resulting new IP? > > > > {disp16} can be used to generate "branch rel16". But implementation > > may be non-trivial. > > Oh, so you mean it could be used in principle, not that it now > can be used right with the introduction of the new pseudo > prefix? If so, I simply misunderstood your use of "can", sorry. > Yes. -- H.J. ^ permalink raw reply [flat|nested] 15+ messages in thread
end of thread, other threads:[~2020-08-04 12:37 UTC | newest]
Thread overview: 15+ messages (download: mbox.gz / follow: Atom feed)
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2020-07-27 23:23 [PATCH] x86: Handle {disp32} for (%bp)/(%ebp)/(%rbp) H.J. Lu
2020-07-28 10:39 ` H.J. Lu
2020-07-28 18:43 ` Jan Beulich
2020-07-28 19:02 ` H.J. Lu
2020-07-28 20:30 ` [PATCH] x86: Add {disp16} pseudo prefix H.J. Lu
2020-07-29 20:26 ` Jan Beulich
2020-07-29 22:53 ` H.J. Lu
2020-07-29 23:39 ` V2 " H.J. Lu
2020-07-31 7:03 ` Jan Beulich
2020-07-31 11:52 ` H.J. Lu
2020-07-31 12:28 ` Jan Beulich
2020-07-31 12:34 ` H.J. Lu
2020-08-04 12:36 ` H.J. Lu
2020-07-31 6:22 ` Jan Beulich
2020-07-31 11:44 ` H.J. Lu
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