Re: [PATCH 5/5][BINUTILS] aarch64: Add support for VMSA feature enhancements.

[Jan Beulich <jbeulich@suse.com>]

On 16.11.2023 12:39, Srinath Parvathaneni wrote:
> This patch adds the permission model enhancement and memory
> attribute index enhancement features and their corresponding
> system registers in AArch64 assembler.
> Permission Indirection Extension (FEAT_S1PIE, FEAT_S2PIE)
> Permission Overlay Extension (FEAT_S1POE, FEAT_S2POE)
> Memory Attribute Index Enhancement (FEAT_AIE)
> Extension to Translation Control Registers (FEAT_TCR2)

With the public documentation not (yet) mentioning these registers
(and you also not providing references to, perhaps, incremental
documentation which is going to be folded into the ARM), it's
pretty hard to judge whether what might look like a typo actually
is one. In particular in

@@ -556,6 +560,10 @@
   SYSREG ("mair_el12",		CPENC (3,5,10,2,0),	F_ARCHEXT,		AARCH64_FEATURE (V8_1A))
   SYSREG ("mair_el2",		CPENC (3,4,10,2,0),	0,			AARCH64_NO_FEATURES)
   SYSREG ("mair_el3",		CPENC (3,6,10,2,0),	0,			AARCH64_NO_FEATURES)
+  SYSREG ("mair2_el1",		CPENC (3,0,10,2,1),	F_ARCHEXT,		AARCH64_FEATURE (AIE))
+  SYSREG ("mair2_el12",		CPENC (3,5,10,2,1),	F_ARCHEXT,		AARCH64_FEATURE (AIE))
+  SYSREG ("mair2_el2",		CPENC (3,4,10,1,1),	F_ARCHEXT,		AARCH64_FEATURE (AIE))
+  SYSREG ("mair2_el3",		CPENC (3,6,10,1,1),	F_ARCHEXT,		AARCH64_FEATURE (AIE))

the EL2 and EL3 values using 1s where the EL1 and EL12 values use 2s
looks somewhat suspicious. No similar inconsistency exists for AMAIR2,
for example.

Jan