* [PATCH] MIPS/GAS/testsuite: Fine-grained MIPS FP ISA matching
@ 2011-08-09 23:07 Maciej W. Rozycki
2011-08-10 8:27 ` Richard Sandiford
0 siblings, 1 reply; 7+ messages in thread
From: Maciej W. Rozycki @ 2011-08-09 23:07 UTC (permalink / raw)
To: binutils; +Cc: Richard Sandiford
Hi,
While merging test suite changes I've noticed some recent 24K erratum
workaround cases have suboptimal coverage. Upon further investigation I
discovered we have no proper mechanism to depend on for FP ISA revisions
in multi-architecture tests. Therefore I decided to make one up.
The MIPS FP ISA evolved a bit differently to the integer ISA and the
dependencies are (roughly) as follows -- as far as the instruction set is
concerned:
1. MIPS I -- base FP instruction set (MIPS I FP ISA).
2. MIPS II -- 64-bit FP memory transfers, 32-bit fixed-point FP
instructions added (MIPS II FP ISA).
3. MIPS III -- 64-bit fixed-point FP instructions added (MIPS III FP ISA).
4. MIPS IV -- indexed FP memory transfers, FP multiply-accumulate,
reciprocal and conditional-move instructions added (MIPS IV
FP ISA).
5. MIPS V -- unaligned indexed FP memory transfers, paired-single FP
instructions added (MIPS V FP ISA).
Then MIPS architecture processors defined their FP ISAs as follows:
1. MIPS32 -- MIPS II FP ISA plus FP conditional-move instructions.
2. MIPS64 -- MIPS V FP ISA.
3. MIPS32r2 -- MIPS V FP ISA plus upper-half FP register transfers.
4. MIPS64r2 -- MIPS V FP ISA plus upper-half FP register transfers.
Therefore I propose to add a set of FP ISA properties as follows to let
test cases that include MIPS III, MIPS IV or MIPS V FP ISA instructions to
have better coverage. The change is imperfect as it doesn't cover MIPS32
ISA FP conditional-move instructions, but I think it is good enough
anyway, especially as I'm told original (r1) MIPS32 FP parts have never
been made. If someone needs to test such a combination, then they may
propose a further property to cover it (like with "ror", etc.).
With these bits in place, the change now extends the 24K erratum
workaround coverage to some older ISAs too. Ultimately, I think these
cases should be passed through microMIPS testing too, to make sure the
workaround is correctly disabled when assembling microMIPS code (there are
no 24K parts supporting the microMIPS ASE).
Comments?
2011-08-09 Maciej W. Rozycki <macro@codesourcery.com>
gas/testsuite/
* gas/mips/mips.exp: Define new "fpisa3", "fpisa4" and "fpisa5"
architecture properties adding them to "mips3", "mips4", "mips5"
and "mips32r2" architectures. Run the "24k-triple-stores-1"
test for "fpisa5" instead of "mips32r2". Run the
"24k-triple-stores-3" test for "mips2" instead of "mips3".
Maciej
binutils-24k-test-mips3.diff
Index: binutils-fsf-trunk-quilt/gas/testsuite/gas/mips/mips.exp
===================================================================
--- binutils-fsf-trunk-quilt.orig/gas/testsuite/gas/mips/mips.exp 2011-08-09 00:57:25.000000000 +0100
+++ binutils-fsf-trunk-quilt/gas/testsuite/gas/mips/mips.exp 2011-08-09 23:08:44.000000000 +0100
@@ -55,6 +55,10 @@
# The architecture includes the instructions defined
# by that MIPS ISA.
#
+# fpisa3, fpisa4, fpisa5
+# The architecture includes the floating-point
+# instructions defined by that MIPS ISA.
+#
# gpr_ilocks
# The architecture interlocks GPRs accesses. (That is,
# there are no load delay slots.)
@@ -369,16 +373,16 @@ mips_arch_create mips1 32 {} {} \
{ -march=mips1 -mtune=mips1 } { -mmips:3000 }
mips_arch_create mips2 32 mips1 { gpr_ilocks } \
{ -march=mips2 -mtune=mips2 } { -mmips:6000 }
-mips_arch_create mips3 64 mips2 {} \
+mips_arch_create mips3 64 mips2 { fpisa3 } \
{ -march=mips3 -mtune=mips3 } { -mmips:4000 }
-mips_arch_create mips4 64 mips3 {} \
+mips_arch_create mips4 64 mips3 { fpisa4 } \
{ -march=mips4 -mtune=mips4 } { -mmips:8000 }
-mips_arch_create mips5 64 mips4 {} \
+mips_arch_create mips5 64 mips4 { fpisa5 } \
{ -march=mips5 -mtune=mips5 } { -mmips:mips5 }
mips_arch_create mips32 32 mips2 {} \
{ -march=mips32 -mtune=mips32 } { -mmips:isa32 } \
{ mipsisa32-*-* mipsisa32el-*-* }
-mips_arch_create mips32r2 32 mips32 { ror } \
+mips_arch_create mips32r2 32 mips32 { fpisa3 fpisa4 fpisa5 ror } \
{ -march=mips32r2 -mtune=mips32r2 } \
{ -mmips:isa32r2 } \
{ mipsisa32r2-*-* mipsisa32r2el-*-* }
@@ -492,11 +496,11 @@ if { [istarget mips*-*-vxworks*] } {
run_dump_test_arches "24k-branch-delay-1" \
[mips_arch_list_matching mips1 !micromips]
run_dump_test_arches "24k-triple-stores-1" \
- [mips_arch_list_matching mips32r2 !octeon !micromips]
+ [mips_arch_list_matching fpisa5 !octeon !micromips]
run_dump_test_arches "24k-triple-stores-2" \
[mips_arch_list_matching mips2 !micromips]
run_dump_test_arches "24k-triple-stores-3" \
- [mips_arch_list_matching mips3 !micromips]
+ [mips_arch_list_matching mips2 !micromips]
run_dump_test_arches "24k-triple-stores-4" \
[mips_arch_list_matching mips2 !micromips]
run_dump_test_arches "24k-triple-stores-5" \
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH] MIPS/GAS/testsuite: Fine-grained MIPS FP ISA matching
2011-08-09 23:07 [PATCH] MIPS/GAS/testsuite: Fine-grained MIPS FP ISA matching Maciej W. Rozycki
@ 2011-08-10 8:27 ` Richard Sandiford
2011-08-10 16:12 ` Maciej W. Rozycki
0 siblings, 1 reply; 7+ messages in thread
From: Richard Sandiford @ 2011-08-10 8:27 UTC (permalink / raw)
To: Maciej W. Rozycki; +Cc: binutils
"Maciej W. Rozycki" <macro@codesourcery.com> writes:
> While merging test suite changes I've noticed some recent 24K erratum
> workaround cases have suboptimal coverage. Upon further investigation I
> discovered we have no proper mechanism to depend on for FP ISA revisions
> in multi-architecture tests. Therefore I decided to make one up.
Well, to put it into perspective, the only change you make related to
the "FP ISA" is to run a single 24k test for ISAs that are incompatible
with the 24k. Of all the things we need more test coverage for,
that has to be way down the list.
But, patch is OK I guess.
Richard
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH] MIPS/GAS/testsuite: Fine-grained MIPS FP ISA matching
2011-08-10 8:27 ` Richard Sandiford
@ 2011-08-10 16:12 ` Maciej W. Rozycki
2011-08-10 17:12 ` Richard Sandiford
0 siblings, 1 reply; 7+ messages in thread
From: Maciej W. Rozycki @ 2011-08-10 16:12 UTC (permalink / raw)
To: Richard Sandiford; +Cc: binutils
On Wed, 10 Aug 2011, Richard Sandiford wrote:
> > While merging test suite changes I've noticed some recent 24K erratum
> > workaround cases have suboptimal coverage. Upon further investigation I
> > discovered we have no proper mechanism to depend on for FP ISA revisions
> > in multi-architecture tests. Therefore I decided to make one up.
>
> Well, to put it into perspective, the only change you make related to
> the "FP ISA" is to run a single 24k test for ISAs that are incompatible
> with the 24k. Of all the things we need more test coverage for,
> that has to be way down the list.
;) If anyhow at all I decided to do it properly.
But you're right in principle and I have now skimmed over the tests we
run and adjusted these I remembered to be qualifying too. Below is the
result. There may be more candidates, especially with some cases we don't
currently run across multiple subarchitectures. This is good enough for
now though, I think. I've checked it does the right thing.
> But, patch is OK I guess.
Thanks for the review. I think it will make sense if I merge the two
changes into one and commit them together. Do you agree?
2011-08-10 Maciej W. Rozycki <macro@codesourcery.com>
gas/testsuite/
* gas/mips/mips.exp: Define new "fpisa3", "fpisa4" and "fpisa5"
architecture properties adding them to "mips3", "mips4", "mips5"
and "mips32r2" architectures. Use the new properties for the
"24k-triple-stores-1", "24k-triple-stores-3", "mips4-fp",
"mips5" and "alnv_ps-swap" tests.
Maciej
binutils-test-fpisa.diff
Index: binutils-fsf-trunk-quilt/gas/testsuite/gas/mips/mips.exp
===================================================================
--- binutils-fsf-trunk-quilt.orig/gas/testsuite/gas/mips/mips.exp 2011-08-10 15:48:49.000000000 +0100
+++ binutils-fsf-trunk-quilt/gas/testsuite/gas/mips/mips.exp 2011-08-10 15:51:58.000000000 +0100
@@ -627,14 +627,14 @@ if { [istarget mips*-*-vxworks*] } {
if $elf { run_dump_test "lif-svr4pic" }
if $elf { run_dump_test "lif-xgot" }
run_dump_test_arches "mips4" [mips_arch_list_matching mips4]
- run_dump_test_arches "mips4-fp" [mips_arch_list_matching mips4]
+ run_dump_test_arches "mips4-fp" [mips_arch_list_matching fpisa4]
run_list_test_arches "mips4-fp" "-32 -msoft-float" \
- [mips_arch_list_matching mips4]
+ [mips_arch_list_matching fpisa4]
run_dump_test_arches "mips4-branch-likely" \
[mips_arch_list_matching mips4]
run_list_test_arches "mips4-branch-likely" "-32 -msoft-float" \
[mips_arch_list_matching mips4]
- run_dump_test_arches "mips5" [mips_arch_list_matching mips5]
+ run_dump_test_arches "mips5" [mips_arch_list_matching fpisa5]
run_dump_test "mul"
run_dump_test_arches "rol" [mips_arch_list_matching mips1 !ror]
@@ -1030,9 +1030,7 @@ if { [istarget mips*-*-vxworks*] } {
run_dump_test "mips32-sync"
run_dump_test_arches "mips32r2-sync" \
[mips_arch_list_matching mips32r2]
- run_dump_test_arches "alnv_ps-swap" [lsort -dictionary -unique [concat \
- [mips_arch_list_matching mips5] \
- [mips_arch_list_matching mips32r2] ] ]
+ run_dump_test_arches "alnv_ps-swap" [mips_arch_list_matching fpisa5]
run_dump_test_arches "cache" [lsort -dictionary -unique [concat \
[mips_arch_list_matching mips3] \
[mips_arch_list_matching mips32] ] ]
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH] MIPS/GAS/testsuite: Fine-grained MIPS FP ISA matching
2011-08-10 16:12 ` Maciej W. Rozycki
@ 2011-08-10 17:12 ` Richard Sandiford
2011-08-10 17:35 ` Maciej W. Rozycki
0 siblings, 1 reply; 7+ messages in thread
From: Richard Sandiford @ 2011-08-10 17:12 UTC (permalink / raw)
To: Maciej W. Rozycki; +Cc: binutils
"Maciej W. Rozycki" <macro@codesourcery.com> writes:
> But you're right in principle and I have now skimmed over the tests we
> run and adjusted these I remembered to be qualifying too. Below is the
> result. There may be more candidates, especially with some cases we don't
> currently run across multiple subarchitectures. This is good enough for
> now though, I think. I've checked it does the right thing.
Ah, OK, with this patch it is indeed more convincing.
> Thanks for the review. I think it will make sense if I merge the two
> changes into one and commit them together. Do you agree?
Yes.
> 2011-08-10 Maciej W. Rozycki <macro@codesourcery.com>
>
> gas/testsuite/
> * gas/mips/mips.exp: Define new "fpisa3", "fpisa4" and "fpisa5"
> architecture properties adding them to "mips3", "mips4", "mips5"
> and "mips32r2" architectures. Use the new properties for the
> "24k-triple-stores-1", "24k-triple-stores-3", "mips4-fp",
> "mips5" and "alnv_ps-swap" tests.
OK, but...
> - run_dump_test_arches "mips5" [mips_arch_list_matching mips5]
> + run_dump_test_arches "mips5" [mips_arch_list_matching fpisa5]
...please also rename mips5 to mips5-fp (as part of the same commit
or separately, whichever you prefer).
Richard
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH] MIPS/GAS/testsuite: Fine-grained MIPS FP ISA matching
2011-08-10 17:12 ` Richard Sandiford
@ 2011-08-10 17:35 ` Maciej W. Rozycki
2011-08-10 19:10 ` Richard Sandiford
0 siblings, 1 reply; 7+ messages in thread
From: Maciej W. Rozycki @ 2011-08-10 17:35 UTC (permalink / raw)
To: Richard Sandiford; +Cc: binutils
On Wed, 10 Aug 2011, Richard Sandiford wrote:
> > - run_dump_test_arches "mips5" [mips_arch_list_matching mips5]
> > + run_dump_test_arches "mips5" [mips_arch_list_matching fpisa5]
>
> ...please also rename mips5 to mips5-fp (as part of the same commit
> or separately, whichever you prefer).
Are you sure that is needed? Please note that the MIPS V ISA only added
FP instructions (and, for the record, to the best of my knowledge there
was no actual implementation ever). So semantically both names are
correct -- the case covers both MIPS V FP ISA additions and all the MIPS V
ISA additions at the same time.
Maciej
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH] MIPS/GAS/testsuite: Fine-grained MIPS FP ISA matching
2011-08-10 17:35 ` Maciej W. Rozycki
@ 2011-08-10 19:10 ` Richard Sandiford
2011-08-10 22:52 ` Maciej W. Rozycki
0 siblings, 1 reply; 7+ messages in thread
From: Richard Sandiford @ 2011-08-10 19:10 UTC (permalink / raw)
To: Maciej W. Rozycki; +Cc: binutils
"Maciej W. Rozycki" <macro@codesourcery.com> writes:
> On Wed, 10 Aug 2011, Richard Sandiford wrote:
>
>> > - run_dump_test_arches "mips5" [mips_arch_list_matching mips5]
>> > + run_dump_test_arches "mips5" [mips_arch_list_matching fpisa5]
>>
>> ...please also rename mips5 to mips5-fp (as part of the same commit
>> or separately, whichever you prefer).
>
> Are you sure that is needed?
The name of the test should be consistent with the condition. I asked
because I wanted the mips5 test to be consistent with mips4-fp. So yes,
please do rename.
> Please note that the MIPS V ISA only added FP instructions
Sure, I realise that.
Richard
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH] MIPS/GAS/testsuite: Fine-grained MIPS FP ISA matching
2011-08-10 19:10 ` Richard Sandiford
@ 2011-08-10 22:52 ` Maciej W. Rozycki
0 siblings, 0 replies; 7+ messages in thread
From: Maciej W. Rozycki @ 2011-08-10 22:52 UTC (permalink / raw)
To: Richard Sandiford; +Cc: binutils
On Wed, 10 Aug 2011, Richard Sandiford wrote:
> >> > - run_dump_test_arches "mips5" [mips_arch_list_matching mips5]
> >> > + run_dump_test_arches "mips5" [mips_arch_list_matching fpisa5]
> >>
> >> ...please also rename mips5 to mips5-fp (as part of the same commit
> >> or separately, whichever you prefer).
> >
> > Are you sure that is needed?
>
> The name of the test should be consistent with the condition. I asked
> because I wanted the mips5 test to be consistent with mips4-fp. So yes,
> please do rename.
Sounds like syntactic sugar to me and due to limitations of CVS we're
losing file history across the rename. Also doing this together with the
other changes would be mere obfuscation, so here's what I committed,
separately. I have refrained from updating test case descriptions though
in these circumstances I think they should be made consistent between
mips4-fp and mips5-fp. It's up to you -- I can't afford any more effort
for this cleanup, sorry.
2011-08-10 Maciej W. Rozycki <macro@codesourcery.com>
gas/testsuite/
* gas/mips/micromips@mips5.d: Rename to...
* gas/mips/micromips@mips5-fp.d: ... this.
* gas/mips/mips5.d: Rename to...
* gas/mips/mips5-fp.d: ... this.
* gas/mips/mips5.l: Rename to...
* gas/mips/mips5-fp.l: ... this.
* gas/mips/mips5.s: Rename to...
* gas/mips/mips5-fp.s: ... this.
* gas/mips/mips.exp: Update accordingly.
Maciej
binutils-test-mips5-fp.diff
Index: binutils-fsf-trunk-quilt/gas/testsuite/gas/mips/mips.exp
===================================================================
--- binutils-fsf-trunk-quilt.orig/gas/testsuite/gas/mips/mips.exp 2011-08-10 22:40:06.000000000 +0100
+++ binutils-fsf-trunk-quilt/gas/testsuite/gas/mips/mips.exp 2011-08-10 22:34:22.000000000 +0100
@@ -634,7 +634,7 @@ if { [istarget mips*-*-vxworks*] } {
[mips_arch_list_matching mips4]
run_list_test_arches "mips4-branch-likely" "-32 -msoft-float" \
[mips_arch_list_matching mips4]
- run_dump_test_arches "mips5" [mips_arch_list_matching fpisa5]
+ run_dump_test_arches "mips5-fp" [mips_arch_list_matching fpisa5]
run_dump_test "mul"
run_dump_test_arches "rol" [mips_arch_list_matching mips1 !ror]
Index: binutils-fsf-trunk-quilt/gas/testsuite/gas/mips/micromips@mips5-fp.d
===================================================================
--- /dev/null 1970-01-01 00:00:00.000000000 +0000
+++ binutils-fsf-trunk-quilt/gas/testsuite/gas/mips/micromips@mips5-fp.d 2011-08-10 22:37:44.000000000 +0100
@@ -0,0 +1,69 @@
+#objdump: -dr --prefix-addresses --show-raw-insn -M reg-names=numeric
+#name: MIPS mips5 instructions
+#source: mips5-fp.s
+#stderr: mips5-fp.l
+
+# Check MIPS V instruction assembly (microMIPS).
+
+.*: +file format .*mips.*
+
+Disassembly of section \.text:
+[0-9a-f]+ <[^>]*> 5402 437b abs\.ps \$f0,\$f2
+[0-9a-f]+ <[^>]*> 54c4 1230 add\.ps \$f2,\$f4,\$f6
+[0-9a-f]+ <[^>]*> 5548 30d9 alnv\.ps \$f6,\$f8,\$f10,\$3
+[0-9a-f]+ <[^>]*> 5548 08bc c\.eq\.ps \$f8,\$f10
+[0-9a-f]+ <[^>]*> 558a 48bc c\.eq\.ps \$fcc2,\$f10,\$f12
+[0-9a-f]+ <[^>]*> 5548 083c c\.f\.ps \$f8,\$f10
+[0-9a-f]+ <[^>]*> 558a 483c c\.f\.ps \$fcc2,\$f10,\$f12
+[0-9a-f]+ <[^>]*> 5548 0bbc c\.le\.ps \$f8,\$f10
+[0-9a-f]+ <[^>]*> 558a 4bbc c\.le\.ps \$fcc2,\$f10,\$f12
+[0-9a-f]+ <[^>]*> 5548 0b3c c\.lt\.ps \$f8,\$f10
+[0-9a-f]+ <[^>]*> 558a 4b3c c\.lt\.ps \$fcc2,\$f10,\$f12
+[0-9a-f]+ <[^>]*> 5548 0b7c c\.nge\.ps \$f8,\$f10
+[0-9a-f]+ <[^>]*> 558a 4b7c c\.nge\.ps \$fcc2,\$f10,\$f12
+[0-9a-f]+ <[^>]*> 5548 0afc c\.ngl\.ps \$f8,\$f10
+[0-9a-f]+ <[^>]*> 558a 4afc c\.ngl\.ps \$fcc2,\$f10,\$f12
+[0-9a-f]+ <[^>]*> 5548 0a7c c\.ngle\.ps \$f8,\$f10
+[0-9a-f]+ <[^>]*> 558a 4a7c c\.ngle\.ps \$fcc2,\$f10,\$f12
+[0-9a-f]+ <[^>]*> 5548 0bfc c\.ngt\.ps \$f8,\$f10
+[0-9a-f]+ <[^>]*> 558a 4bfc c\.ngt\.ps \$fcc2,\$f10,\$f12
+[0-9a-f]+ <[^>]*> 5548 09bc c\.ole\.ps \$f8,\$f10
+[0-9a-f]+ <[^>]*> 558a 49bc c\.ole\.ps \$fcc2,\$f10,\$f12
+[0-9a-f]+ <[^>]*> 5548 093c c\.olt\.ps \$f8,\$f10
+[0-9a-f]+ <[^>]*> 558a 493c c\.olt\.ps \$fcc2,\$f10,\$f12
+[0-9a-f]+ <[^>]*> 5548 0abc c\.seq\.ps \$f8,\$f10
+[0-9a-f]+ <[^>]*> 558a 4abc c\.seq\.ps \$fcc2,\$f10,\$f12
+[0-9a-f]+ <[^>]*> 5548 0a3c c\.sf\.ps \$f8,\$f10
+[0-9a-f]+ <[^>]*> 558a 4a3c c\.sf\.ps \$fcc2,\$f10,\$f12
+[0-9a-f]+ <[^>]*> 5548 08fc c\.ueq\.ps \$f8,\$f10
+[0-9a-f]+ <[^>]*> 558a 48fc c\.ueq\.ps \$fcc2,\$f10,\$f12
+[0-9a-f]+ <[^>]*> 5548 09fc c\.ule\.ps \$f8,\$f10
+[0-9a-f]+ <[^>]*> 558a 49fc c\.ule\.ps \$fcc2,\$f10,\$f12
+[0-9a-f]+ <[^>]*> 5548 097c c\.ult\.ps \$f8,\$f10
+[0-9a-f]+ <[^>]*> 558a 497c c\.ult\.ps \$fcc2,\$f10,\$f12
+[0-9a-f]+ <[^>]*> 5548 087c c\.un\.ps \$f8,\$f10
+[0-9a-f]+ <[^>]*> 558a 487c c\.un\.ps \$fcc2,\$f10,\$f12
+[0-9a-f]+ <[^>]*> 560e 6180 cvt\.ps\.s \$f12,\$f14,\$f16
+[0-9a-f]+ <[^>]*> 5612 213b cvt\.s\.pl \$f16,\$f18
+[0-9a-f]+ <[^>]*> 5654 293b cvt\.s\.pu \$f18,\$f20
+[0-9a-f]+ <[^>]*> 5485 a148 luxc1 \$f20,\$4\(\$5\)
+[0-9a-f]+ <[^>]*> 5758 a591 madd\.ps \$f20,\$f22,\$f24,\$f26
+[0-9a-f]+ <[^>]*> 571a 407b mov\.ps \$f24,\$f26
+[0-9a-f]+ <[^>]*> 575c 4420 movf\.ps \$f26,\$f28,\$fcc2
+[0-9a-f]+ <[^>]*> 547c d238 movn\.ps \$f26,\$f28,\$3
+[0-9a-f]+ <[^>]*> 579e 8460 movt\.ps \$f28,\$f30,\$fcc4
+[0-9a-f]+ <[^>]*> 54be e278 movz\.ps \$f28,\$f30,\$5
+[0-9a-f]+ <[^>]*> 5482 f031 msub\.ps \$f30,\$f0,\$f2,\$f4
+[0-9a-f]+ <[^>]*> 54c4 12b0 mul\.ps \$f2,\$f4,\$f6
+[0-9a-f]+ <[^>]*> 54c8 4b7b neg\.ps \$f6,\$f8
+[0-9a-f]+ <[^>]*> 558a 3212 nmadd\.ps \$f6,\$f8,\$f10,\$f12
+[0-9a-f]+ <[^>]*> 558a 3232 nmsub\.ps \$f6,\$f8,\$f10,\$f12
+[0-9a-f]+ <[^>]*> 55cc 5080 pll\.ps \$f10,\$f12,\$f14
+[0-9a-f]+ <[^>]*> 5650 70c0 plu\.ps \$f14,\$f16,\$f18
+[0-9a-f]+ <[^>]*> 5692 8100 pul\.ps \$f16,\$f18,\$f20
+[0-9a-f]+ <[^>]*> 5716 a140 puu\.ps \$f20,\$f22,\$f24
+[0-9a-f]+ <[^>]*> 5758 b270 sub\.ps \$f22,\$f24,\$f26
+[0-9a-f]+ <[^>]*> 54c7 d188 suxc1 \$f26,\$6\(\$7\)
+[0-9a-f]+ <[^>]*> 558a 68bc c\.eq\.ps \$fcc3,\$f10,\$f12
+[0-9a-f]+ <[^>]*> 575c 6420 movf\.ps \$f26,\$f28,\$fcc3
+ \.\.\.
Index: binutils-fsf-trunk-quilt/gas/testsuite/gas/mips/micromips@mips5.d
===================================================================
--- binutils-fsf-trunk-quilt.orig/gas/testsuite/gas/mips/micromips@mips5.d 2011-07-28 00:17:45.000000000 +0100
+++ /dev/null 1970-01-01 00:00:00.000000000 +0000
@@ -1,69 +0,0 @@
-#objdump: -dr --prefix-addresses --show-raw-insn -M reg-names=numeric
-#name: MIPS mips5 instructions
-#source: mips5.s
-#stderr: mips5.l
-
-# Check MIPS V instruction assembly (microMIPS).
-
-.*: +file format .*mips.*
-
-Disassembly of section \.text:
-[0-9a-f]+ <[^>]*> 5402 437b abs\.ps \$f0,\$f2
-[0-9a-f]+ <[^>]*> 54c4 1230 add\.ps \$f2,\$f4,\$f6
-[0-9a-f]+ <[^>]*> 5548 30d9 alnv\.ps \$f6,\$f8,\$f10,\$3
-[0-9a-f]+ <[^>]*> 5548 08bc c\.eq\.ps \$f8,\$f10
-[0-9a-f]+ <[^>]*> 558a 48bc c\.eq\.ps \$fcc2,\$f10,\$f12
-[0-9a-f]+ <[^>]*> 5548 083c c\.f\.ps \$f8,\$f10
-[0-9a-f]+ <[^>]*> 558a 483c c\.f\.ps \$fcc2,\$f10,\$f12
-[0-9a-f]+ <[^>]*> 5548 0bbc c\.le\.ps \$f8,\$f10
-[0-9a-f]+ <[^>]*> 558a 4bbc c\.le\.ps \$fcc2,\$f10,\$f12
-[0-9a-f]+ <[^>]*> 5548 0b3c c\.lt\.ps \$f8,\$f10
-[0-9a-f]+ <[^>]*> 558a 4b3c c\.lt\.ps \$fcc2,\$f10,\$f12
-[0-9a-f]+ <[^>]*> 5548 0b7c c\.nge\.ps \$f8,\$f10
-[0-9a-f]+ <[^>]*> 558a 4b7c c\.nge\.ps \$fcc2,\$f10,\$f12
-[0-9a-f]+ <[^>]*> 5548 0afc c\.ngl\.ps \$f8,\$f10
-[0-9a-f]+ <[^>]*> 558a 4afc c\.ngl\.ps \$fcc2,\$f10,\$f12
-[0-9a-f]+ <[^>]*> 5548 0a7c c\.ngle\.ps \$f8,\$f10
-[0-9a-f]+ <[^>]*> 558a 4a7c c\.ngle\.ps \$fcc2,\$f10,\$f12
-[0-9a-f]+ <[^>]*> 5548 0bfc c\.ngt\.ps \$f8,\$f10
-[0-9a-f]+ <[^>]*> 558a 4bfc c\.ngt\.ps \$fcc2,\$f10,\$f12
-[0-9a-f]+ <[^>]*> 5548 09bc c\.ole\.ps \$f8,\$f10
-[0-9a-f]+ <[^>]*> 558a 49bc c\.ole\.ps \$fcc2,\$f10,\$f12
-[0-9a-f]+ <[^>]*> 5548 093c c\.olt\.ps \$f8,\$f10
-[0-9a-f]+ <[^>]*> 558a 493c c\.olt\.ps \$fcc2,\$f10,\$f12
-[0-9a-f]+ <[^>]*> 5548 0abc c\.seq\.ps \$f8,\$f10
-[0-9a-f]+ <[^>]*> 558a 4abc c\.seq\.ps \$fcc2,\$f10,\$f12
-[0-9a-f]+ <[^>]*> 5548 0a3c c\.sf\.ps \$f8,\$f10
-[0-9a-f]+ <[^>]*> 558a 4a3c c\.sf\.ps \$fcc2,\$f10,\$f12
-[0-9a-f]+ <[^>]*> 5548 08fc c\.ueq\.ps \$f8,\$f10
-[0-9a-f]+ <[^>]*> 558a 48fc c\.ueq\.ps \$fcc2,\$f10,\$f12
-[0-9a-f]+ <[^>]*> 5548 09fc c\.ule\.ps \$f8,\$f10
-[0-9a-f]+ <[^>]*> 558a 49fc c\.ule\.ps \$fcc2,\$f10,\$f12
-[0-9a-f]+ <[^>]*> 5548 097c c\.ult\.ps \$f8,\$f10
-[0-9a-f]+ <[^>]*> 558a 497c c\.ult\.ps \$fcc2,\$f10,\$f12
-[0-9a-f]+ <[^>]*> 5548 087c c\.un\.ps \$f8,\$f10
-[0-9a-f]+ <[^>]*> 558a 487c c\.un\.ps \$fcc2,\$f10,\$f12
-[0-9a-f]+ <[^>]*> 560e 6180 cvt\.ps\.s \$f12,\$f14,\$f16
-[0-9a-f]+ <[^>]*> 5612 213b cvt\.s\.pl \$f16,\$f18
-[0-9a-f]+ <[^>]*> 5654 293b cvt\.s\.pu \$f18,\$f20
-[0-9a-f]+ <[^>]*> 5485 a148 luxc1 \$f20,\$4\(\$5\)
-[0-9a-f]+ <[^>]*> 5758 a591 madd\.ps \$f20,\$f22,\$f24,\$f26
-[0-9a-f]+ <[^>]*> 571a 407b mov\.ps \$f24,\$f26
-[0-9a-f]+ <[^>]*> 575c 4420 movf\.ps \$f26,\$f28,\$fcc2
-[0-9a-f]+ <[^>]*> 547c d238 movn\.ps \$f26,\$f28,\$3
-[0-9a-f]+ <[^>]*> 579e 8460 movt\.ps \$f28,\$f30,\$fcc4
-[0-9a-f]+ <[^>]*> 54be e278 movz\.ps \$f28,\$f30,\$5
-[0-9a-f]+ <[^>]*> 5482 f031 msub\.ps \$f30,\$f0,\$f2,\$f4
-[0-9a-f]+ <[^>]*> 54c4 12b0 mul\.ps \$f2,\$f4,\$f6
-[0-9a-f]+ <[^>]*> 54c8 4b7b neg\.ps \$f6,\$f8
-[0-9a-f]+ <[^>]*> 558a 3212 nmadd\.ps \$f6,\$f8,\$f10,\$f12
-[0-9a-f]+ <[^>]*> 558a 3232 nmsub\.ps \$f6,\$f8,\$f10,\$f12
-[0-9a-f]+ <[^>]*> 55cc 5080 pll\.ps \$f10,\$f12,\$f14
-[0-9a-f]+ <[^>]*> 5650 70c0 plu\.ps \$f14,\$f16,\$f18
-[0-9a-f]+ <[^>]*> 5692 8100 pul\.ps \$f16,\$f18,\$f20
-[0-9a-f]+ <[^>]*> 5716 a140 puu\.ps \$f20,\$f22,\$f24
-[0-9a-f]+ <[^>]*> 5758 b270 sub\.ps \$f22,\$f24,\$f26
-[0-9a-f]+ <[^>]*> 54c7 d188 suxc1 \$f26,\$6\(\$7\)
-[0-9a-f]+ <[^>]*> 558a 68bc c\.eq\.ps \$fcc3,\$f10,\$f12
-[0-9a-f]+ <[^>]*> 575c 6420 movf\.ps \$f26,\$f28,\$fcc3
- \.\.\.
Index: binutils-fsf-trunk-quilt/gas/testsuite/gas/mips/mips5-fp.d
===================================================================
--- /dev/null 1970-01-01 00:00:00.000000000 +0000
+++ binutils-fsf-trunk-quilt/gas/testsuite/gas/mips/mips5-fp.d 2011-08-10 22:37:48.000000000 +0100
@@ -0,0 +1,68 @@
+#objdump: -dr --prefix-addresses --show-raw-insn -M reg-names=numeric
+#name: MIPS mips5 instructions
+#stderr: mips5-fp.l
+
+# Check MIPS V instruction assembly
+
+.*: +file format .*mips.*
+
+Disassembly of section \.text:
+0+0000 <[^>]*> 46c01005 abs\.ps \$f0,\$f2
+0+0004 <[^>]*> 46c62080 add\.ps \$f2,\$f4,\$f6
+0+0008 <[^>]*> 4c6a419e alnv\.ps \$f6,\$f8,\$f10,\$3
+0+000c <[^>]*> 46ca4032 c\.eq\.ps \$f8,\$f10
+0+0010 <[^>]*> 46cc5232 c\.eq\.ps \$fcc2,\$f10,\$f12
+0+0014 <[^>]*> 46ca4030 c\.f\.ps \$f8,\$f10
+0+0018 <[^>]*> 46cc5230 c\.f\.ps \$fcc2,\$f10,\$f12
+0+001c <[^>]*> 46ca403e c\.le\.ps \$f8,\$f10
+0+0020 <[^>]*> 46cc523e c\.le\.ps \$fcc2,\$f10,\$f12
+0+0024 <[^>]*> 46ca403c c\.lt\.ps \$f8,\$f10
+0+0028 <[^>]*> 46cc523c c\.lt\.ps \$fcc2,\$f10,\$f12
+0+002c <[^>]*> 46ca403d c\.nge\.ps \$f8,\$f10
+0+0030 <[^>]*> 46cc523d c\.nge\.ps \$fcc2,\$f10,\$f12
+0+0034 <[^>]*> 46ca403b c\.ngl\.ps \$f8,\$f10
+0+0038 <[^>]*> 46cc523b c\.ngl\.ps \$fcc2,\$f10,\$f12
+0+003c <[^>]*> 46ca4039 c\.ngle\.ps \$f8,\$f10
+0+0040 <[^>]*> 46cc5239 c\.ngle\.ps \$fcc2,\$f10,\$f12
+0+0044 <[^>]*> 46ca403f c\.ngt\.ps \$f8,\$f10
+0+0048 <[^>]*> 46cc523f c\.ngt\.ps \$fcc2,\$f10,\$f12
+0+004c <[^>]*> 46ca4036 c\.ole\.ps \$f8,\$f10
+0+0050 <[^>]*> 46cc5236 c\.ole\.ps \$fcc2,\$f10,\$f12
+0+0054 <[^>]*> 46ca4034 c\.olt\.ps \$f8,\$f10
+0+0058 <[^>]*> 46cc5234 c\.olt\.ps \$fcc2,\$f10,\$f12
+0+005c <[^>]*> 46ca403a c\.seq\.ps \$f8,\$f10
+0+0060 <[^>]*> 46cc523a c\.seq\.ps \$fcc2,\$f10,\$f12
+0+0064 <[^>]*> 46ca4038 c\.sf\.ps \$f8,\$f10
+0+0068 <[^>]*> 46cc5238 c\.sf\.ps \$fcc2,\$f10,\$f12
+0+006c <[^>]*> 46ca4033 c\.ueq\.ps \$f8,\$f10
+0+0070 <[^>]*> 46cc5233 c\.ueq\.ps \$fcc2,\$f10,\$f12
+0+0074 <[^>]*> 46ca4037 c\.ule\.ps \$f8,\$f10
+0+0078 <[^>]*> 46cc5237 c\.ule\.ps \$fcc2,\$f10,\$f12
+0+007c <[^>]*> 46ca4035 c\.ult\.ps \$f8,\$f10
+0+0080 <[^>]*> 46cc5235 c\.ult\.ps \$fcc2,\$f10,\$f12
+0+0084 <[^>]*> 46ca4031 c\.un\.ps \$f8,\$f10
+0+0088 <[^>]*> 46cc5231 c\.un\.ps \$fcc2,\$f10,\$f12
+0+008c <[^>]*> 46107326 cvt\.ps\.s \$f12,\$f14,\$f16
+0+0090 <[^>]*> 46c09428 cvt\.s\.pl \$f16,\$f18
+0+0094 <[^>]*> 46c0a4a0 cvt\.s\.pu \$f18,\$f20
+0+0098 <[^>]*> 4ca40505 luxc1 \$f20,\$4\(\$5\)
+0+009c <[^>]*> 4edac526 madd\.ps \$f20,\$f22,\$f24,\$f26
+0+00a0 <[^>]*> 46c0d606 mov\.ps \$f24,\$f26
+0+00a4 <[^>]*> 46c8e691 movf\.ps \$f26,\$f28,\$fcc2
+0+00a8 <[^>]*> 46c3e693 movn\.ps \$f26,\$f28,\$3
+0+00ac <[^>]*> 46d1f711 movt\.ps \$f28,\$f30,\$fcc4
+0+00b0 <[^>]*> 46c5f712 movz\.ps \$f28,\$f30,\$5
+0+00b4 <[^>]*> 4c0417ae msub\.ps \$f30,\$f0,\$f2,\$f4
+0+00b8 <[^>]*> 46c62082 mul\.ps \$f2,\$f4,\$f6
+0+00bc <[^>]*> 46c04187 neg\.ps \$f6,\$f8
+0+00c0 <[^>]*> 4d0c51b6 nmadd\.ps \$f6,\$f8,\$f10,\$f12
+0+00c4 <[^>]*> 4d0c51be nmsub\.ps \$f6,\$f8,\$f10,\$f12
+0+00c8 <[^>]*> 46ce62ac pll\.ps \$f10,\$f12,\$f14
+0+00cc <[^>]*> 46d283ad plu\.ps \$f14,\$f16,\$f18
+0+00d0 <[^>]*> 46d4942e pul\.ps \$f16,\$f18,\$f20
+0+00d4 <[^>]*> 46d8b52f puu\.ps \$f20,\$f22,\$f24
+0+00d8 <[^>]*> 46dac581 sub\.ps \$f22,\$f24,\$f26
+0+00dc <[^>]*> 4ce6d00d suxc1 \$f26,\$6\(\$7\)
+0+00e0 <[^>]*> 46cc5332 c\.eq\.ps \$fcc3,\$f10,\$f12
+0+00e4 <[^>]*> 46cce691 movf\.ps \$f26,\$f28,\$fcc3
+ \.\.\.
Index: binutils-fsf-trunk-quilt/gas/testsuite/gas/mips/mips5-fp.l
===================================================================
--- /dev/null 1970-01-01 00:00:00.000000000 +0000
+++ binutils-fsf-trunk-quilt/gas/testsuite/gas/mips/mips5-fp.l 2011-08-10 22:35:02.000000000 +0100
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*:61: Warning: Condition code register should be even for c.eq.ps, was 3
+.*:62: Warning: Condition code register should be even for movf.ps, was 3
Index: binutils-fsf-trunk-quilt/gas/testsuite/gas/mips/mips5-fp.s
===================================================================
--- /dev/null 1970-01-01 00:00:00.000000000 +0000
+++ binutils-fsf-trunk-quilt/gas/testsuite/gas/mips/mips5-fp.s 2011-08-10 22:35:02.000000000 +0100
@@ -0,0 +1,65 @@
+# Source file used to test -mips5 instructions.
+
+text_label:
+ abs.ps $f0, $f2
+ add.ps $f2, $f4, $f6
+ alnv.ps $f6, $f8, $f10, $3
+ c.eq.ps $f8, $f10
+ c.eq.ps $fcc2, $f10, $f12
+ c.f.ps $f8, $f10
+ c.f.ps $fcc2, $f10, $f12
+ c.le.ps $f8, $f10
+ c.le.ps $fcc2, $f10, $f12
+ c.lt.ps $f8, $f10
+ c.lt.ps $fcc2, $f10, $f12
+ c.nge.ps $f8, $f10
+ c.nge.ps $fcc2, $f10, $f12
+ c.ngl.ps $f8, $f10
+ c.ngl.ps $fcc2, $f10, $f12
+ c.ngle.ps $f8, $f10
+ c.ngle.ps $fcc2, $f10, $f12
+ c.ngt.ps $f8, $f10
+ c.ngt.ps $fcc2, $f10, $f12
+ c.ole.ps $f8, $f10
+ c.ole.ps $fcc2, $f10, $f12
+ c.olt.ps $f8, $f10
+ c.olt.ps $fcc2, $f10, $f12
+ c.seq.ps $f8, $f10
+ c.seq.ps $fcc2, $f10, $f12
+ c.sf.ps $f8, $f10
+ c.sf.ps $fcc2, $f10, $f12
+ c.ueq.ps $f8, $f10
+ c.ueq.ps $fcc2, $f10, $f12
+ c.ule.ps $f8, $f10
+ c.ule.ps $fcc2, $f10, $f12
+ c.ult.ps $f8, $f10
+ c.ult.ps $fcc2, $f10, $f12
+ c.un.ps $f8, $f10
+ c.un.ps $fcc2, $f10, $f12
+ cvt.ps.s $f12, $f14, $f16
+ cvt.s.pl $f16, $f18
+ cvt.s.pu $f18, $f20
+ luxc1 $f20, $4($5)
+ madd.ps $f20, $f22, $f24, $f26
+ mov.ps $f24, $f26
+ movf.ps $f26, $f28, $fcc2
+ movn.ps $f26, $f28, $3
+ movt.ps $f28, $f30, $fcc4
+ movz.ps $f28, $f30, $5
+ msub.ps $f30, $f0, $f2, $f4
+ mul.ps $f2, $f4, $f6
+ neg.ps $f6, $f8
+ nmadd.ps $f6, $f8, $f10, $f12
+ nmsub.ps $f6, $f8, $f10, $f12
+ pll.ps $f10, $f12, $f14
+ plu.ps $f14, $f16, $f18
+ pul.ps $f16, $f18, $f20
+ puu.ps $f20, $f22, $f24
+ sub.ps $f22, $f24, $f26
+ suxc1 $f26, $6($7)
+
+ c.eq.ps $fcc3, $f10, $f12 # warns
+ movf.ps $f26, $f28, $fcc3 # warns
+
+# Force at least 8 (non-delay-slot) zero bytes, to make 'objdump' print ...
+ .space 8
Index: binutils-fsf-trunk-quilt/gas/testsuite/gas/mips/mips5.d
===================================================================
--- binutils-fsf-trunk-quilt.orig/gas/testsuite/gas/mips/mips5.d 2010-05-12 22:07:14.000000000 +0100
+++ /dev/null 1970-01-01 00:00:00.000000000 +0000
@@ -1,68 +0,0 @@
-#objdump: -dr --prefix-addresses --show-raw-insn -M reg-names=numeric
-#name: MIPS mips5 instructions
-#stderr: mips5.l
-
-# Check MIPS V instruction assembly
-
-.*: +file format .*mips.*
-
-Disassembly of section \.text:
-0+0000 <[^>]*> 46c01005 abs\.ps \$f0,\$f2
-0+0004 <[^>]*> 46c62080 add\.ps \$f2,\$f4,\$f6
-0+0008 <[^>]*> 4c6a419e alnv\.ps \$f6,\$f8,\$f10,\$3
-0+000c <[^>]*> 46ca4032 c\.eq\.ps \$f8,\$f10
-0+0010 <[^>]*> 46cc5232 c\.eq\.ps \$fcc2,\$f10,\$f12
-0+0014 <[^>]*> 46ca4030 c\.f\.ps \$f8,\$f10
-0+0018 <[^>]*> 46cc5230 c\.f\.ps \$fcc2,\$f10,\$f12
-0+001c <[^>]*> 46ca403e c\.le\.ps \$f8,\$f10
-0+0020 <[^>]*> 46cc523e c\.le\.ps \$fcc2,\$f10,\$f12
-0+0024 <[^>]*> 46ca403c c\.lt\.ps \$f8,\$f10
-0+0028 <[^>]*> 46cc523c c\.lt\.ps \$fcc2,\$f10,\$f12
-0+002c <[^>]*> 46ca403d c\.nge\.ps \$f8,\$f10
-0+0030 <[^>]*> 46cc523d c\.nge\.ps \$fcc2,\$f10,\$f12
-0+0034 <[^>]*> 46ca403b c\.ngl\.ps \$f8,\$f10
-0+0038 <[^>]*> 46cc523b c\.ngl\.ps \$fcc2,\$f10,\$f12
-0+003c <[^>]*> 46ca4039 c\.ngle\.ps \$f8,\$f10
-0+0040 <[^>]*> 46cc5239 c\.ngle\.ps \$fcc2,\$f10,\$f12
-0+0044 <[^>]*> 46ca403f c\.ngt\.ps \$f8,\$f10
-0+0048 <[^>]*> 46cc523f c\.ngt\.ps \$fcc2,\$f10,\$f12
-0+004c <[^>]*> 46ca4036 c\.ole\.ps \$f8,\$f10
-0+0050 <[^>]*> 46cc5236 c\.ole\.ps \$fcc2,\$f10,\$f12
-0+0054 <[^>]*> 46ca4034 c\.olt\.ps \$f8,\$f10
-0+0058 <[^>]*> 46cc5234 c\.olt\.ps \$fcc2,\$f10,\$f12
-0+005c <[^>]*> 46ca403a c\.seq\.ps \$f8,\$f10
-0+0060 <[^>]*> 46cc523a c\.seq\.ps \$fcc2,\$f10,\$f12
-0+0064 <[^>]*> 46ca4038 c\.sf\.ps \$f8,\$f10
-0+0068 <[^>]*> 46cc5238 c\.sf\.ps \$fcc2,\$f10,\$f12
-0+006c <[^>]*> 46ca4033 c\.ueq\.ps \$f8,\$f10
-0+0070 <[^>]*> 46cc5233 c\.ueq\.ps \$fcc2,\$f10,\$f12
-0+0074 <[^>]*> 46ca4037 c\.ule\.ps \$f8,\$f10
-0+0078 <[^>]*> 46cc5237 c\.ule\.ps \$fcc2,\$f10,\$f12
-0+007c <[^>]*> 46ca4035 c\.ult\.ps \$f8,\$f10
-0+0080 <[^>]*> 46cc5235 c\.ult\.ps \$fcc2,\$f10,\$f12
-0+0084 <[^>]*> 46ca4031 c\.un\.ps \$f8,\$f10
-0+0088 <[^>]*> 46cc5231 c\.un\.ps \$fcc2,\$f10,\$f12
-0+008c <[^>]*> 46107326 cvt\.ps\.s \$f12,\$f14,\$f16
-0+0090 <[^>]*> 46c09428 cvt\.s\.pl \$f16,\$f18
-0+0094 <[^>]*> 46c0a4a0 cvt\.s\.pu \$f18,\$f20
-0+0098 <[^>]*> 4ca40505 luxc1 \$f20,\$4\(\$5\)
-0+009c <[^>]*> 4edac526 madd\.ps \$f20,\$f22,\$f24,\$f26
-0+00a0 <[^>]*> 46c0d606 mov\.ps \$f24,\$f26
-0+00a4 <[^>]*> 46c8e691 movf\.ps \$f26,\$f28,\$fcc2
-0+00a8 <[^>]*> 46c3e693 movn\.ps \$f26,\$f28,\$3
-0+00ac <[^>]*> 46d1f711 movt\.ps \$f28,\$f30,\$fcc4
-0+00b0 <[^>]*> 46c5f712 movz\.ps \$f28,\$f30,\$5
-0+00b4 <[^>]*> 4c0417ae msub\.ps \$f30,\$f0,\$f2,\$f4
-0+00b8 <[^>]*> 46c62082 mul\.ps \$f2,\$f4,\$f6
-0+00bc <[^>]*> 46c04187 neg\.ps \$f6,\$f8
-0+00c0 <[^>]*> 4d0c51b6 nmadd\.ps \$f6,\$f8,\$f10,\$f12
-0+00c4 <[^>]*> 4d0c51be nmsub\.ps \$f6,\$f8,\$f10,\$f12
-0+00c8 <[^>]*> 46ce62ac pll\.ps \$f10,\$f12,\$f14
-0+00cc <[^>]*> 46d283ad plu\.ps \$f14,\$f16,\$f18
-0+00d0 <[^>]*> 46d4942e pul\.ps \$f16,\$f18,\$f20
-0+00d4 <[^>]*> 46d8b52f puu\.ps \$f20,\$f22,\$f24
-0+00d8 <[^>]*> 46dac581 sub\.ps \$f22,\$f24,\$f26
-0+00dc <[^>]*> 4ce6d00d suxc1 \$f26,\$6\(\$7\)
-0+00e0 <[^>]*> 46cc5332 c\.eq\.ps \$fcc3,\$f10,\$f12
-0+00e4 <[^>]*> 46cce691 movf\.ps \$f26,\$f28,\$fcc3
- \.\.\.
Index: binutils-fsf-trunk-quilt/gas/testsuite/gas/mips/mips5.l
===================================================================
--- binutils-fsf-trunk-quilt.orig/gas/testsuite/gas/mips/mips5.l 2010-05-12 22:07:14.000000000 +0100
+++ /dev/null 1970-01-01 00:00:00.000000000 +0000
@@ -1,3 +0,0 @@
-.*: Assembler messages:
-.*:61: Warning: Condition code register should be even for c.eq.ps, was 3
-.*:62: Warning: Condition code register should be even for movf.ps, was 3
Index: binutils-fsf-trunk-quilt/gas/testsuite/gas/mips/mips5.s
===================================================================
--- binutils-fsf-trunk-quilt.orig/gas/testsuite/gas/mips/mips5.s 2010-05-12 22:07:14.000000000 +0100
+++ /dev/null 1970-01-01 00:00:00.000000000 +0000
@@ -1,65 +0,0 @@
-# Source file used to test -mips5 instructions.
-
-text_label:
- abs.ps $f0, $f2
- add.ps $f2, $f4, $f6
- alnv.ps $f6, $f8, $f10, $3
- c.eq.ps $f8, $f10
- c.eq.ps $fcc2, $f10, $f12
- c.f.ps $f8, $f10
- c.f.ps $fcc2, $f10, $f12
- c.le.ps $f8, $f10
- c.le.ps $fcc2, $f10, $f12
- c.lt.ps $f8, $f10
- c.lt.ps $fcc2, $f10, $f12
- c.nge.ps $f8, $f10
- c.nge.ps $fcc2, $f10, $f12
- c.ngl.ps $f8, $f10
- c.ngl.ps $fcc2, $f10, $f12
- c.ngle.ps $f8, $f10
- c.ngle.ps $fcc2, $f10, $f12
- c.ngt.ps $f8, $f10
- c.ngt.ps $fcc2, $f10, $f12
- c.ole.ps $f8, $f10
- c.ole.ps $fcc2, $f10, $f12
- c.olt.ps $f8, $f10
- c.olt.ps $fcc2, $f10, $f12
- c.seq.ps $f8, $f10
- c.seq.ps $fcc2, $f10, $f12
- c.sf.ps $f8, $f10
- c.sf.ps $fcc2, $f10, $f12
- c.ueq.ps $f8, $f10
- c.ueq.ps $fcc2, $f10, $f12
- c.ule.ps $f8, $f10
- c.ule.ps $fcc2, $f10, $f12
- c.ult.ps $f8, $f10
- c.ult.ps $fcc2, $f10, $f12
- c.un.ps $f8, $f10
- c.un.ps $fcc2, $f10, $f12
- cvt.ps.s $f12, $f14, $f16
- cvt.s.pl $f16, $f18
- cvt.s.pu $f18, $f20
- luxc1 $f20, $4($5)
- madd.ps $f20, $f22, $f24, $f26
- mov.ps $f24, $f26
- movf.ps $f26, $f28, $fcc2
- movn.ps $f26, $f28, $3
- movt.ps $f28, $f30, $fcc4
- movz.ps $f28, $f30, $5
- msub.ps $f30, $f0, $f2, $f4
- mul.ps $f2, $f4, $f6
- neg.ps $f6, $f8
- nmadd.ps $f6, $f8, $f10, $f12
- nmsub.ps $f6, $f8, $f10, $f12
- pll.ps $f10, $f12, $f14
- plu.ps $f14, $f16, $f18
- pul.ps $f16, $f18, $f20
- puu.ps $f20, $f22, $f24
- sub.ps $f22, $f24, $f26
- suxc1 $f26, $6($7)
-
- c.eq.ps $fcc3, $f10, $f12 # warns
- movf.ps $f26, $f28, $fcc3 # warns
-
-# Force at least 8 (non-delay-slot) zero bytes, to make 'objdump' print ...
- .space 8
^ permalink raw reply [flat|nested] 7+ messages in thread
end of thread, other threads:[~2011-08-10 22:52 UTC | newest]
Thread overview: 7+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2011-08-09 23:07 [PATCH] MIPS/GAS/testsuite: Fine-grained MIPS FP ISA matching Maciej W. Rozycki
2011-08-10 8:27 ` Richard Sandiford
2011-08-10 16:12 ` Maciej W. Rozycki
2011-08-10 17:12 ` Richard Sandiford
2011-08-10 17:35 ` Maciej W. Rozycki
2011-08-10 19:10 ` Richard Sandiford
2011-08-10 22:52 ` Maciej W. Rozycki
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