From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 29200 invoked by alias); 21 May 2014 20:45:11 -0000 Mailing-List: contact binutils-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: binutils-owner@sourceware.org Received: (qmail 29183 invoked by uid 89); 21 May 2014 20:45:10 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-0.9 required=5.0 tests=AWL,BAYES_00,FROM_12LTRDOM,UPPERCASE_50_75 autolearn=no version=3.3.2 X-HELO: relay1.mentorg.com Received: from relay1.mentorg.com (HELO relay1.mentorg.com) (192.94.38.131) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Wed, 21 May 2014 20:45:09 +0000 Received: from svr-orw-exc-10.mgc.mentorg.com ([147.34.98.58]) by relay1.mentorg.com with esmtp id 1WnDNo-0002eX-NO from Maciej_Rozycki@mentor.com ; Wed, 21 May 2014 13:45:04 -0700 Received: from SVR-IES-FEM-02.mgc.mentorg.com ([137.202.0.106]) by SVR-ORW-EXC-10.mgc.mentorg.com with Microsoft SMTPSVC(6.0.3790.4675); Wed, 21 May 2014 13:45:04 -0700 Received: from localhost (137.202.0.76) by SVR-IES-FEM-02.mgc.mentorg.com (137.202.0.106) with Microsoft SMTP Server (TLS) id 14.2.247.3; Wed, 21 May 2014 21:45:02 +0100 Date: Wed, 21 May 2014 20:45:00 -0000 From: "Maciej W. Rozycki" To: Christian Svensson , Stefan Kristiansson CC: Subject: or1k/opcodes: ISO C version compatibility issues Message-ID: User-Agent: Alpine 1.10 (DEB 962 2008-03-14) MIME-Version: 1.0 Content-Type: text/plain; charset="US-ASCII" X-SW-Source: 2014-05/txt/msg00195.txt.bz2 Hi, When building GDB with --enable-targets=all for the i686-pc-linux-gnu host using GCC 4.3.3 I've tripped over these errors: cc1: warnings being treated as errors In file included from .../opcodes/or1k-asm.c:34: .../opcodes/or1k-desc.h:260: error: this decimal constant is unsigned only in ISO C90 .../opcodes/or1k-desc.h:263: error: this decimal constant is unsigned only in ISO C90 .../opcodes/or1k-desc.h:270: error: this decimal constant is unsigned only in ISO C90 make[4]: *** [or1k-asm.lo] Error 1 (also for or1k-desc.c). I have been able to make the files compile with the change below, however these are generated files and a suitable change would have to be applied to cpu/or1kcommon.cpu instead. Unfortunately that source has been written in Scheme that I have no immediate skills to correct. Would you please look into making the correct update to the Scheme source? Maciej gdb-opcodes-or1k-unsigned.diff Index: gdb-fsf-trunk-quilt/opcodes/or1k-desc.h =================================================================== --- gdb-fsf-trunk-quilt.orig/opcodes/or1k-desc.h 2014-05-13 02:52:15.000000000 +0100 +++ gdb-fsf-trunk-quilt/opcodes/or1k-desc.h 2014-05-13 03:02:36.919016281 +0100 @@ -257,17 +257,17 @@ typedef enum spr_field_lsbs { /* Enum declaration for SPR field masks. */ typedef enum spr_field_masks { - SPR_FIELD_MASK_SYS_VR_REV = 63, SPR_FIELD_MASK_SYS_VR_CFG = 16711680, SPR_FIELD_MASK_SYS_VR_VER = 4278190080, SPR_FIELD_MASK_SYS_UPR_UP = 1 + SPR_FIELD_MASK_SYS_VR_REV = 63, SPR_FIELD_MASK_SYS_VR_CFG = 16711680, SPR_FIELD_MASK_SYS_VR_VER = 4278190080u, SPR_FIELD_MASK_SYS_UPR_UP = 1 , SPR_FIELD_MASK_SYS_UPR_DCP = 2, SPR_FIELD_MASK_SYS_UPR_ICP = 4, SPR_FIELD_MASK_SYS_UPR_DMP = 8, SPR_FIELD_MASK_SYS_UPR_MP = 16 , SPR_FIELD_MASK_SYS_UPR_IMP = 32, SPR_FIELD_MASK_SYS_UPR_DUP = 64, SPR_FIELD_MASK_SYS_UPR_PCUP = 128, SPR_FIELD_MASK_SYS_UPR_PICP = 256 - , SPR_FIELD_MASK_SYS_UPR_PMP = 512, SPR_FIELD_MASK_SYS_UPR_TTP = 1024, SPR_FIELD_MASK_SYS_UPR_CUP = 4278190080, SPR_FIELD_MASK_SYS_CPUCFGR_NSGR = 15 + , SPR_FIELD_MASK_SYS_UPR_PMP = 512, SPR_FIELD_MASK_SYS_UPR_TTP = 1024, SPR_FIELD_MASK_SYS_UPR_CUP = 4278190080u, SPR_FIELD_MASK_SYS_CPUCFGR_NSGR = 15 , SPR_FIELD_MASK_SYS_CPUCFGR_CGF = 16, SPR_FIELD_MASK_SYS_CPUCFGR_OB32S = 32, SPR_FIELD_MASK_SYS_CPUCFGR_OB64S = 64, SPR_FIELD_MASK_SYS_CPUCFGR_OF32S = 128 , SPR_FIELD_MASK_SYS_CPUCFGR_OF64S = 256, SPR_FIELD_MASK_SYS_CPUCFGR_OV64S = 512, SPR_FIELD_MASK_SYS_CPUCFGR_ND = 1024, SPR_FIELD_MASK_SYS_SR_SM = 1 , SPR_FIELD_MASK_SYS_SR_TEE = 2, SPR_FIELD_MASK_SYS_SR_IEE = 4, SPR_FIELD_MASK_SYS_SR_DCE = 8, SPR_FIELD_MASK_SYS_SR_ICE = 16 , SPR_FIELD_MASK_SYS_SR_DME = 32, SPR_FIELD_MASK_SYS_SR_IME = 64, SPR_FIELD_MASK_SYS_SR_LEE = 128, SPR_FIELD_MASK_SYS_SR_CE = 256 , SPR_FIELD_MASK_SYS_SR_F = 512, SPR_FIELD_MASK_SYS_SR_CY = 1024, SPR_FIELD_MASK_SYS_SR_OV = 2048, SPR_FIELD_MASK_SYS_SR_OVE = 4096 , SPR_FIELD_MASK_SYS_SR_DSX = 8192, SPR_FIELD_MASK_SYS_SR_EPH = 16384, SPR_FIELD_MASK_SYS_SR_FO = 32768, SPR_FIELD_MASK_SYS_SR_SUMRA = 65536 - , SPR_FIELD_MASK_SYS_SR_CID = 4026531840, SPR_FIELD_MASK_SYS_FPCSR_FPEE = 1, SPR_FIELD_MASK_SYS_FPCSR_RM = 6, SPR_FIELD_MASK_SYS_FPCSR_OVF = 8 + , SPR_FIELD_MASK_SYS_SR_CID = 4026531840u, SPR_FIELD_MASK_SYS_FPCSR_FPEE = 1, SPR_FIELD_MASK_SYS_FPCSR_RM = 6, SPR_FIELD_MASK_SYS_FPCSR_OVF = 8 , SPR_FIELD_MASK_SYS_FPCSR_UNF = 16, SPR_FIELD_MASK_SYS_FPCSR_SNF = 32, SPR_FIELD_MASK_SYS_FPCSR_QNF = 64, SPR_FIELD_MASK_SYS_FPCSR_ZF = 128 , SPR_FIELD_MASK_SYS_FPCSR_IXF = 256, SPR_FIELD_MASK_SYS_FPCSR_IVF = 512, SPR_FIELD_MASK_SYS_FPCSR_INF = 1024, SPR_FIELD_MASK_SYS_FPCSR_DZF = 2048 } SPR_FIELD_MASKS;