* [committed 00/18] MIPS coprocessor opcodes handling fixes
@ 2021-05-29 1:36 Maciej W. Rozycki
2021-05-29 1:36 ` [committed 01/18] MIPS/GAS: Use FCSR rather than RA with CFC1/CTC1 Maciej W. Rozycki
` (17 more replies)
0 siblings, 18 replies; 19+ messages in thread
From: Maciej W. Rozycki @ 2021-05-29 1:36 UTC (permalink / raw)
To: binutils
Hi,
In the course of an attempt to track down a Linux kernel heisenbug making
init(8) sometimes crash with SIGSEGV upon boot with an R3000-based system
I have noticed the RFE instruction is not correctly disassembled and the
generic `c0 0x10' notation is produced instead. This is due to an earlier
change, which reordered the "rfe" entry in the opcode table to the wrong
place and caused this regression.
This was supposed to be a simple change, a one-liner really, but I chose
to add a proper test case for it and in the course I discovered numerous
issues in coprocessor opcode handling, plus a missing `config.sub' part
required for some GAS configurations, already committed previously. I
ended up with this patch series of 18 patches total, with the original RFE
fix buried within, as 11/18. Also I had 1/18 prepared earlier on already,
but it's turned out intertwined with some of the other changes, so I have
bundled it with the rest.
See individual change descriptions for details.
Regression-tested across 87 MIPS targets. Committed.
Maciej
^ permalink raw reply [flat|nested] 19+ messages in thread
* [committed 01/18] MIPS/GAS: Use FCSR rather than RA with CFC1/CTC1
2021-05-29 1:36 [committed 00/18] MIPS coprocessor opcodes handling fixes Maciej W. Rozycki
@ 2021-05-29 1:36 ` Maciej W. Rozycki
2021-05-29 1:36 ` [committed 02/18] microMIPS/opcodes: Refer FPRs rather than FCRs with DMTC1 Maciej W. Rozycki
` (16 subsequent siblings)
17 siblings, 0 replies; 19+ messages in thread
From: Maciej W. Rozycki @ 2021-05-29 1:36 UTC (permalink / raw)
To: binutils
Fix an issue caused by commit f9419b056fe2 ("MIPS gas: code cleanup"),
<https://sourceware.org/ml/binutils/2002-05/msg00192.html>, and replace
the incorrect use of RA with the CFC1 and CTC1 instructions with FCSR.
While the register referred by its number is $31 in both cases, these
instructions operate on the floating-point control register file rather
than general-purpose registers.
gas/
* config/tc-mips.c (FCSR): New macro.
(macro) <M_TRUNCWS, M_TRUNCWD>: Use it in place of RA.
---
gas/config/tc-mips.c | 10 ++++++----
1 file changed, 6 insertions(+), 4 deletions(-)
binutils-mips1-gas-truncwx-fcsr.diff
Index: binutils-gdb/gas/config/tc-mips.c
===================================================================
--- binutils-gdb.orig/gas/config/tc-mips.c
+++ binutils-gdb/gas/config/tc-mips.c
@@ -104,6 +104,8 @@ static char *mips_flags_frag;
#define FP 30
#define RA 31
+#define FCSR 31
+
#define ILLEGAL_REG (32)
#define AT mips_opts.at
@@ -13835,18 +13837,18 @@ macro (struct mips_cl_insn *ip, char *st
* or is there a reason for it?
*/
start_noreorder ();
- macro_build (NULL, "cfc1", "t,G", op[2], RA);
- macro_build (NULL, "cfc1", "t,G", op[2], RA);
+ macro_build (NULL, "cfc1", "t,G", op[2], FCSR);
+ macro_build (NULL, "cfc1", "t,G", op[2], FCSR);
macro_build (NULL, "nop", "");
expr1.X_add_number = 3;
macro_build (&expr1, "ori", "t,r,i", AT, op[2], BFD_RELOC_LO16);
expr1.X_add_number = 2;
macro_build (&expr1, "xori", "t,r,i", AT, AT, BFD_RELOC_LO16);
- macro_build (NULL, "ctc1", "t,G", AT, RA);
+ macro_build (NULL, "ctc1", "t,G", AT, FCSR);
macro_build (NULL, "nop", "");
macro_build (NULL, mask == M_TRUNCWD ? "cvt.w.d" : "cvt.w.s", "D,S",
op[0], op[1]);
- macro_build (NULL, "ctc1", "t,G", op[2], RA);
+ macro_build (NULL, "ctc1", "t,G", op[2], FCSR);
macro_build (NULL, "nop", "");
end_noreorder ();
break;
^ permalink raw reply [flat|nested] 19+ messages in thread
* [committed 02/18] microMIPS/opcodes: Refer FPRs rather than FCRs with DMTC1
2021-05-29 1:36 [committed 00/18] MIPS coprocessor opcodes handling fixes Maciej W. Rozycki
2021-05-29 1:36 ` [committed 01/18] MIPS/GAS: Use FCSR rather than RA with CFC1/CTC1 Maciej W. Rozycki
@ 2021-05-29 1:36 ` Maciej W. Rozycki
2021-05-29 1:36 ` [committed 03/18] MIPS/opcodes: Free up redundant `g' operand code Maciej W. Rozycki
` (15 subsequent siblings)
17 siblings, 0 replies; 19+ messages in thread
From: Maciej W. Rozycki @ 2021-05-29 1:36 UTC (permalink / raw)
To: binutils
The DMTC1 instruction operates on a floating-point general register as
its second operand, however in the disassembly of the microMIPS encoding
a floating-point control register is shown instead. This is due to an
incorrect ordering of the two "dmtc1" entries in the opcode table, which
gives precedence to one using the `G' aka coprocessor format over one
using the `S' or floating-point register format.
The coprocessor format, or OP_REG_COPRO, is used so that GAS supports
referring to FPRs by their numbers in assembly, such as $0, $1, etc.
however in the case of CP1/FPU it is also used by the disassembler to
decode those numbers to the names of corresponding control registers.
This in turn causes nonsensical disassembly such as:
dmtc1 a1,c1_fir
in a reference to $f0. It has been like this ever since microMIPS ISA
support has been added.
Correct the ordering of the two entries then by swapping them with each
other, making disassembly output consistent with the regular MIPS DMTC1
instruction as well all the remaining CP1 move instructions. Adjust all
the test cases affected accordingly.
opcodes/
* micromips-opc.c (micromips_opcodes): Swap the two "dmtc1"
entries with each other.
gas/
* testsuite/gas/mips/micromips.d: Update disassembly according
to "dmtc1" entry fix with opcodes.
* testsuite/gas/mips/micromips-compact.d: Likewise.
* testsuite/gas/mips/micromips-insn32.d: Likewise.
* testsuite/gas/mips/micromips-noinsn32.d: Likewise.
* testsuite/gas/mips/micromips-trap.d: Likewise.
* testsuite/gas/mips/micromips@isa-override-1.d: Likewise.
---
gas/testsuite/gas/mips/micromips-compact.d | 128 +++++++++++-----------
gas/testsuite/gas/mips/micromips-insn32.d | 128 +++++++++++-----------
gas/testsuite/gas/mips/micromips-noinsn32.d | 128 +++++++++++-----------
gas/testsuite/gas/mips/micromips-trap.d | 128 +++++++++++-----------
gas/testsuite/gas/mips/micromips.d | 128 +++++++++++-----------
gas/testsuite/gas/mips/micromips@isa-override-1.d | 2
opcodes/micromips-opc.c | 2
7 files changed, 322 insertions(+), 322 deletions(-)
binutils-umips-opcodes-dmtc1.diff
Index: binutils-gdb/gas/testsuite/gas/mips/micromips-compact.d
===================================================================
--- binutils-gdb.orig/gas/testsuite/gas/mips/micromips-compact.d
+++ binutils-gdb/gas/testsuite/gas/mips/micromips-compact.d
@@ -6765,70 +6765,70 @@
[ 0-9a-f]+: 54bd 243b dmfc1 a1,\$f29
[ 0-9a-f]+: 54be 243b dmfc1 a1,\$f30
[ 0-9a-f]+: 54bf 243b dmfc1 a1,\$f31
-[ 0-9a-f]+: 54a0 2c3b dmtc1 a1,c1_fir
-[ 0-9a-f]+: 54a1 2c3b dmtc1 a1,c1_ufr
-[ 0-9a-f]+: 54a2 2c3b dmtc1 a1,\$2
-[ 0-9a-f]+: 54a3 2c3b dmtc1 a1,\$3
-[ 0-9a-f]+: 54a4 2c3b dmtc1 a1,c1_unfr
-[ 0-9a-f]+: 54a5 2c3b dmtc1 a1,\$5
-[ 0-9a-f]+: 54a6 2c3b dmtc1 a1,\$6
-[ 0-9a-f]+: 54a7 2c3b dmtc1 a1,\$7
-[ 0-9a-f]+: 54a8 2c3b dmtc1 a1,\$8
-[ 0-9a-f]+: 54a9 2c3b dmtc1 a1,\$9
-[ 0-9a-f]+: 54aa 2c3b dmtc1 a1,\$10
-[ 0-9a-f]+: 54ab 2c3b dmtc1 a1,\$11
-[ 0-9a-f]+: 54ac 2c3b dmtc1 a1,\$12
-[ 0-9a-f]+: 54ad 2c3b dmtc1 a1,\$13
-[ 0-9a-f]+: 54ae 2c3b dmtc1 a1,\$14
-[ 0-9a-f]+: 54af 2c3b dmtc1 a1,\$15
-[ 0-9a-f]+: 54b0 2c3b dmtc1 a1,\$16
-[ 0-9a-f]+: 54b1 2c3b dmtc1 a1,\$17
-[ 0-9a-f]+: 54b2 2c3b dmtc1 a1,\$18
-[ 0-9a-f]+: 54b3 2c3b dmtc1 a1,\$19
-[ 0-9a-f]+: 54b4 2c3b dmtc1 a1,\$20
-[ 0-9a-f]+: 54b5 2c3b dmtc1 a1,\$21
-[ 0-9a-f]+: 54b6 2c3b dmtc1 a1,\$22
-[ 0-9a-f]+: 54b7 2c3b dmtc1 a1,\$23
-[ 0-9a-f]+: 54b8 2c3b dmtc1 a1,\$24
-[ 0-9a-f]+: 54b9 2c3b dmtc1 a1,c1_fccr
-[ 0-9a-f]+: 54ba 2c3b dmtc1 a1,c1_fexr
-[ 0-9a-f]+: 54bb 2c3b dmtc1 a1,\$27
-[ 0-9a-f]+: 54bc 2c3b dmtc1 a1,c1_fenr
-[ 0-9a-f]+: 54bd 2c3b dmtc1 a1,\$29
-[ 0-9a-f]+: 54be 2c3b dmtc1 a1,\$30
-[ 0-9a-f]+: 54bf 2c3b dmtc1 a1,c1_fcsr
-[ 0-9a-f]+: 54a0 2c3b dmtc1 a1,c1_fir
-[ 0-9a-f]+: 54a1 2c3b dmtc1 a1,c1_ufr
-[ 0-9a-f]+: 54a2 2c3b dmtc1 a1,\$2
-[ 0-9a-f]+: 54a3 2c3b dmtc1 a1,\$3
-[ 0-9a-f]+: 54a4 2c3b dmtc1 a1,c1_unfr
-[ 0-9a-f]+: 54a5 2c3b dmtc1 a1,\$5
-[ 0-9a-f]+: 54a6 2c3b dmtc1 a1,\$6
-[ 0-9a-f]+: 54a7 2c3b dmtc1 a1,\$7
-[ 0-9a-f]+: 54a8 2c3b dmtc1 a1,\$8
-[ 0-9a-f]+: 54a9 2c3b dmtc1 a1,\$9
-[ 0-9a-f]+: 54aa 2c3b dmtc1 a1,\$10
-[ 0-9a-f]+: 54ab 2c3b dmtc1 a1,\$11
-[ 0-9a-f]+: 54ac 2c3b dmtc1 a1,\$12
-[ 0-9a-f]+: 54ad 2c3b dmtc1 a1,\$13
-[ 0-9a-f]+: 54ae 2c3b dmtc1 a1,\$14
-[ 0-9a-f]+: 54af 2c3b dmtc1 a1,\$15
-[ 0-9a-f]+: 54b0 2c3b dmtc1 a1,\$16
-[ 0-9a-f]+: 54b1 2c3b dmtc1 a1,\$17
-[ 0-9a-f]+: 54b2 2c3b dmtc1 a1,\$18
-[ 0-9a-f]+: 54b3 2c3b dmtc1 a1,\$19
-[ 0-9a-f]+: 54b4 2c3b dmtc1 a1,\$20
-[ 0-9a-f]+: 54b5 2c3b dmtc1 a1,\$21
-[ 0-9a-f]+: 54b6 2c3b dmtc1 a1,\$22
-[ 0-9a-f]+: 54b7 2c3b dmtc1 a1,\$23
-[ 0-9a-f]+: 54b8 2c3b dmtc1 a1,\$24
-[ 0-9a-f]+: 54b9 2c3b dmtc1 a1,c1_fccr
-[ 0-9a-f]+: 54ba 2c3b dmtc1 a1,c1_fexr
-[ 0-9a-f]+: 54bb 2c3b dmtc1 a1,\$27
-[ 0-9a-f]+: 54bc 2c3b dmtc1 a1,c1_fenr
-[ 0-9a-f]+: 54bd 2c3b dmtc1 a1,\$29
-[ 0-9a-f]+: 54be 2c3b dmtc1 a1,\$30
-[ 0-9a-f]+: 54bf 2c3b dmtc1 a1,c1_fcsr
+[ 0-9a-f]+: 54a0 2c3b dmtc1 a1,\$f0
+[ 0-9a-f]+: 54a1 2c3b dmtc1 a1,\$f1
+[ 0-9a-f]+: 54a2 2c3b dmtc1 a1,\$f2
+[ 0-9a-f]+: 54a3 2c3b dmtc1 a1,\$f3
+[ 0-9a-f]+: 54a4 2c3b dmtc1 a1,\$f4
+[ 0-9a-f]+: 54a5 2c3b dmtc1 a1,\$f5
+[ 0-9a-f]+: 54a6 2c3b dmtc1 a1,\$f6
+[ 0-9a-f]+: 54a7 2c3b dmtc1 a1,\$f7
+[ 0-9a-f]+: 54a8 2c3b dmtc1 a1,\$f8
+[ 0-9a-f]+: 54a9 2c3b dmtc1 a1,\$f9
+[ 0-9a-f]+: 54aa 2c3b dmtc1 a1,\$f10
+[ 0-9a-f]+: 54ab 2c3b dmtc1 a1,\$f11
+[ 0-9a-f]+: 54ac 2c3b dmtc1 a1,\$f12
+[ 0-9a-f]+: 54ad 2c3b dmtc1 a1,\$f13
+[ 0-9a-f]+: 54ae 2c3b dmtc1 a1,\$f14
+[ 0-9a-f]+: 54af 2c3b dmtc1 a1,\$f15
+[ 0-9a-f]+: 54b0 2c3b dmtc1 a1,\$f16
+[ 0-9a-f]+: 54b1 2c3b dmtc1 a1,\$f17
+[ 0-9a-f]+: 54b2 2c3b dmtc1 a1,\$f18
+[ 0-9a-f]+: 54b3 2c3b dmtc1 a1,\$f19
+[ 0-9a-f]+: 54b4 2c3b dmtc1 a1,\$f20
+[ 0-9a-f]+: 54b5 2c3b dmtc1 a1,\$f21
+[ 0-9a-f]+: 54b6 2c3b dmtc1 a1,\$f22
+[ 0-9a-f]+: 54b7 2c3b dmtc1 a1,\$f23
+[ 0-9a-f]+: 54b8 2c3b dmtc1 a1,\$f24
+[ 0-9a-f]+: 54b9 2c3b dmtc1 a1,\$f25
+[ 0-9a-f]+: 54ba 2c3b dmtc1 a1,\$f26
+[ 0-9a-f]+: 54bb 2c3b dmtc1 a1,\$f27
+[ 0-9a-f]+: 54bc 2c3b dmtc1 a1,\$f28
+[ 0-9a-f]+: 54bd 2c3b dmtc1 a1,\$f29
+[ 0-9a-f]+: 54be 2c3b dmtc1 a1,\$f30
+[ 0-9a-f]+: 54bf 2c3b dmtc1 a1,\$f31
+[ 0-9a-f]+: 54a0 2c3b dmtc1 a1,\$f0
+[ 0-9a-f]+: 54a1 2c3b dmtc1 a1,\$f1
+[ 0-9a-f]+: 54a2 2c3b dmtc1 a1,\$f2
+[ 0-9a-f]+: 54a3 2c3b dmtc1 a1,\$f3
+[ 0-9a-f]+: 54a4 2c3b dmtc1 a1,\$f4
+[ 0-9a-f]+: 54a5 2c3b dmtc1 a1,\$f5
+[ 0-9a-f]+: 54a6 2c3b dmtc1 a1,\$f6
+[ 0-9a-f]+: 54a7 2c3b dmtc1 a1,\$f7
+[ 0-9a-f]+: 54a8 2c3b dmtc1 a1,\$f8
+[ 0-9a-f]+: 54a9 2c3b dmtc1 a1,\$f9
+[ 0-9a-f]+: 54aa 2c3b dmtc1 a1,\$f10
+[ 0-9a-f]+: 54ab 2c3b dmtc1 a1,\$f11
+[ 0-9a-f]+: 54ac 2c3b dmtc1 a1,\$f12
+[ 0-9a-f]+: 54ad 2c3b dmtc1 a1,\$f13
+[ 0-9a-f]+: 54ae 2c3b dmtc1 a1,\$f14
+[ 0-9a-f]+: 54af 2c3b dmtc1 a1,\$f15
+[ 0-9a-f]+: 54b0 2c3b dmtc1 a1,\$f16
+[ 0-9a-f]+: 54b1 2c3b dmtc1 a1,\$f17
+[ 0-9a-f]+: 54b2 2c3b dmtc1 a1,\$f18
+[ 0-9a-f]+: 54b3 2c3b dmtc1 a1,\$f19
+[ 0-9a-f]+: 54b4 2c3b dmtc1 a1,\$f20
+[ 0-9a-f]+: 54b5 2c3b dmtc1 a1,\$f21
+[ 0-9a-f]+: 54b6 2c3b dmtc1 a1,\$f22
+[ 0-9a-f]+: 54b7 2c3b dmtc1 a1,\$f23
+[ 0-9a-f]+: 54b8 2c3b dmtc1 a1,\$f24
+[ 0-9a-f]+: 54b9 2c3b dmtc1 a1,\$f25
+[ 0-9a-f]+: 54ba 2c3b dmtc1 a1,\$f26
+[ 0-9a-f]+: 54bb 2c3b dmtc1 a1,\$f27
+[ 0-9a-f]+: 54bc 2c3b dmtc1 a1,\$f28
+[ 0-9a-f]+: 54bd 2c3b dmtc1 a1,\$f29
+[ 0-9a-f]+: 54be 2c3b dmtc1 a1,\$f30
+[ 0-9a-f]+: 54bf 2c3b dmtc1 a1,\$f31
[ 0-9a-f]+: 0040 6d3c dmfc2 v0,\$0
[ 0-9a-f]+: 0041 6d3c dmfc2 v0,\$1
[ 0-9a-f]+: 0042 6d3c dmfc2 v0,\$2
Index: binutils-gdb/gas/testsuite/gas/mips/micromips-insn32.d
===================================================================
--- binutils-gdb.orig/gas/testsuite/gas/mips/micromips-insn32.d
+++ binutils-gdb/gas/testsuite/gas/mips/micromips-insn32.d
@@ -6789,70 +6789,70 @@
[ 0-9a-f]+: 54bd 243b dmfc1 a1,\$f29
[ 0-9a-f]+: 54be 243b dmfc1 a1,\$f30
[ 0-9a-f]+: 54bf 243b dmfc1 a1,\$f31
-[ 0-9a-f]+: 54a0 2c3b dmtc1 a1,c1_fir
-[ 0-9a-f]+: 54a1 2c3b dmtc1 a1,c1_ufr
-[ 0-9a-f]+: 54a2 2c3b dmtc1 a1,\$2
-[ 0-9a-f]+: 54a3 2c3b dmtc1 a1,\$3
-[ 0-9a-f]+: 54a4 2c3b dmtc1 a1,c1_unfr
-[ 0-9a-f]+: 54a5 2c3b dmtc1 a1,\$5
-[ 0-9a-f]+: 54a6 2c3b dmtc1 a1,\$6
-[ 0-9a-f]+: 54a7 2c3b dmtc1 a1,\$7
-[ 0-9a-f]+: 54a8 2c3b dmtc1 a1,\$8
-[ 0-9a-f]+: 54a9 2c3b dmtc1 a1,\$9
-[ 0-9a-f]+: 54aa 2c3b dmtc1 a1,\$10
-[ 0-9a-f]+: 54ab 2c3b dmtc1 a1,\$11
-[ 0-9a-f]+: 54ac 2c3b dmtc1 a1,\$12
-[ 0-9a-f]+: 54ad 2c3b dmtc1 a1,\$13
-[ 0-9a-f]+: 54ae 2c3b dmtc1 a1,\$14
-[ 0-9a-f]+: 54af 2c3b dmtc1 a1,\$15
-[ 0-9a-f]+: 54b0 2c3b dmtc1 a1,\$16
-[ 0-9a-f]+: 54b1 2c3b dmtc1 a1,\$17
-[ 0-9a-f]+: 54b2 2c3b dmtc1 a1,\$18
-[ 0-9a-f]+: 54b3 2c3b dmtc1 a1,\$19
-[ 0-9a-f]+: 54b4 2c3b dmtc1 a1,\$20
-[ 0-9a-f]+: 54b5 2c3b dmtc1 a1,\$21
-[ 0-9a-f]+: 54b6 2c3b dmtc1 a1,\$22
-[ 0-9a-f]+: 54b7 2c3b dmtc1 a1,\$23
-[ 0-9a-f]+: 54b8 2c3b dmtc1 a1,\$24
-[ 0-9a-f]+: 54b9 2c3b dmtc1 a1,c1_fccr
-[ 0-9a-f]+: 54ba 2c3b dmtc1 a1,c1_fexr
-[ 0-9a-f]+: 54bb 2c3b dmtc1 a1,\$27
-[ 0-9a-f]+: 54bc 2c3b dmtc1 a1,c1_fenr
-[ 0-9a-f]+: 54bd 2c3b dmtc1 a1,\$29
-[ 0-9a-f]+: 54be 2c3b dmtc1 a1,\$30
-[ 0-9a-f]+: 54bf 2c3b dmtc1 a1,c1_fcsr
-[ 0-9a-f]+: 54a0 2c3b dmtc1 a1,c1_fir
-[ 0-9a-f]+: 54a1 2c3b dmtc1 a1,c1_ufr
-[ 0-9a-f]+: 54a2 2c3b dmtc1 a1,\$2
-[ 0-9a-f]+: 54a3 2c3b dmtc1 a1,\$3
-[ 0-9a-f]+: 54a4 2c3b dmtc1 a1,c1_unfr
-[ 0-9a-f]+: 54a5 2c3b dmtc1 a1,\$5
-[ 0-9a-f]+: 54a6 2c3b dmtc1 a1,\$6
-[ 0-9a-f]+: 54a7 2c3b dmtc1 a1,\$7
-[ 0-9a-f]+: 54a8 2c3b dmtc1 a1,\$8
-[ 0-9a-f]+: 54a9 2c3b dmtc1 a1,\$9
-[ 0-9a-f]+: 54aa 2c3b dmtc1 a1,\$10
-[ 0-9a-f]+: 54ab 2c3b dmtc1 a1,\$11
-[ 0-9a-f]+: 54ac 2c3b dmtc1 a1,\$12
-[ 0-9a-f]+: 54ad 2c3b dmtc1 a1,\$13
-[ 0-9a-f]+: 54ae 2c3b dmtc1 a1,\$14
-[ 0-9a-f]+: 54af 2c3b dmtc1 a1,\$15
-[ 0-9a-f]+: 54b0 2c3b dmtc1 a1,\$16
-[ 0-9a-f]+: 54b1 2c3b dmtc1 a1,\$17
-[ 0-9a-f]+: 54b2 2c3b dmtc1 a1,\$18
-[ 0-9a-f]+: 54b3 2c3b dmtc1 a1,\$19
-[ 0-9a-f]+: 54b4 2c3b dmtc1 a1,\$20
-[ 0-9a-f]+: 54b5 2c3b dmtc1 a1,\$21
-[ 0-9a-f]+: 54b6 2c3b dmtc1 a1,\$22
-[ 0-9a-f]+: 54b7 2c3b dmtc1 a1,\$23
-[ 0-9a-f]+: 54b8 2c3b dmtc1 a1,\$24
-[ 0-9a-f]+: 54b9 2c3b dmtc1 a1,c1_fccr
-[ 0-9a-f]+: 54ba 2c3b dmtc1 a1,c1_fexr
-[ 0-9a-f]+: 54bb 2c3b dmtc1 a1,\$27
-[ 0-9a-f]+: 54bc 2c3b dmtc1 a1,c1_fenr
-[ 0-9a-f]+: 54bd 2c3b dmtc1 a1,\$29
-[ 0-9a-f]+: 54be 2c3b dmtc1 a1,\$30
-[ 0-9a-f]+: 54bf 2c3b dmtc1 a1,c1_fcsr
+[ 0-9a-f]+: 54a0 2c3b dmtc1 a1,\$f0
+[ 0-9a-f]+: 54a1 2c3b dmtc1 a1,\$f1
+[ 0-9a-f]+: 54a2 2c3b dmtc1 a1,\$f2
+[ 0-9a-f]+: 54a3 2c3b dmtc1 a1,\$f3
+[ 0-9a-f]+: 54a4 2c3b dmtc1 a1,\$f4
+[ 0-9a-f]+: 54a5 2c3b dmtc1 a1,\$f5
+[ 0-9a-f]+: 54a6 2c3b dmtc1 a1,\$f6
+[ 0-9a-f]+: 54a7 2c3b dmtc1 a1,\$f7
+[ 0-9a-f]+: 54a8 2c3b dmtc1 a1,\$f8
+[ 0-9a-f]+: 54a9 2c3b dmtc1 a1,\$f9
+[ 0-9a-f]+: 54aa 2c3b dmtc1 a1,\$f10
+[ 0-9a-f]+: 54ab 2c3b dmtc1 a1,\$f11
+[ 0-9a-f]+: 54ac 2c3b dmtc1 a1,\$f12
+[ 0-9a-f]+: 54ad 2c3b dmtc1 a1,\$f13
+[ 0-9a-f]+: 54ae 2c3b dmtc1 a1,\$f14
+[ 0-9a-f]+: 54af 2c3b dmtc1 a1,\$f15
+[ 0-9a-f]+: 54b0 2c3b dmtc1 a1,\$f16
+[ 0-9a-f]+: 54b1 2c3b dmtc1 a1,\$f17
+[ 0-9a-f]+: 54b2 2c3b dmtc1 a1,\$f18
+[ 0-9a-f]+: 54b3 2c3b dmtc1 a1,\$f19
+[ 0-9a-f]+: 54b4 2c3b dmtc1 a1,\$f20
+[ 0-9a-f]+: 54b5 2c3b dmtc1 a1,\$f21
+[ 0-9a-f]+: 54b6 2c3b dmtc1 a1,\$f22
+[ 0-9a-f]+: 54b7 2c3b dmtc1 a1,\$f23
+[ 0-9a-f]+: 54b8 2c3b dmtc1 a1,\$f24
+[ 0-9a-f]+: 54b9 2c3b dmtc1 a1,\$f25
+[ 0-9a-f]+: 54ba 2c3b dmtc1 a1,\$f26
+[ 0-9a-f]+: 54bb 2c3b dmtc1 a1,\$f27
+[ 0-9a-f]+: 54bc 2c3b dmtc1 a1,\$f28
+[ 0-9a-f]+: 54bd 2c3b dmtc1 a1,\$f29
+[ 0-9a-f]+: 54be 2c3b dmtc1 a1,\$f30
+[ 0-9a-f]+: 54bf 2c3b dmtc1 a1,\$f31
+[ 0-9a-f]+: 54a0 2c3b dmtc1 a1,\$f0
+[ 0-9a-f]+: 54a1 2c3b dmtc1 a1,\$f1
+[ 0-9a-f]+: 54a2 2c3b dmtc1 a1,\$f2
+[ 0-9a-f]+: 54a3 2c3b dmtc1 a1,\$f3
+[ 0-9a-f]+: 54a4 2c3b dmtc1 a1,\$f4
+[ 0-9a-f]+: 54a5 2c3b dmtc1 a1,\$f5
+[ 0-9a-f]+: 54a6 2c3b dmtc1 a1,\$f6
+[ 0-9a-f]+: 54a7 2c3b dmtc1 a1,\$f7
+[ 0-9a-f]+: 54a8 2c3b dmtc1 a1,\$f8
+[ 0-9a-f]+: 54a9 2c3b dmtc1 a1,\$f9
+[ 0-9a-f]+: 54aa 2c3b dmtc1 a1,\$f10
+[ 0-9a-f]+: 54ab 2c3b dmtc1 a1,\$f11
+[ 0-9a-f]+: 54ac 2c3b dmtc1 a1,\$f12
+[ 0-9a-f]+: 54ad 2c3b dmtc1 a1,\$f13
+[ 0-9a-f]+: 54ae 2c3b dmtc1 a1,\$f14
+[ 0-9a-f]+: 54af 2c3b dmtc1 a1,\$f15
+[ 0-9a-f]+: 54b0 2c3b dmtc1 a1,\$f16
+[ 0-9a-f]+: 54b1 2c3b dmtc1 a1,\$f17
+[ 0-9a-f]+: 54b2 2c3b dmtc1 a1,\$f18
+[ 0-9a-f]+: 54b3 2c3b dmtc1 a1,\$f19
+[ 0-9a-f]+: 54b4 2c3b dmtc1 a1,\$f20
+[ 0-9a-f]+: 54b5 2c3b dmtc1 a1,\$f21
+[ 0-9a-f]+: 54b6 2c3b dmtc1 a1,\$f22
+[ 0-9a-f]+: 54b7 2c3b dmtc1 a1,\$f23
+[ 0-9a-f]+: 54b8 2c3b dmtc1 a1,\$f24
+[ 0-9a-f]+: 54b9 2c3b dmtc1 a1,\$f25
+[ 0-9a-f]+: 54ba 2c3b dmtc1 a1,\$f26
+[ 0-9a-f]+: 54bb 2c3b dmtc1 a1,\$f27
+[ 0-9a-f]+: 54bc 2c3b dmtc1 a1,\$f28
+[ 0-9a-f]+: 54bd 2c3b dmtc1 a1,\$f29
+[ 0-9a-f]+: 54be 2c3b dmtc1 a1,\$f30
+[ 0-9a-f]+: 54bf 2c3b dmtc1 a1,\$f31
[ 0-9a-f]+: 0040 6d3c dmfc2 v0,\$0
[ 0-9a-f]+: 0041 6d3c dmfc2 v0,\$1
[ 0-9a-f]+: 0042 6d3c dmfc2 v0,\$2
Index: binutils-gdb/gas/testsuite/gas/mips/micromips-noinsn32.d
===================================================================
--- binutils-gdb.orig/gas/testsuite/gas/mips/micromips-noinsn32.d
+++ binutils-gdb/gas/testsuite/gas/mips/micromips-noinsn32.d
@@ -6766,70 +6766,70 @@
[ 0-9a-f]+: 54bd 243b dmfc1 a1,\$f29
[ 0-9a-f]+: 54be 243b dmfc1 a1,\$f30
[ 0-9a-f]+: 54bf 243b dmfc1 a1,\$f31
-[ 0-9a-f]+: 54a0 2c3b dmtc1 a1,c1_fir
-[ 0-9a-f]+: 54a1 2c3b dmtc1 a1,c1_ufr
-[ 0-9a-f]+: 54a2 2c3b dmtc1 a1,\$2
-[ 0-9a-f]+: 54a3 2c3b dmtc1 a1,\$3
-[ 0-9a-f]+: 54a4 2c3b dmtc1 a1,c1_unfr
-[ 0-9a-f]+: 54a5 2c3b dmtc1 a1,\$5
-[ 0-9a-f]+: 54a6 2c3b dmtc1 a1,\$6
-[ 0-9a-f]+: 54a7 2c3b dmtc1 a1,\$7
-[ 0-9a-f]+: 54a8 2c3b dmtc1 a1,\$8
-[ 0-9a-f]+: 54a9 2c3b dmtc1 a1,\$9
-[ 0-9a-f]+: 54aa 2c3b dmtc1 a1,\$10
-[ 0-9a-f]+: 54ab 2c3b dmtc1 a1,\$11
-[ 0-9a-f]+: 54ac 2c3b dmtc1 a1,\$12
-[ 0-9a-f]+: 54ad 2c3b dmtc1 a1,\$13
-[ 0-9a-f]+: 54ae 2c3b dmtc1 a1,\$14
-[ 0-9a-f]+: 54af 2c3b dmtc1 a1,\$15
-[ 0-9a-f]+: 54b0 2c3b dmtc1 a1,\$16
-[ 0-9a-f]+: 54b1 2c3b dmtc1 a1,\$17
-[ 0-9a-f]+: 54b2 2c3b dmtc1 a1,\$18
-[ 0-9a-f]+: 54b3 2c3b dmtc1 a1,\$19
-[ 0-9a-f]+: 54b4 2c3b dmtc1 a1,\$20
-[ 0-9a-f]+: 54b5 2c3b dmtc1 a1,\$21
-[ 0-9a-f]+: 54b6 2c3b dmtc1 a1,\$22
-[ 0-9a-f]+: 54b7 2c3b dmtc1 a1,\$23
-[ 0-9a-f]+: 54b8 2c3b dmtc1 a1,\$24
-[ 0-9a-f]+: 54b9 2c3b dmtc1 a1,c1_fccr
-[ 0-9a-f]+: 54ba 2c3b dmtc1 a1,c1_fexr
-[ 0-9a-f]+: 54bb 2c3b dmtc1 a1,\$27
-[ 0-9a-f]+: 54bc 2c3b dmtc1 a1,c1_fenr
-[ 0-9a-f]+: 54bd 2c3b dmtc1 a1,\$29
-[ 0-9a-f]+: 54be 2c3b dmtc1 a1,\$30
-[ 0-9a-f]+: 54bf 2c3b dmtc1 a1,c1_fcsr
-[ 0-9a-f]+: 54a0 2c3b dmtc1 a1,c1_fir
-[ 0-9a-f]+: 54a1 2c3b dmtc1 a1,c1_ufr
-[ 0-9a-f]+: 54a2 2c3b dmtc1 a1,\$2
-[ 0-9a-f]+: 54a3 2c3b dmtc1 a1,\$3
-[ 0-9a-f]+: 54a4 2c3b dmtc1 a1,c1_unfr
-[ 0-9a-f]+: 54a5 2c3b dmtc1 a1,\$5
-[ 0-9a-f]+: 54a6 2c3b dmtc1 a1,\$6
-[ 0-9a-f]+: 54a7 2c3b dmtc1 a1,\$7
-[ 0-9a-f]+: 54a8 2c3b dmtc1 a1,\$8
-[ 0-9a-f]+: 54a9 2c3b dmtc1 a1,\$9
-[ 0-9a-f]+: 54aa 2c3b dmtc1 a1,\$10
-[ 0-9a-f]+: 54ab 2c3b dmtc1 a1,\$11
-[ 0-9a-f]+: 54ac 2c3b dmtc1 a1,\$12
-[ 0-9a-f]+: 54ad 2c3b dmtc1 a1,\$13
-[ 0-9a-f]+: 54ae 2c3b dmtc1 a1,\$14
-[ 0-9a-f]+: 54af 2c3b dmtc1 a1,\$15
-[ 0-9a-f]+: 54b0 2c3b dmtc1 a1,\$16
-[ 0-9a-f]+: 54b1 2c3b dmtc1 a1,\$17
-[ 0-9a-f]+: 54b2 2c3b dmtc1 a1,\$18
-[ 0-9a-f]+: 54b3 2c3b dmtc1 a1,\$19
-[ 0-9a-f]+: 54b4 2c3b dmtc1 a1,\$20
-[ 0-9a-f]+: 54b5 2c3b dmtc1 a1,\$21
-[ 0-9a-f]+: 54b6 2c3b dmtc1 a1,\$22
-[ 0-9a-f]+: 54b7 2c3b dmtc1 a1,\$23
-[ 0-9a-f]+: 54b8 2c3b dmtc1 a1,\$24
-[ 0-9a-f]+: 54b9 2c3b dmtc1 a1,c1_fccr
-[ 0-9a-f]+: 54ba 2c3b dmtc1 a1,c1_fexr
-[ 0-9a-f]+: 54bb 2c3b dmtc1 a1,\$27
-[ 0-9a-f]+: 54bc 2c3b dmtc1 a1,c1_fenr
-[ 0-9a-f]+: 54bd 2c3b dmtc1 a1,\$29
-[ 0-9a-f]+: 54be 2c3b dmtc1 a1,\$30
-[ 0-9a-f]+: 54bf 2c3b dmtc1 a1,c1_fcsr
+[ 0-9a-f]+: 54a0 2c3b dmtc1 a1,\$f0
+[ 0-9a-f]+: 54a1 2c3b dmtc1 a1,\$f1
+[ 0-9a-f]+: 54a2 2c3b dmtc1 a1,\$f2
+[ 0-9a-f]+: 54a3 2c3b dmtc1 a1,\$f3
+[ 0-9a-f]+: 54a4 2c3b dmtc1 a1,\$f4
+[ 0-9a-f]+: 54a5 2c3b dmtc1 a1,\$f5
+[ 0-9a-f]+: 54a6 2c3b dmtc1 a1,\$f6
+[ 0-9a-f]+: 54a7 2c3b dmtc1 a1,\$f7
+[ 0-9a-f]+: 54a8 2c3b dmtc1 a1,\$f8
+[ 0-9a-f]+: 54a9 2c3b dmtc1 a1,\$f9
+[ 0-9a-f]+: 54aa 2c3b dmtc1 a1,\$f10
+[ 0-9a-f]+: 54ab 2c3b dmtc1 a1,\$f11
+[ 0-9a-f]+: 54ac 2c3b dmtc1 a1,\$f12
+[ 0-9a-f]+: 54ad 2c3b dmtc1 a1,\$f13
+[ 0-9a-f]+: 54ae 2c3b dmtc1 a1,\$f14
+[ 0-9a-f]+: 54af 2c3b dmtc1 a1,\$f15
+[ 0-9a-f]+: 54b0 2c3b dmtc1 a1,\$f16
+[ 0-9a-f]+: 54b1 2c3b dmtc1 a1,\$f17
+[ 0-9a-f]+: 54b2 2c3b dmtc1 a1,\$f18
+[ 0-9a-f]+: 54b3 2c3b dmtc1 a1,\$f19
+[ 0-9a-f]+: 54b4 2c3b dmtc1 a1,\$f20
+[ 0-9a-f]+: 54b5 2c3b dmtc1 a1,\$f21
+[ 0-9a-f]+: 54b6 2c3b dmtc1 a1,\$f22
+[ 0-9a-f]+: 54b7 2c3b dmtc1 a1,\$f23
+[ 0-9a-f]+: 54b8 2c3b dmtc1 a1,\$f24
+[ 0-9a-f]+: 54b9 2c3b dmtc1 a1,\$f25
+[ 0-9a-f]+: 54ba 2c3b dmtc1 a1,\$f26
+[ 0-9a-f]+: 54bb 2c3b dmtc1 a1,\$f27
+[ 0-9a-f]+: 54bc 2c3b dmtc1 a1,\$f28
+[ 0-9a-f]+: 54bd 2c3b dmtc1 a1,\$f29
+[ 0-9a-f]+: 54be 2c3b dmtc1 a1,\$f30
+[ 0-9a-f]+: 54bf 2c3b dmtc1 a1,\$f31
+[ 0-9a-f]+: 54a0 2c3b dmtc1 a1,\$f0
+[ 0-9a-f]+: 54a1 2c3b dmtc1 a1,\$f1
+[ 0-9a-f]+: 54a2 2c3b dmtc1 a1,\$f2
+[ 0-9a-f]+: 54a3 2c3b dmtc1 a1,\$f3
+[ 0-9a-f]+: 54a4 2c3b dmtc1 a1,\$f4
+[ 0-9a-f]+: 54a5 2c3b dmtc1 a1,\$f5
+[ 0-9a-f]+: 54a6 2c3b dmtc1 a1,\$f6
+[ 0-9a-f]+: 54a7 2c3b dmtc1 a1,\$f7
+[ 0-9a-f]+: 54a8 2c3b dmtc1 a1,\$f8
+[ 0-9a-f]+: 54a9 2c3b dmtc1 a1,\$f9
+[ 0-9a-f]+: 54aa 2c3b dmtc1 a1,\$f10
+[ 0-9a-f]+: 54ab 2c3b dmtc1 a1,\$f11
+[ 0-9a-f]+: 54ac 2c3b dmtc1 a1,\$f12
+[ 0-9a-f]+: 54ad 2c3b dmtc1 a1,\$f13
+[ 0-9a-f]+: 54ae 2c3b dmtc1 a1,\$f14
+[ 0-9a-f]+: 54af 2c3b dmtc1 a1,\$f15
+[ 0-9a-f]+: 54b0 2c3b dmtc1 a1,\$f16
+[ 0-9a-f]+: 54b1 2c3b dmtc1 a1,\$f17
+[ 0-9a-f]+: 54b2 2c3b dmtc1 a1,\$f18
+[ 0-9a-f]+: 54b3 2c3b dmtc1 a1,\$f19
+[ 0-9a-f]+: 54b4 2c3b dmtc1 a1,\$f20
+[ 0-9a-f]+: 54b5 2c3b dmtc1 a1,\$f21
+[ 0-9a-f]+: 54b6 2c3b dmtc1 a1,\$f22
+[ 0-9a-f]+: 54b7 2c3b dmtc1 a1,\$f23
+[ 0-9a-f]+: 54b8 2c3b dmtc1 a1,\$f24
+[ 0-9a-f]+: 54b9 2c3b dmtc1 a1,\$f25
+[ 0-9a-f]+: 54ba 2c3b dmtc1 a1,\$f26
+[ 0-9a-f]+: 54bb 2c3b dmtc1 a1,\$f27
+[ 0-9a-f]+: 54bc 2c3b dmtc1 a1,\$f28
+[ 0-9a-f]+: 54bd 2c3b dmtc1 a1,\$f29
+[ 0-9a-f]+: 54be 2c3b dmtc1 a1,\$f30
+[ 0-9a-f]+: 54bf 2c3b dmtc1 a1,\$f31
[ 0-9a-f]+: 0040 6d3c dmfc2 v0,\$0
[ 0-9a-f]+: 0041 6d3c dmfc2 v0,\$1
[ 0-9a-f]+: 0042 6d3c dmfc2 v0,\$2
Index: binutils-gdb/gas/testsuite/gas/mips/micromips-trap.d
===================================================================
--- binutils-gdb.orig/gas/testsuite/gas/mips/micromips-trap.d
+++ binutils-gdb/gas/testsuite/gas/mips/micromips-trap.d
@@ -6757,70 +6757,70 @@
[ 0-9a-f]+: 54bd 243b dmfc1 a1,\$f29
[ 0-9a-f]+: 54be 243b dmfc1 a1,\$f30
[ 0-9a-f]+: 54bf 243b dmfc1 a1,\$f31
-[ 0-9a-f]+: 54a0 2c3b dmtc1 a1,c1_fir
-[ 0-9a-f]+: 54a1 2c3b dmtc1 a1,c1_ufr
-[ 0-9a-f]+: 54a2 2c3b dmtc1 a1,\$2
-[ 0-9a-f]+: 54a3 2c3b dmtc1 a1,\$3
-[ 0-9a-f]+: 54a4 2c3b dmtc1 a1,c1_unfr
-[ 0-9a-f]+: 54a5 2c3b dmtc1 a1,\$5
-[ 0-9a-f]+: 54a6 2c3b dmtc1 a1,\$6
-[ 0-9a-f]+: 54a7 2c3b dmtc1 a1,\$7
-[ 0-9a-f]+: 54a8 2c3b dmtc1 a1,\$8
-[ 0-9a-f]+: 54a9 2c3b dmtc1 a1,\$9
-[ 0-9a-f]+: 54aa 2c3b dmtc1 a1,\$10
-[ 0-9a-f]+: 54ab 2c3b dmtc1 a1,\$11
-[ 0-9a-f]+: 54ac 2c3b dmtc1 a1,\$12
-[ 0-9a-f]+: 54ad 2c3b dmtc1 a1,\$13
-[ 0-9a-f]+: 54ae 2c3b dmtc1 a1,\$14
-[ 0-9a-f]+: 54af 2c3b dmtc1 a1,\$15
-[ 0-9a-f]+: 54b0 2c3b dmtc1 a1,\$16
-[ 0-9a-f]+: 54b1 2c3b dmtc1 a1,\$17
-[ 0-9a-f]+: 54b2 2c3b dmtc1 a1,\$18
-[ 0-9a-f]+: 54b3 2c3b dmtc1 a1,\$19
-[ 0-9a-f]+: 54b4 2c3b dmtc1 a1,\$20
-[ 0-9a-f]+: 54b5 2c3b dmtc1 a1,\$21
-[ 0-9a-f]+: 54b6 2c3b dmtc1 a1,\$22
-[ 0-9a-f]+: 54b7 2c3b dmtc1 a1,\$23
-[ 0-9a-f]+: 54b8 2c3b dmtc1 a1,\$24
-[ 0-9a-f]+: 54b9 2c3b dmtc1 a1,c1_fccr
-[ 0-9a-f]+: 54ba 2c3b dmtc1 a1,c1_fexr
-[ 0-9a-f]+: 54bb 2c3b dmtc1 a1,\$27
-[ 0-9a-f]+: 54bc 2c3b dmtc1 a1,c1_fenr
-[ 0-9a-f]+: 54bd 2c3b dmtc1 a1,\$29
-[ 0-9a-f]+: 54be 2c3b dmtc1 a1,\$30
-[ 0-9a-f]+: 54bf 2c3b dmtc1 a1,c1_fcsr
-[ 0-9a-f]+: 54a0 2c3b dmtc1 a1,c1_fir
-[ 0-9a-f]+: 54a1 2c3b dmtc1 a1,c1_ufr
-[ 0-9a-f]+: 54a2 2c3b dmtc1 a1,\$2
-[ 0-9a-f]+: 54a3 2c3b dmtc1 a1,\$3
-[ 0-9a-f]+: 54a4 2c3b dmtc1 a1,c1_unfr
-[ 0-9a-f]+: 54a5 2c3b dmtc1 a1,\$5
-[ 0-9a-f]+: 54a6 2c3b dmtc1 a1,\$6
-[ 0-9a-f]+: 54a7 2c3b dmtc1 a1,\$7
-[ 0-9a-f]+: 54a8 2c3b dmtc1 a1,\$8
-[ 0-9a-f]+: 54a9 2c3b dmtc1 a1,\$9
-[ 0-9a-f]+: 54aa 2c3b dmtc1 a1,\$10
-[ 0-9a-f]+: 54ab 2c3b dmtc1 a1,\$11
-[ 0-9a-f]+: 54ac 2c3b dmtc1 a1,\$12
-[ 0-9a-f]+: 54ad 2c3b dmtc1 a1,\$13
-[ 0-9a-f]+: 54ae 2c3b dmtc1 a1,\$14
-[ 0-9a-f]+: 54af 2c3b dmtc1 a1,\$15
-[ 0-9a-f]+: 54b0 2c3b dmtc1 a1,\$16
-[ 0-9a-f]+: 54b1 2c3b dmtc1 a1,\$17
-[ 0-9a-f]+: 54b2 2c3b dmtc1 a1,\$18
-[ 0-9a-f]+: 54b3 2c3b dmtc1 a1,\$19
-[ 0-9a-f]+: 54b4 2c3b dmtc1 a1,\$20
-[ 0-9a-f]+: 54b5 2c3b dmtc1 a1,\$21
-[ 0-9a-f]+: 54b6 2c3b dmtc1 a1,\$22
-[ 0-9a-f]+: 54b7 2c3b dmtc1 a1,\$23
-[ 0-9a-f]+: 54b8 2c3b dmtc1 a1,\$24
-[ 0-9a-f]+: 54b9 2c3b dmtc1 a1,c1_fccr
-[ 0-9a-f]+: 54ba 2c3b dmtc1 a1,c1_fexr
-[ 0-9a-f]+: 54bb 2c3b dmtc1 a1,\$27
-[ 0-9a-f]+: 54bc 2c3b dmtc1 a1,c1_fenr
-[ 0-9a-f]+: 54bd 2c3b dmtc1 a1,\$29
-[ 0-9a-f]+: 54be 2c3b dmtc1 a1,\$30
-[ 0-9a-f]+: 54bf 2c3b dmtc1 a1,c1_fcsr
+[ 0-9a-f]+: 54a0 2c3b dmtc1 a1,\$f0
+[ 0-9a-f]+: 54a1 2c3b dmtc1 a1,\$f1
+[ 0-9a-f]+: 54a2 2c3b dmtc1 a1,\$f2
+[ 0-9a-f]+: 54a3 2c3b dmtc1 a1,\$f3
+[ 0-9a-f]+: 54a4 2c3b dmtc1 a1,\$f4
+[ 0-9a-f]+: 54a5 2c3b dmtc1 a1,\$f5
+[ 0-9a-f]+: 54a6 2c3b dmtc1 a1,\$f6
+[ 0-9a-f]+: 54a7 2c3b dmtc1 a1,\$f7
+[ 0-9a-f]+: 54a8 2c3b dmtc1 a1,\$f8
+[ 0-9a-f]+: 54a9 2c3b dmtc1 a1,\$f9
+[ 0-9a-f]+: 54aa 2c3b dmtc1 a1,\$f10
+[ 0-9a-f]+: 54ab 2c3b dmtc1 a1,\$f11
+[ 0-9a-f]+: 54ac 2c3b dmtc1 a1,\$f12
+[ 0-9a-f]+: 54ad 2c3b dmtc1 a1,\$f13
+[ 0-9a-f]+: 54ae 2c3b dmtc1 a1,\$f14
+[ 0-9a-f]+: 54af 2c3b dmtc1 a1,\$f15
+[ 0-9a-f]+: 54b0 2c3b dmtc1 a1,\$f16
+[ 0-9a-f]+: 54b1 2c3b dmtc1 a1,\$f17
+[ 0-9a-f]+: 54b2 2c3b dmtc1 a1,\$f18
+[ 0-9a-f]+: 54b3 2c3b dmtc1 a1,\$f19
+[ 0-9a-f]+: 54b4 2c3b dmtc1 a1,\$f20
+[ 0-9a-f]+: 54b5 2c3b dmtc1 a1,\$f21
+[ 0-9a-f]+: 54b6 2c3b dmtc1 a1,\$f22
+[ 0-9a-f]+: 54b7 2c3b dmtc1 a1,\$f23
+[ 0-9a-f]+: 54b8 2c3b dmtc1 a1,\$f24
+[ 0-9a-f]+: 54b9 2c3b dmtc1 a1,\$f25
+[ 0-9a-f]+: 54ba 2c3b dmtc1 a1,\$f26
+[ 0-9a-f]+: 54bb 2c3b dmtc1 a1,\$f27
+[ 0-9a-f]+: 54bc 2c3b dmtc1 a1,\$f28
+[ 0-9a-f]+: 54bd 2c3b dmtc1 a1,\$f29
+[ 0-9a-f]+: 54be 2c3b dmtc1 a1,\$f30
+[ 0-9a-f]+: 54bf 2c3b dmtc1 a1,\$f31
+[ 0-9a-f]+: 54a0 2c3b dmtc1 a1,\$f0
+[ 0-9a-f]+: 54a1 2c3b dmtc1 a1,\$f1
+[ 0-9a-f]+: 54a2 2c3b dmtc1 a1,\$f2
+[ 0-9a-f]+: 54a3 2c3b dmtc1 a1,\$f3
+[ 0-9a-f]+: 54a4 2c3b dmtc1 a1,\$f4
+[ 0-9a-f]+: 54a5 2c3b dmtc1 a1,\$f5
+[ 0-9a-f]+: 54a6 2c3b dmtc1 a1,\$f6
+[ 0-9a-f]+: 54a7 2c3b dmtc1 a1,\$f7
+[ 0-9a-f]+: 54a8 2c3b dmtc1 a1,\$f8
+[ 0-9a-f]+: 54a9 2c3b dmtc1 a1,\$f9
+[ 0-9a-f]+: 54aa 2c3b dmtc1 a1,\$f10
+[ 0-9a-f]+: 54ab 2c3b dmtc1 a1,\$f11
+[ 0-9a-f]+: 54ac 2c3b dmtc1 a1,\$f12
+[ 0-9a-f]+: 54ad 2c3b dmtc1 a1,\$f13
+[ 0-9a-f]+: 54ae 2c3b dmtc1 a1,\$f14
+[ 0-9a-f]+: 54af 2c3b dmtc1 a1,\$f15
+[ 0-9a-f]+: 54b0 2c3b dmtc1 a1,\$f16
+[ 0-9a-f]+: 54b1 2c3b dmtc1 a1,\$f17
+[ 0-9a-f]+: 54b2 2c3b dmtc1 a1,\$f18
+[ 0-9a-f]+: 54b3 2c3b dmtc1 a1,\$f19
+[ 0-9a-f]+: 54b4 2c3b dmtc1 a1,\$f20
+[ 0-9a-f]+: 54b5 2c3b dmtc1 a1,\$f21
+[ 0-9a-f]+: 54b6 2c3b dmtc1 a1,\$f22
+[ 0-9a-f]+: 54b7 2c3b dmtc1 a1,\$f23
+[ 0-9a-f]+: 54b8 2c3b dmtc1 a1,\$f24
+[ 0-9a-f]+: 54b9 2c3b dmtc1 a1,\$f25
+[ 0-9a-f]+: 54ba 2c3b dmtc1 a1,\$f26
+[ 0-9a-f]+: 54bb 2c3b dmtc1 a1,\$f27
+[ 0-9a-f]+: 54bc 2c3b dmtc1 a1,\$f28
+[ 0-9a-f]+: 54bd 2c3b dmtc1 a1,\$f29
+[ 0-9a-f]+: 54be 2c3b dmtc1 a1,\$f30
+[ 0-9a-f]+: 54bf 2c3b dmtc1 a1,\$f31
[ 0-9a-f]+: 0040 6d3c dmfc2 v0,\$0
[ 0-9a-f]+: 0041 6d3c dmfc2 v0,\$1
[ 0-9a-f]+: 0042 6d3c dmfc2 v0,\$2
Index: binutils-gdb/gas/testsuite/gas/mips/micromips.d
===================================================================
--- binutils-gdb.orig/gas/testsuite/gas/mips/micromips.d
+++ binutils-gdb/gas/testsuite/gas/mips/micromips.d
@@ -6844,70 +6844,70 @@
[ 0-9a-f]+: 54bd 243b dmfc1 a1,\$f29
[ 0-9a-f]+: 54be 243b dmfc1 a1,\$f30
[ 0-9a-f]+: 54bf 243b dmfc1 a1,\$f31
-[ 0-9a-f]+: 54a0 2c3b dmtc1 a1,c1_fir
-[ 0-9a-f]+: 54a1 2c3b dmtc1 a1,c1_ufr
-[ 0-9a-f]+: 54a2 2c3b dmtc1 a1,\$2
-[ 0-9a-f]+: 54a3 2c3b dmtc1 a1,\$3
-[ 0-9a-f]+: 54a4 2c3b dmtc1 a1,c1_unfr
-[ 0-9a-f]+: 54a5 2c3b dmtc1 a1,\$5
-[ 0-9a-f]+: 54a6 2c3b dmtc1 a1,\$6
-[ 0-9a-f]+: 54a7 2c3b dmtc1 a1,\$7
-[ 0-9a-f]+: 54a8 2c3b dmtc1 a1,\$8
-[ 0-9a-f]+: 54a9 2c3b dmtc1 a1,\$9
-[ 0-9a-f]+: 54aa 2c3b dmtc1 a1,\$10
-[ 0-9a-f]+: 54ab 2c3b dmtc1 a1,\$11
-[ 0-9a-f]+: 54ac 2c3b dmtc1 a1,\$12
-[ 0-9a-f]+: 54ad 2c3b dmtc1 a1,\$13
-[ 0-9a-f]+: 54ae 2c3b dmtc1 a1,\$14
-[ 0-9a-f]+: 54af 2c3b dmtc1 a1,\$15
-[ 0-9a-f]+: 54b0 2c3b dmtc1 a1,\$16
-[ 0-9a-f]+: 54b1 2c3b dmtc1 a1,\$17
-[ 0-9a-f]+: 54b2 2c3b dmtc1 a1,\$18
-[ 0-9a-f]+: 54b3 2c3b dmtc1 a1,\$19
-[ 0-9a-f]+: 54b4 2c3b dmtc1 a1,\$20
-[ 0-9a-f]+: 54b5 2c3b dmtc1 a1,\$21
-[ 0-9a-f]+: 54b6 2c3b dmtc1 a1,\$22
-[ 0-9a-f]+: 54b7 2c3b dmtc1 a1,\$23
-[ 0-9a-f]+: 54b8 2c3b dmtc1 a1,\$24
-[ 0-9a-f]+: 54b9 2c3b dmtc1 a1,c1_fccr
-[ 0-9a-f]+: 54ba 2c3b dmtc1 a1,c1_fexr
-[ 0-9a-f]+: 54bb 2c3b dmtc1 a1,\$27
-[ 0-9a-f]+: 54bc 2c3b dmtc1 a1,c1_fenr
-[ 0-9a-f]+: 54bd 2c3b dmtc1 a1,\$29
-[ 0-9a-f]+: 54be 2c3b dmtc1 a1,\$30
-[ 0-9a-f]+: 54bf 2c3b dmtc1 a1,c1_fcsr
-[ 0-9a-f]+: 54a0 2c3b dmtc1 a1,c1_fir
-[ 0-9a-f]+: 54a1 2c3b dmtc1 a1,c1_ufr
-[ 0-9a-f]+: 54a2 2c3b dmtc1 a1,\$2
-[ 0-9a-f]+: 54a3 2c3b dmtc1 a1,\$3
-[ 0-9a-f]+: 54a4 2c3b dmtc1 a1,c1_unfr
-[ 0-9a-f]+: 54a5 2c3b dmtc1 a1,\$5
-[ 0-9a-f]+: 54a6 2c3b dmtc1 a1,\$6
-[ 0-9a-f]+: 54a7 2c3b dmtc1 a1,\$7
-[ 0-9a-f]+: 54a8 2c3b dmtc1 a1,\$8
-[ 0-9a-f]+: 54a9 2c3b dmtc1 a1,\$9
-[ 0-9a-f]+: 54aa 2c3b dmtc1 a1,\$10
-[ 0-9a-f]+: 54ab 2c3b dmtc1 a1,\$11
-[ 0-9a-f]+: 54ac 2c3b dmtc1 a1,\$12
-[ 0-9a-f]+: 54ad 2c3b dmtc1 a1,\$13
-[ 0-9a-f]+: 54ae 2c3b dmtc1 a1,\$14
-[ 0-9a-f]+: 54af 2c3b dmtc1 a1,\$15
-[ 0-9a-f]+: 54b0 2c3b dmtc1 a1,\$16
-[ 0-9a-f]+: 54b1 2c3b dmtc1 a1,\$17
-[ 0-9a-f]+: 54b2 2c3b dmtc1 a1,\$18
-[ 0-9a-f]+: 54b3 2c3b dmtc1 a1,\$19
-[ 0-9a-f]+: 54b4 2c3b dmtc1 a1,\$20
-[ 0-9a-f]+: 54b5 2c3b dmtc1 a1,\$21
-[ 0-9a-f]+: 54b6 2c3b dmtc1 a1,\$22
-[ 0-9a-f]+: 54b7 2c3b dmtc1 a1,\$23
-[ 0-9a-f]+: 54b8 2c3b dmtc1 a1,\$24
-[ 0-9a-f]+: 54b9 2c3b dmtc1 a1,c1_fccr
-[ 0-9a-f]+: 54ba 2c3b dmtc1 a1,c1_fexr
-[ 0-9a-f]+: 54bb 2c3b dmtc1 a1,\$27
-[ 0-9a-f]+: 54bc 2c3b dmtc1 a1,c1_fenr
-[ 0-9a-f]+: 54bd 2c3b dmtc1 a1,\$29
-[ 0-9a-f]+: 54be 2c3b dmtc1 a1,\$30
-[ 0-9a-f]+: 54bf 2c3b dmtc1 a1,c1_fcsr
+[ 0-9a-f]+: 54a0 2c3b dmtc1 a1,\$f0
+[ 0-9a-f]+: 54a1 2c3b dmtc1 a1,\$f1
+[ 0-9a-f]+: 54a2 2c3b dmtc1 a1,\$f2
+[ 0-9a-f]+: 54a3 2c3b dmtc1 a1,\$f3
+[ 0-9a-f]+: 54a4 2c3b dmtc1 a1,\$f4
+[ 0-9a-f]+: 54a5 2c3b dmtc1 a1,\$f5
+[ 0-9a-f]+: 54a6 2c3b dmtc1 a1,\$f6
+[ 0-9a-f]+: 54a7 2c3b dmtc1 a1,\$f7
+[ 0-9a-f]+: 54a8 2c3b dmtc1 a1,\$f8
+[ 0-9a-f]+: 54a9 2c3b dmtc1 a1,\$f9
+[ 0-9a-f]+: 54aa 2c3b dmtc1 a1,\$f10
+[ 0-9a-f]+: 54ab 2c3b dmtc1 a1,\$f11
+[ 0-9a-f]+: 54ac 2c3b dmtc1 a1,\$f12
+[ 0-9a-f]+: 54ad 2c3b dmtc1 a1,\$f13
+[ 0-9a-f]+: 54ae 2c3b dmtc1 a1,\$f14
+[ 0-9a-f]+: 54af 2c3b dmtc1 a1,\$f15
+[ 0-9a-f]+: 54b0 2c3b dmtc1 a1,\$f16
+[ 0-9a-f]+: 54b1 2c3b dmtc1 a1,\$f17
+[ 0-9a-f]+: 54b2 2c3b dmtc1 a1,\$f18
+[ 0-9a-f]+: 54b3 2c3b dmtc1 a1,\$f19
+[ 0-9a-f]+: 54b4 2c3b dmtc1 a1,\$f20
+[ 0-9a-f]+: 54b5 2c3b dmtc1 a1,\$f21
+[ 0-9a-f]+: 54b6 2c3b dmtc1 a1,\$f22
+[ 0-9a-f]+: 54b7 2c3b dmtc1 a1,\$f23
+[ 0-9a-f]+: 54b8 2c3b dmtc1 a1,\$f24
+[ 0-9a-f]+: 54b9 2c3b dmtc1 a1,\$f25
+[ 0-9a-f]+: 54ba 2c3b dmtc1 a1,\$f26
+[ 0-9a-f]+: 54bb 2c3b dmtc1 a1,\$f27
+[ 0-9a-f]+: 54bc 2c3b dmtc1 a1,\$f28
+[ 0-9a-f]+: 54bd 2c3b dmtc1 a1,\$f29
+[ 0-9a-f]+: 54be 2c3b dmtc1 a1,\$f30
+[ 0-9a-f]+: 54bf 2c3b dmtc1 a1,\$f31
+[ 0-9a-f]+: 54a0 2c3b dmtc1 a1,\$f0
+[ 0-9a-f]+: 54a1 2c3b dmtc1 a1,\$f1
+[ 0-9a-f]+: 54a2 2c3b dmtc1 a1,\$f2
+[ 0-9a-f]+: 54a3 2c3b dmtc1 a1,\$f3
+[ 0-9a-f]+: 54a4 2c3b dmtc1 a1,\$f4
+[ 0-9a-f]+: 54a5 2c3b dmtc1 a1,\$f5
+[ 0-9a-f]+: 54a6 2c3b dmtc1 a1,\$f6
+[ 0-9a-f]+: 54a7 2c3b dmtc1 a1,\$f7
+[ 0-9a-f]+: 54a8 2c3b dmtc1 a1,\$f8
+[ 0-9a-f]+: 54a9 2c3b dmtc1 a1,\$f9
+[ 0-9a-f]+: 54aa 2c3b dmtc1 a1,\$f10
+[ 0-9a-f]+: 54ab 2c3b dmtc1 a1,\$f11
+[ 0-9a-f]+: 54ac 2c3b dmtc1 a1,\$f12
+[ 0-9a-f]+: 54ad 2c3b dmtc1 a1,\$f13
+[ 0-9a-f]+: 54ae 2c3b dmtc1 a1,\$f14
+[ 0-9a-f]+: 54af 2c3b dmtc1 a1,\$f15
+[ 0-9a-f]+: 54b0 2c3b dmtc1 a1,\$f16
+[ 0-9a-f]+: 54b1 2c3b dmtc1 a1,\$f17
+[ 0-9a-f]+: 54b2 2c3b dmtc1 a1,\$f18
+[ 0-9a-f]+: 54b3 2c3b dmtc1 a1,\$f19
+[ 0-9a-f]+: 54b4 2c3b dmtc1 a1,\$f20
+[ 0-9a-f]+: 54b5 2c3b dmtc1 a1,\$f21
+[ 0-9a-f]+: 54b6 2c3b dmtc1 a1,\$f22
+[ 0-9a-f]+: 54b7 2c3b dmtc1 a1,\$f23
+[ 0-9a-f]+: 54b8 2c3b dmtc1 a1,\$f24
+[ 0-9a-f]+: 54b9 2c3b dmtc1 a1,\$f25
+[ 0-9a-f]+: 54ba 2c3b dmtc1 a1,\$f26
+[ 0-9a-f]+: 54bb 2c3b dmtc1 a1,\$f27
+[ 0-9a-f]+: 54bc 2c3b dmtc1 a1,\$f28
+[ 0-9a-f]+: 54bd 2c3b dmtc1 a1,\$f29
+[ 0-9a-f]+: 54be 2c3b dmtc1 a1,\$f30
+[ 0-9a-f]+: 54bf 2c3b dmtc1 a1,\$f31
[ 0-9a-f]+: 0040 6d3c dmfc2 v0,\$0
[ 0-9a-f]+: 0041 6d3c dmfc2 v0,\$1
[ 0-9a-f]+: 0042 6d3c dmfc2 v0,\$2
Index: binutils-gdb/gas/testsuite/gas/mips/micromips@isa-override-1.d
===================================================================
--- binutils-gdb.orig/gas/testsuite/gas/mips/micromips@isa-override-1.d
+++ binutils-gdb/gas/testsuite/gas/mips/micromips@isa-override-1.d
@@ -28,7 +28,7 @@
[0-9a-f]+ <[^>]*> 5821 8000 dsll at,at,0x10
[0-9a-f]+ <[^>]*> 5021 89ab ori at,at,0x89ab
[0-9a-f]+ <[^>]*> 5821 8000 dsll at,at,0x10
-[0-9a-f]+ <[^>]*> 5422 2c3b dmtc1 at,\$2
+[0-9a-f]+ <[^>]*> 5422 2c3b dmtc1 at,\$f2
[0-9a-f]+ <[^>]*> fc44 0000 lw v0,0\(a0\)
[0-9a-f]+ <[^>]*> fc64 0004 lw v1,4\(a0\)
[0-9a-f]+ <[^>]*> 41a1 89ab lui at,0x89ab
Index: binutils-gdb/opcodes/micromips-opc.c
===================================================================
--- binutils-gdb.orig/opcodes/micromips-opc.c
+++ binutils-gdb/opcodes/micromips-opc.c
@@ -633,8 +633,8 @@ const struct mips_opcode micromips_opcod
{"dmtgc0", "t,G,H", 0x580006fc, 0xfc00c7ff, RD_1|WR_C0|WR_CC, 0, 0, IVIRT64, 0 },
{"dmfc1", "t,S", 0x5400243b, 0xfc00ffff, WR_1|RD_2|FP_S|LC, 0, I3, 0, 0 },
{"dmfc1", "t,G", 0x5400243b, 0xfc00ffff, WR_1|RD_2|FP_S|LC, 0, I3, 0, 0 },
-{"dmtc1", "t,G", 0x54002c3b, 0xfc00ffff, RD_1|WR_2|FP_S|CM, 0, I3, 0, 0 },
{"dmtc1", "t,S", 0x54002c3b, 0xfc00ffff, RD_1|WR_2|FP_S|CM, 0, I3, 0, 0 },
+{"dmtc1", "t,G", 0x54002c3b, 0xfc00ffff, RD_1|WR_2|FP_S|CM, 0, I3, 0, 0 },
{"dmfc2", "t,G", 0x00006d3c, 0xfc00ffff, WR_1|RD_C2, 0, I3, 0, 0 },
/*{"dmfc2", "t,G,H", 0x58000283, 0xfc001fff, WR_1|RD_C2, 0, I3, 0, 0 },*/
{"dmtc2", "t,G", 0x00007d3c, 0xfc00ffff, RD_1|WR_C2|WR_CC, 0, I3, 0, 0 },
^ permalink raw reply [flat|nested] 19+ messages in thread
* [committed 03/18] MIPS/opcodes: Free up redundant `g' operand code
2021-05-29 1:36 [committed 00/18] MIPS coprocessor opcodes handling fixes Maciej W. Rozycki
2021-05-29 1:36 ` [committed 01/18] MIPS/GAS: Use FCSR rather than RA with CFC1/CTC1 Maciej W. Rozycki
2021-05-29 1:36 ` [committed 02/18] microMIPS/opcodes: Refer FPRs rather than FCRs with DMTC1 Maciej W. Rozycki
@ 2021-05-29 1:36 ` Maciej W. Rozycki
2021-05-29 1:37 ` [committed 04/18] MIPS/binutils/testsuite: Fix XPA and Virtualization ASE cases Maciej W. Rozycki
` (14 subsequent siblings)
17 siblings, 0 replies; 19+ messages in thread
From: Maciej W. Rozycki @ 2021-05-29 1:36 UTC (permalink / raw)
To: binutils
In the operand handling rewrite made for the MIPS disassembler with
commit ab90248154ba ("Add structures to describe MIPS operands"),
<https://sourceware.org/ml/binutils/2013-07/msg00135.html>, the `g'
operand code has become redundant for the regular MIPS instruction set
by duplicating the OP_REG_COPRO semantics of the `G' operand code.
Later commit 351cdf24d223 ("Implement O32 FPXX, FP64 and FP64A ABI
extensions") converted the CTTC1 instruction from the `g' to the `G'
operand code, but still left a few instructions behind.
Convert the three remaining instructions still using the `g' code then,
namely: CTTC2, MTTC2 and MTTHC2, and remove all traces of the operand
code, freeing it up for other use.
opcodes/
* mips-opc.c (mips_builtin_opcodes): Switch "cttc2", "mttc2",
and "mtthc2" to using the `G' rather than `g' operand code for
the coprocessor control register referred.
include/
* opcode/mips.h: Complement change made to opcodes and remove
references to the `g' regular MIPS ISA operand code.
---
include/opcode/mips.h | 3 +--
opcodes/mips-opc.c | 7 +++----
2 files changed, 4 insertions(+), 6 deletions(-)
binutils-mips-opcodes-xtc2-g.diff
Index: binutils-gdb/include/opcode/mips.h
===================================================================
--- binutils-gdb.orig/include/opcode/mips.h
+++ binutils-gdb/include/opcode/mips.h
@@ -899,7 +899,6 @@ mips_opcode_32bit_p (const struct mips_o
"$" 1 bit load high flag (OP_*_MT_H)
"*" 2 bit dsp/smartmips accumulator register (OP_*_MTACC_T)
"&" 2 bit dsp/smartmips accumulator register (OP_*_MTACC_D)
- "g" 5 bit coprocessor 1 and 2 destination register (OP_*_RD)
"+t" 5 bit coprocessor 0 destination register (OP_*_RT)
MCU ASE usage:
@@ -1001,7 +1000,7 @@ mips_opcode_32bit_p (const struct mips_o
"1234567890"
"%[]<>(),+-:'@!#$*&\~"
"ABCDEFGHIJKLMNOPQRSTUVWXYZ"
- "abcdefghijklopqrstuvwxz"
+ "abcdef hijkl opqrstuvwx z"
Extension character sequences used so far ("+" followed by the
following), for quick reference when adding more:
Index: binutils-gdb/opcodes/mips-opc.c
===================================================================
--- binutils-gdb.orig/opcodes/mips-opc.c
+++ binutils-gdb/opcodes/mips-opc.c
@@ -195,7 +195,6 @@ decode_mips_operand (const char *p)
case 'c': HINT (10, 16);
case 'd': REG (5, 11, GP);
case 'e': UINT (3, 22)
- case 'g': REG (5, 11, COPRO);
case 'h': HINT (5, 11);
case 'i': HINT (16, 0);
case 'j': SINT (16, 0);
@@ -997,7 +996,7 @@ const struct mips_opcode mips_builtin_op
/* ctc3 is at the bottom of the table. */
{"cttc1", "t,G", 0x41800023, 0xffe007ff, RD_1|WR_CC|TRAP|CM, 0, 0, MT32, 0 },
{"cttc1", "t,S", 0x41800023, 0xffe007ff, RD_1|WR_CC|TRAP|CM, 0, 0, MT32, 0 },
-{"cttc2", "t,g", 0x41800025, 0xffe007ff, RD_1|WR_CC|TRAP|CM, 0, 0, MT32, IOCT|IOCTP|IOCT2 },
+{"cttc2", "t,G", 0x41800025, 0xffe007ff, RD_1|WR_CC|TRAP|CM, 0, 0, MT32, IOCT|IOCTP|IOCT2 },
{"cvt.d.l", "D,S", 0x46a00021, 0xffff003f, WR_1|RD_2|FP_D, 0, I3_33, 0, 0 },
{"cvt.d.s", "D,S", 0x46000021, 0xffff003f, WR_1|RD_2|FP_S|FP_D, 0, I1, 0, SF },
{"cvt.d.w", "D,S", 0x46800021, 0xffff003f, WR_1|RD_2|FP_S|FP_D, 0, I1, 0, SF },
@@ -1556,14 +1555,14 @@ const struct mips_opcode mips_builtin_op
{"mttc0", "t,G,H", 0x41800000, 0xffe007f8, RD_1|WR_C0|WR_CC|TRAP|CM, 0, 0, MT32, 0 },
{"mttc1", "t,S", 0x41800022, 0xffe007ff, RD_1|WR_2|TRAP|CM|FP_S, 0, 0, MT32, 0 },
{"mttc1", "t,G", 0x41800022, 0xffe007ff, RD_1|WR_2|TRAP|CM|FP_S, 0, 0, MT32, 0 },
-{"mttc2", "t,g", 0x41800024, 0xffe007ff, RD_1|WR_C2|WR_CC|TRAP|CM, 0, 0, MT32, IOCT|IOCTP|IOCT2 },
+{"mttc2", "t,G", 0x41800024, 0xffe007ff, RD_1|WR_C2|WR_CC|TRAP|CM, 0, 0, MT32, IOCT|IOCTP|IOCT2 },
{"mttacx", "t", 0x41801021, 0xffe0ffff, RD_1|WR_a|TRAP, 0, 0, MT32, 0 },
{"mttacx", "t,&", 0x41801021, 0xffe09fff, RD_1|WR_a|TRAP, 0, 0, MT32, 0 },
{"mttdsp", "t", 0x41808021, 0xffe0ffff, RD_1|TRAP, 0, 0, MT32, 0 },
{"mttgpr", "t,d", 0x41800020, 0xffe007ff, RD_1|WR_2|TRAP, 0, 0, MT32, 0 },
{"mtthc1", "t,S", 0x41800032, 0xffe007ff, RD_1|WR_2|TRAP|CM|FP_D, 0, 0, MT32, 0 },
{"mtthc1", "t,G", 0x41800032, 0xffe007ff, RD_1|WR_2|TRAP|CM|FP_D, 0, 0, MT32, 0 },
-{"mtthc2", "t,g", 0x41800034, 0xffe007ff, RD_1|WR_C2|WR_CC|TRAP|CM, 0, 0, MT32, IOCT|IOCTP|IOCT2 },
+{"mtthc2", "t,G", 0x41800034, 0xffe007ff, RD_1|WR_C2|WR_CC|TRAP|CM, 0, 0, MT32, IOCT|IOCTP|IOCT2 },
{"mtthi", "t", 0x41800821, 0xffe0ffff, RD_1|WR_a|TRAP, 0, 0, MT32, 0 },
{"mtthi", "t,&", 0x41800821, 0xffe09fff, RD_1|WR_a|TRAP, 0, 0, MT32, 0 },
{"mttlo", "t", 0x41800021, 0xffe0ffff, RD_1|WR_a|TRAP, 0, 0, MT32, 0 },
^ permalink raw reply [flat|nested] 19+ messages in thread
* [committed 04/18] MIPS/binutils/testsuite: Fix XPA and Virtualization ASE cases
2021-05-29 1:36 [committed 00/18] MIPS coprocessor opcodes handling fixes Maciej W. Rozycki
` (2 preceding siblings ...)
2021-05-29 1:36 ` [committed 03/18] MIPS/opcodes: Free up redundant `g' operand code Maciej W. Rozycki
@ 2021-05-29 1:37 ` Maciej W. Rozycki
2021-05-29 1:37 ` [committed 05/18] MIPS/opcodes: Add TX39 CP0 register names Maciej W. Rozycki
` (13 subsequent siblings)
17 siblings, 0 replies; 19+ messages in thread
From: Maciej W. Rozycki @ 2021-05-29 1:37 UTC (permalink / raw)
To: binutils
Fix commit 9785fc2a4d22 ("MIPS: Fix XPA base and Virtualization ASE
instruction handling") and explicitly use the `mips:3000' machine for
disassembly across the XPA base and XPA Virtualization ASE test cases,
providing actual coverage for the `virt' and `xpa' disassembler options
and removing failures for targets that default to those ASEs enabled:
mipsisa32r2-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 1
mipsisa32r2-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 2
mipsisa32r2-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 3
mipsisa32r2-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 1
mipsisa32r2-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 2
mipsisa32r2-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 3
mipsisa32r2el-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 1
mipsisa32r2el-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 2
mipsisa32r2el-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 3
mipsisa32r2el-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 1
mipsisa32r2el-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 2
mipsisa32r2el-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 3
mipsisa32r3-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 1
mipsisa32r3-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 2
mipsisa32r3-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 3
mipsisa32r3-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 1
mipsisa32r3-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 2
mipsisa32r3-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 3
mipsisa32r3el-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 1
mipsisa32r3el-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 2
mipsisa32r3el-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 3
mipsisa32r3el-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 1
mipsisa32r3el-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 2
mipsisa32r3el-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 3
mipsisa32r5-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 1
mipsisa32r5-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 2
mipsisa32r5-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 3
mipsisa32r5-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 1
mipsisa32r5-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 2
mipsisa32r5-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 3
mipsisa32r5el-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 1
mipsisa32r5el-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 2
mipsisa32r5el-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 3
mipsisa32r5el-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 1
mipsisa32r5el-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 2
mipsisa32r5el-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 3
mipsisa32r6-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 1
mipsisa32r6-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 2
mipsisa32r6-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 3
mipsisa32r6-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 1
mipsisa32r6-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 2
mipsisa32r6-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 3
mipsisa32r6el-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 1
mipsisa32r6el-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 2
mipsisa32r6el-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 3
mipsisa32r6el-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 1
mipsisa32r6el-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 2
mipsisa32r6el-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 3
mipsisa64r2-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 1
mipsisa64r2-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 2
mipsisa64r2-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 3
mipsisa64r2-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 1
mipsisa64r2-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 2
mipsisa64r2-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 3
mipsisa64r2el-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 1
mipsisa64r2el-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 2
mipsisa64r2el-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 3
mipsisa64r2el-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 1
mipsisa64r2el-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 2
mipsisa64r2el-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 3
mipsisa64r3-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 1
mipsisa64r3-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 2
mipsisa64r3-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 3
mipsisa64r3-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 1
mipsisa64r3-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 2
mipsisa64r3-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 3
mipsisa64r3el-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 1
mipsisa64r3el-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 2
mipsisa64r3el-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 3
mipsisa64r3el-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 1
mipsisa64r3el-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 2
mipsisa64r3el-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 3
mipsisa64r5-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 1
mipsisa64r5-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 2
mipsisa64r5-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 3
mipsisa64r5-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 1
mipsisa64r5-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 2
mipsisa64r5-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 3
mipsisa64r5el-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 1
mipsisa64r5el-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 2
mipsisa64r5el-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 3
mipsisa64r5el-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 1
mipsisa64r5el-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 2
mipsisa64r5el-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 3
mipsisa64r6-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 1
mipsisa64r6-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 2
mipsisa64r6-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 3
mipsisa64r6-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 1
mipsisa64r6-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 2
mipsisa64r6-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 3
mipsisa64r6el-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 1
mipsisa64r6el-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 2
mipsisa64r6el-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 3
mipsisa64r6el-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 1
mipsisa64r6el-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 2
mipsisa64r6el-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 3
This is because the test cases rely on these ASEs being disabled for
disassembly by default and expect instructions belonging to these ASEs
not to be shown unless explicitly enabled. The `mips-xpa-virt-4' test
case passes regardless, but we want it to verify the explicit options do
work, so use the `mips:3000' machine to set the defaults there as well.
binutils/
* testsuite/binutils-all/mips/mips-xpa-virt-1.d: Use `mips:3000'
machine for disassembly.
* testsuite/binutils-all/mips/mips-xpa-virt-2.d: Likewise.
* testsuite/binutils-all/mips/mips-xpa-virt-3.d: Likewise.
* testsuite/binutils-all/mips/mips-xpa-virt-4.d: Likewise.
---
binutils/testsuite/binutils-all/mips/mips-xpa-virt-1.d | 2 +-
binutils/testsuite/binutils-all/mips/mips-xpa-virt-2.d | 2 +-
binutils/testsuite/binutils-all/mips/mips-xpa-virt-3.d | 2 +-
binutils/testsuite/binutils-all/mips/mips-xpa-virt-4.d | 2 +-
4 files changed, 4 insertions(+), 4 deletions(-)
binutils-mips-test-xpa-virt.diff
Index: binutils-gdb/binutils/testsuite/binutils-all/mips/mips-xpa-virt-1.d
===================================================================
--- binutils-gdb.orig/binutils/testsuite/binutils-all/mips/mips-xpa-virt-1.d
+++ binutils-gdb/binutils/testsuite/binutils-all/mips/mips-xpa-virt-1.d
@@ -1,5 +1,5 @@
#PROG: objcopy
-#objdump: -d --prefix-addresses --show-raw-insn -M cp0-names=mips32
+#objdump: -d --prefix-addresses --show-raw-insn -m mips:3000 -M cp0-names=mips32
#name: MIPS XPA and Virtualization ASE instruction disassembly 1
#source: mips-xpa-virt.s
Index: binutils-gdb/binutils/testsuite/binutils-all/mips/mips-xpa-virt-2.d
===================================================================
--- binutils-gdb.orig/binutils/testsuite/binutils-all/mips/mips-xpa-virt-2.d
+++ binutils-gdb/binutils/testsuite/binutils-all/mips/mips-xpa-virt-2.d
@@ -1,5 +1,5 @@
#PROG: objcopy
-#objdump: -d --prefix-addresses --show-raw-insn -M xpa,cp0-names=mips32
+#objdump: -d --prefix-addresses --show-raw-insn -m mips:3000 -M xpa,cp0-names=mips32
#name: MIPS XPA and Virtualization ASE instruction disassembly 2
#source: mips-xpa-virt.s
Index: binutils-gdb/binutils/testsuite/binutils-all/mips/mips-xpa-virt-3.d
===================================================================
--- binutils-gdb.orig/binutils/testsuite/binutils-all/mips/mips-xpa-virt-3.d
+++ binutils-gdb/binutils/testsuite/binutils-all/mips/mips-xpa-virt-3.d
@@ -1,5 +1,5 @@
#PROG: objcopy
-#objdump: -d --prefix-addresses --show-raw-insn -M virt,cp0-names=mips32
+#objdump: -d --prefix-addresses --show-raw-insn -m mips:3000 -M virt,cp0-names=mips32
#name: MIPS XPA and Virtualization ASE instruction disassembly 3
#source: mips-xpa-virt.s
Index: binutils-gdb/binutils/testsuite/binutils-all/mips/mips-xpa-virt-4.d
===================================================================
--- binutils-gdb.orig/binutils/testsuite/binutils-all/mips/mips-xpa-virt-4.d
+++ binutils-gdb/binutils/testsuite/binutils-all/mips/mips-xpa-virt-4.d
@@ -1,5 +1,5 @@
#PROG: objcopy
-#objdump: -d --prefix-addresses --show-raw-insn -M xpa,virt,cp0-names=mips32
+#objdump: -d --prefix-addresses --show-raw-insn -m mips:3000 -M xpa,virt,cp0-names=mips32
#name: MIPS XPA and Virtualization ASE instruction disassembly 4
#source: mips-xpa-virt.s
^ permalink raw reply [flat|nested] 19+ messages in thread
* [committed 05/18] MIPS/opcodes: Add TX39 CP0 register names
2021-05-29 1:36 [committed 00/18] MIPS coprocessor opcodes handling fixes Maciej W. Rozycki
` (3 preceding siblings ...)
2021-05-29 1:37 ` [committed 04/18] MIPS/binutils/testsuite: Fix XPA and Virtualization ASE cases Maciej W. Rozycki
@ 2021-05-29 1:37 ` Maciej W. Rozycki
2021-05-29 1:37 ` [committed 06/18] MIPS/opcodes: Do not use CP0 register names for control registers Maciej W. Rozycki
` (12 subsequent siblings)
17 siblings, 0 replies; 19+ messages in thread
From: Maciej W. Rozycki @ 2021-05-29 1:37 UTC (permalink / raw)
To: binutils
The TX39 core has its distinct set of CP0 registers[1], so it needs a
separate table to hold their names. Add a test case accordingly.
References:
[1] "32-Bit RISC Microprocessor TX39 Family Core Architecture User's
Manual", Toshiba, Jul. 27, 1995, Section 2.2.2 "System control
coprocessor (CP0) registers", pp. 9-10
opcodes/
* mips-dis.c (mips_cp0_names_r3900): New variable.
(mips_arch_choices): Use it rather than `mips_cp0_names_numeric'
for "r3900".
gas/
* testsuite/gas/mips/cp0-names-r3900.d: New test.
* testsuite/gas/mips/mips.exp: Run it.
---
gas/testsuite/gas/mips/cp0-names-r3900.d | 43 +++++++++++++++++++++++++++++++
gas/testsuite/gas/mips/mips.exp | 1
opcodes/mips-dis.c | 14 +++++++++-
3 files changed, 57 insertions(+), 1 deletion(-)
binutils-mips-opcodes-cp0-names-r3900.diff
Index: binutils-gdb/gas/testsuite/gas/mips/cp0-names-r3900.d
===================================================================
--- /dev/null
+++ binutils-gdb/gas/testsuite/gas/mips/cp0-names-r3900.d
@@ -0,0 +1,43 @@
+#objdump: -dr --prefix-addresses --show-raw-insn -M gpr-names=numeric,cp0-names=r3900
+#name: MIPS CP0 register disassembly (r3900)
+#as: -32 -march=r3900
+#source: cp0-names.s
+
+# Check objdump's handling of -M cp0-names=foo options.
+
+.*: +file format .*mips.*
+
+Disassembly of section \.text:
+[0-9a-f]+ <[^>]*> 40800000 mtc0 \$0,\$0
+[0-9a-f]+ <[^>]*> 40800800 mtc0 \$0,\$1
+[0-9a-f]+ <[^>]*> 40801000 mtc0 \$0,\$2
+[0-9a-f]+ <[^>]*> 40801800 mtc0 \$0,c0_config
+[0-9a-f]+ <[^>]*> 40802000 mtc0 \$0,\$4
+[0-9a-f]+ <[^>]*> 40802800 mtc0 \$0,\$5
+[0-9a-f]+ <[^>]*> 40803000 mtc0 \$0,\$6
+[0-9a-f]+ <[^>]*> 40803800 mtc0 \$0,c0_cache
+[0-9a-f]+ <[^>]*> 40804000 mtc0 \$0,c0_badvaddr
+[0-9a-f]+ <[^>]*> 40804800 mtc0 \$0,\$9
+[0-9a-f]+ <[^>]*> 40805000 mtc0 \$0,\$10
+[0-9a-f]+ <[^>]*> 40805800 mtc0 \$0,\$11
+[0-9a-f]+ <[^>]*> 40806000 mtc0 \$0,c0_sr
+[0-9a-f]+ <[^>]*> 40806800 mtc0 \$0,c0_cause
+[0-9a-f]+ <[^>]*> 40807000 mtc0 \$0,c0_epc
+[0-9a-f]+ <[^>]*> 40807800 mtc0 \$0,c0_prid
+[0-9a-f]+ <[^>]*> 40808000 mtc0 \$0,c0_debug
+[0-9a-f]+ <[^>]*> 40808800 mtc0 \$0,c0_depc
+[0-9a-f]+ <[^>]*> 40809000 mtc0 \$0,\$18
+[0-9a-f]+ <[^>]*> 40809800 mtc0 \$0,\$19
+[0-9a-f]+ <[^>]*> 4080a000 mtc0 \$0,\$20
+[0-9a-f]+ <[^>]*> 4080a800 mtc0 \$0,\$21
+[0-9a-f]+ <[^>]*> 4080b000 mtc0 \$0,\$22
+[0-9a-f]+ <[^>]*> 4080b800 mtc0 \$0,\$23
+[0-9a-f]+ <[^>]*> 4080c000 mtc0 \$0,\$24
+[0-9a-f]+ <[^>]*> 4080c800 mtc0 \$0,\$25
+[0-9a-f]+ <[^>]*> 4080d000 mtc0 \$0,\$26
+[0-9a-f]+ <[^>]*> 4080d800 mtc0 \$0,\$27
+[0-9a-f]+ <[^>]*> 4080e000 mtc0 \$0,\$28
+[0-9a-f]+ <[^>]*> 4080e800 mtc0 \$0,\$29
+[0-9a-f]+ <[^>]*> 4080f000 mtc0 \$0,\$30
+[0-9a-f]+ <[^>]*> 4080f800 mtc0 \$0,\$31
+ \.\.\.
Index: binutils-gdb/gas/testsuite/gas/mips/mips.exp
===================================================================
--- binutils-gdb.orig/gas/testsuite/gas/mips/mips.exp
+++ binutils-gdb/gas/testsuite/gas/mips/mips.exp
@@ -1315,6 +1315,7 @@ if { [istarget mips*-*-vxworks*] } {
run_dump_test "cp0-names-numeric"
run_dump_test "cp0-names-r3000"
+ run_dump_test "cp0-names-r3900"
run_dump_test "cp0-names-r4000" \
{ { {name} {(r4000)} } { {objdump} {-M cp0-names=r4000} } }
run_dump_test "cp0-names-r4000" \
Index: binutils-gdb/opcodes/mips-dis.c
===================================================================
--- binutils-gdb.orig/opcodes/mips-dis.c
+++ binutils-gdb/opcodes/mips-dis.c
@@ -122,6 +122,18 @@ static const char * const mips_cp1_names
"$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31"
};
+static const char * const mips_cp0_names_r3900[32] =
+{
+ "$0", "$1", "$2", "c0_config",
+ "$4", "$5", "$6", "c0_cache",
+ "c0_badvaddr", "$9", "$10", "$11",
+ "c0_sr", "c0_cause", "c0_epc", "c0_prid",
+ "c0_debug", "c0_depc", "$18", "$19",
+ "$20", "$21", "$22", "$23",
+ "$24", "$25", "$26", "$27",
+ "$28", "$29", "$30", "$31",
+};
+
static const char * const mips_cp0_names_r3000[32] =
{
"c0_index", "c0_random", "c0_entrylo", "$3",
@@ -457,7 +469,7 @@ const struct mips_arch_choice mips_arch_
mips_cp0_names_r3000, NULL, 0, mips_cp1_names_numeric,
mips_hwr_names_numeric },
{ "r3900", 1, bfd_mach_mips3900, CPU_R3900, ISA_MIPS1, 0,
- mips_cp0_names_numeric, NULL, 0, mips_cp1_names_numeric,
+ mips_cp0_names_r3900, NULL, 0, mips_cp1_names_numeric,
mips_hwr_names_numeric },
{ "r4000", 1, bfd_mach_mips4000, CPU_R4000, ISA_MIPS3, 0,
mips_cp0_names_r4000, NULL, 0, mips_cp1_names_numeric,
^ permalink raw reply [flat|nested] 19+ messages in thread
* [committed 06/18] MIPS/opcodes: Do not use CP0 register names for control registers
2021-05-29 1:36 [committed 00/18] MIPS coprocessor opcodes handling fixes Maciej W. Rozycki
` (4 preceding siblings ...)
2021-05-29 1:37 ` [committed 05/18] MIPS/opcodes: Add TX39 CP0 register names Maciej W. Rozycki
@ 2021-05-29 1:37 ` Maciej W. Rozycki
2021-05-29 1:37 ` [committed 07/18] MIPS/GAS/testsuite: Add tests for coprocessor access instructions Maciej W. Rozycki
` (11 subsequent siblings)
17 siblings, 0 replies; 19+ messages in thread
From: Maciej W. Rozycki @ 2021-05-29 1:37 UTC (permalink / raw)
To: binutils
The CP0 control register set has never been defined, however encodings
for the CFC0 and CTC0 instructions remained available for implementers
up until the MIPS32 ISA declared them invalid and causing the Reserved
Instruction exception[1]. Therefore we handle them for both assembly
and disassembly, however in the latter case the names of CP0 registers
from the regular set are incorrectly printed if named registers are
requested. This is because we do not define separate operand classes
for coprocessor regular and control registers respectively, which means
the disassembler has no way to tell the two cases apart. Consequently
nonsensical disassembly is produced like:
cfc0 v0,c0_random
Later the MIPSr5 ISA reused the encodings for XPA ASE MFHC0 and MTHC0
instructions[2] although it failed to document them in the relevant
opcode table until MIPSr6 only.
Correct the issue then by defining a new register class, OP_REG_CONTROL,
and corresponding operand codes, `g' and `y' for the two positions in
the machine instruction a control register operand can take. Adjust the
test cases affected accordingly.
While at it swap the regular MIPS opcode table "cfc0" and "ctc0" entries
with each other so that they come in the alphabetical order.
References:
[1] "MIPS32 Architecture For Programmers, Volume II: The MIPS32
Instruction Set", MIPS Technologies, Inc., Document Number: MD00086,
Revision 1.00, August 29, 2002, Table A-9 "MIPS32 COP0 Encoding of
rs Field", p. 242
[2] "MIPS Architecture For Programmers, Volume II-A: The MIPS32
Instruction Set", MIPS Technologies, Inc., Document Number: MD00086,
Revision 5.04, December 11, 2013, Section 3.2 "Alphabetical List of
Instructions", pp. 195, 216
include/
* opcode/mips.h: Document `g' and `y' operand codes.
(mips_reg_operand_type): Add OP_REG_CONTROL enumeration
constant.
gas/
* tc-mips.c (convert_reg_type) <OP_REG_CONTROL>: New case.
(macro) <M_TRUNCWS, M_TRUNCWD>: Use the `g' rather than `G'
operand code.
opcodes/
* mips-dis.c (print_reg) <OP_REG_COPRO>: Move control register
handling code over to...
<OP_REG_CONTROL>: ... this new case.
* mips-opc.c (decode_mips_operand) <'g', 'y'>: New cases.
(mips_builtin_opcodes): Update "cfc1", "ctc1", "cttc1", "cttc2",
"cfc0", "ctc0", "cfc2", "ctc2", "cfc3", and "ctc3" entries
replacing the `G' operand code with `g'. Update "cftc1" and
"cftc2" entries replacing the `E' operand code with `y'.
* micromips-opc.c (decode_micromips_operand) <'g'>: New case.
(micromips_opcodes): Update "cfc1", "cfc2", "ctc1", and "ctc2"
entries replacing the `G' operand code with `g'.
binutils/
* testsuite/binutils-all/mips/mips-xpa-virt-1.d: Correct CFC0
operand disassembly.
* testsuite/binutils-all/mips/mips-xpa-virt-3.d: Likewise.
---
binutils/testsuite/binutils-all/mips/mips-xpa-virt-1.d | 2 -
binutils/testsuite/binutils-all/mips/mips-xpa-virt-3.d | 2 -
gas/config/tc-mips.c | 9 +++--
include/opcode/mips.h | 11 +++++--
opcodes/micromips-opc.c | 9 +++--
opcodes/mips-dis.c | 7 +++-
opcodes/mips-opc.c | 26 +++++++++--------
7 files changed, 41 insertions(+), 25 deletions(-)
binutils-mips-opcodes-control.diff
Index: binutils-gdb/binutils/testsuite/binutils-all/mips/mips-xpa-virt-1.d
===================================================================
--- binutils-gdb.orig/binutils/testsuite/binutils-all/mips/mips-xpa-virt-1.d
+++ binutils-gdb/binutils/testsuite/binutils-all/mips/mips-xpa-virt-1.d
@@ -7,7 +7,7 @@
Disassembly of section \.text:
[0-9a-f]+ <[^>]*> 40020800 mfc0 v0,c0_random
-[0-9a-f]+ <[^>]*> 40420800 cfc0 v0,c0_random
+[0-9a-f]+ <[^>]*> 40420800 cfc0 v0,\$1
[0-9a-f]+ <[^>]*> 40620800 0x40620800
[0-9a-f]+ <[^>]*> 40620c00 0x40620c00
\.\.\.
Index: binutils-gdb/binutils/testsuite/binutils-all/mips/mips-xpa-virt-3.d
===================================================================
--- binutils-gdb.orig/binutils/testsuite/binutils-all/mips/mips-xpa-virt-3.d
+++ binutils-gdb/binutils/testsuite/binutils-all/mips/mips-xpa-virt-3.d
@@ -7,7 +7,7 @@
Disassembly of section \.text:
[0-9a-f]+ <[^>]*> 40020800 mfc0 v0,c0_random
-[0-9a-f]+ <[^>]*> 40420800 cfc0 v0,c0_random
+[0-9a-f]+ <[^>]*> 40420800 cfc0 v0,\$1
[0-9a-f]+ <[^>]*> 40620800 mfgc0 v0,c0_random
[0-9a-f]+ <[^>]*> 40620c00 0x40620c00
\.\.\.
Index: binutils-gdb/gas/config/tc-mips.c
===================================================================
--- binutils-gdb.orig/gas/config/tc-mips.c
+++ binutils-gdb/gas/config/tc-mips.c
@@ -5050,6 +5050,7 @@ convert_reg_type (const struct mips_opco
return RTYPE_ACC;
case OP_REG_COPRO:
+ case OP_REG_CONTROL:
if (opcode->name[strlen (opcode->name) - 1] == '0')
return RTYPE_NUM | RTYPE_CP0;
return RTYPE_NUM;
@@ -13837,18 +13838,18 @@ macro (struct mips_cl_insn *ip, char *st
* or is there a reason for it?
*/
start_noreorder ();
- macro_build (NULL, "cfc1", "t,G", op[2], FCSR);
- macro_build (NULL, "cfc1", "t,G", op[2], FCSR);
+ macro_build (NULL, "cfc1", "t,g", op[2], FCSR);
+ macro_build (NULL, "cfc1", "t,g", op[2], FCSR);
macro_build (NULL, "nop", "");
expr1.X_add_number = 3;
macro_build (&expr1, "ori", "t,r,i", AT, op[2], BFD_RELOC_LO16);
expr1.X_add_number = 2;
macro_build (&expr1, "xori", "t,r,i", AT, AT, BFD_RELOC_LO16);
- macro_build (NULL, "ctc1", "t,G", AT, FCSR);
+ macro_build (NULL, "ctc1", "t,g", AT, FCSR);
macro_build (NULL, "nop", "");
macro_build (NULL, mask == M_TRUNCWD ? "cvt.w.d" : "cvt.w.s", "D,S",
op[0], op[1]);
- macro_build (NULL, "ctc1", "t,G", op[2], FCSR);
+ macro_build (NULL, "ctc1", "t,g", op[2], FCSR);
macro_build (NULL, "nop", "");
end_noreorder ();
break;
Index: binutils-gdb/include/opcode/mips.h
===================================================================
--- binutils-gdb.orig/include/opcode/mips.h
+++ binutils-gdb/include/opcode/mips.h
@@ -461,6 +461,10 @@ enum mips_reg_operand_type {
also be used in some contexts. */
OP_REG_COPRO,
+ /* Coprocessor control registers $0-$31. Mnemonic names like c1_fcsr can
+ also be used in some contexts. */
+ OP_REG_CONTROL,
+
/* Hardware registers $0-$31. Mnemonic names like hwr_cpunum can
also be used in some contexts. */
OP_REG_HW,
@@ -841,6 +845,7 @@ mips_opcode_32bit_p (const struct mips_o
"H" 3 bit sel field for (d)mtc* and (d)mfc* (OP_*_SEL)
"P" 5 bit performance-monitor register (OP_*_PERFREG)
"e" 5 bit vector register byte specifier (OP_*_VECBYTE)
+ "g" 5 bit control destination register (OP_*_RD)
"%" 3 bit immediate vr5400 vector alignment operand (OP_*_VECALIGN)
Macro instructions:
@@ -899,6 +904,7 @@ mips_opcode_32bit_p (const struct mips_o
"$" 1 bit load high flag (OP_*_MT_H)
"*" 2 bit dsp/smartmips accumulator register (OP_*_MTACC_T)
"&" 2 bit dsp/smartmips accumulator register (OP_*_MTACC_D)
+ "y" 5 bit control target register (OP_*_RT)
"+t" 5 bit coprocessor 0 destination register (OP_*_RT)
MCU ASE usage:
@@ -1000,7 +1006,7 @@ mips_opcode_32bit_p (const struct mips_o
"1234567890"
"%[]<>(),+-:'@!#$*&\~"
"ABCDEFGHIJKLMNOPQRSTUVWXYZ"
- "abcdef hijkl opqrstuvwx z"
+ "abcdef hijkl opqrstuvwxyz"
Extension character sequences used so far ("+" followed by the
following), for quick reference when adding more:
@@ -2277,6 +2283,7 @@ extern const int bfd_mips16_num_opcodes;
"E" 5-bit target register (MICROMIPSOP_*_RT)
"G" 5-bit source register (MICROMIPSOP_*_RS)
"H" 3-bit sel field for (D)MTC* and (D)MFC* (MICROMIPSOP_*_SEL)
+ "g" 5-bit control source register (MICROMIPSOP_*_RS)
Macro instructions:
"A" general 32 bit expression
@@ -2338,7 +2345,7 @@ extern const int bfd_mips16_num_opcodes;
"12345678 0"
"<>(),+-.@\^|~"
"ABCDEFGHI KLMN RST V "
- "abcd f hijklmnopqrstuvw yz"
+ "abcd fghijklmnopqrstuvw yz"
Extension character sequences used so far ("+" followed by the
following), for quick reference when adding more:
Index: binutils-gdb/opcodes/micromips-opc.c
===================================================================
--- binutils-gdb.orig/opcodes/micromips-opc.c
+++ binutils-gdb/opcodes/micromips-opc.c
@@ -176,6 +176,7 @@ decode_micromips_operand (const char *p)
case 'b': REG (5, 16, GP);
case 'c': HINT (10, 16);
case 'd': REG (5, 11, GP);
+ case 'g': REG (5, 16, CONTROL);
case 'h': HINT (5, 11);
case 'i': HINT (16, 0);
case 'j': SINT (16, 0);
@@ -548,15 +549,15 @@ const struct mips_opcode micromips_opcod
{"ceil.l.s", "T,S", 0x5400133b, 0xfc00ffff, WR_1|RD_2|FP_S|FP_D, 0, I1, 0, 0 },
{"ceil.w.d", "T,S", 0x54005b3b, 0xfc00ffff, WR_1|RD_2|FP_S|FP_D, 0, I1, 0, 0 },
{"ceil.w.s", "T,S", 0x54001b3b, 0xfc00ffff, WR_1|RD_2|FP_S, 0, I1, 0, 0 },
-{"cfc1", "t,G", 0x5400103b, 0xfc00ffff, WR_1|RD_C1, 0, I1, 0, 0 },
+{"cfc1", "t,g", 0x5400103b, 0xfc00ffff, WR_1|RD_C1, 0, I1, 0, 0 },
{"cfc1", "t,S", 0x5400103b, 0xfc00ffff, WR_1|RD_C1, 0, I1, 0, 0 },
-{"cfc2", "t,G", 0x0000cd3c, 0xfc00ffff, WR_1|RD_C2, 0, I1, 0, 0 },
+{"cfc2", "t,g", 0x0000cd3c, 0xfc00ffff, WR_1|RD_C2, 0, I1, 0, 0 },
{"clo", "t,s", 0x00004b3c, 0xfc00ffff, WR_1|RD_2, 0, I1, 0, 0 },
{"clz", "t,s", 0x00005b3c, 0xfc00ffff, WR_1|RD_2, 0, I1, 0, 0 },
{"cop2", "C", 0x00000002, 0xfc000007, CP, 0, I1, 0, 0 },
-{"ctc1", "t,G", 0x5400183b, 0xfc00ffff, RD_1|WR_CC, 0, I1, 0, 0 },
+{"ctc1", "t,g", 0x5400183b, 0xfc00ffff, RD_1|WR_CC, 0, I1, 0, 0 },
{"ctc1", "t,S", 0x5400183b, 0xfc00ffff, RD_1|WR_CC, 0, I1, 0, 0 },
-{"ctc2", "t,G", 0x0000dd3c, 0xfc00ffff, RD_1|WR_C2|WR_CC, 0, I1, 0, 0 },
+{"ctc2", "t,g", 0x0000dd3c, 0xfc00ffff, RD_1|WR_C2|WR_CC, 0, I1, 0, 0 },
{"cvt.d.l", "T,S", 0x5400537b, 0xfc00ffff, WR_1|RD_2|FP_D, 0, I1, 0, 0 },
{"cvt.d.s", "T,S", 0x5400137b, 0xfc00ffff, WR_1|RD_2|FP_S|FP_D, 0, I1, 0, 0 },
{"cvt.d.w", "T,S", 0x5400337b, 0xfc00ffff, WR_1|RD_2|FP_S|FP_D, 0, I1, 0, 0 },
Index: binutils-gdb/opcodes/mips-dis.c
===================================================================
--- binutils-gdb.orig/opcodes/mips-dis.c
+++ binutils-gdb/opcodes/mips-dis.c
@@ -1192,7 +1192,12 @@ print_reg (struct disassemble_info *info
case OP_REG_COPRO:
if (opcode->name[strlen (opcode->name) - 1] == '0')
info->fprintf_func (info->stream, "%s", mips_cp0_names[regno]);
- else if (opcode->name[strlen (opcode->name) - 1] == '1')
+ else
+ info->fprintf_func (info->stream, "$%d", regno);
+ break;
+
+ case OP_REG_CONTROL:
+ if (opcode->name[strlen (opcode->name) - 1] == '1')
info->fprintf_func (info->stream, "%s", mips_cp1_names[regno]);
else
info->fprintf_func (info->stream, "$%d", regno);
Index: binutils-gdb/opcodes/mips-opc.c
===================================================================
--- binutils-gdb.orig/opcodes/mips-opc.c
+++ binutils-gdb/opcodes/mips-opc.c
@@ -195,6 +195,7 @@ decode_mips_operand (const char *p)
case 'c': HINT (10, 16);
case 'd': REG (5, 11, GP);
case 'e': UINT (3, 22)
+ case 'g': REG (5, 11, CONTROL);
case 'h': HINT (5, 11);
case 'i': HINT (16, 0);
case 'j': SINT (16, 0);
@@ -209,6 +210,7 @@ decode_mips_operand (const char *p)
case 'v': OPTIONAL_REG (5, 21, GP);
case 'w': OPTIONAL_REG (5, 16, GP);
case 'x': REG (0, 0, GP);
+ case 'y': REG (5, 16, CONTROL);
case 'z': MAPPED_REG (0, 0, GP, reg_0_map);
}
return 0;
@@ -975,13 +977,13 @@ const struct mips_opcode mips_builtin_op
{"ceil.w.d", "D,S", 0x4620000e, 0xffff003f, WR_1|RD_2|FP_S|FP_D, 0, I2, 0, SF },
{"ceil.w.s", "D,S", 0x4600000e, 0xffff003f, WR_1|RD_2|FP_S, 0, I2, 0, EE },
/* cfc0 is at the bottom of the table. */
-{"cfc1", "t,G", 0x44400000, 0xffe007ff, WR_1|RD_C1|LC, 0, I1, 0, 0 },
+{"cfc1", "t,g", 0x44400000, 0xffe007ff, WR_1|RD_C1|LC, 0, I1, 0, 0 },
{"cfc1", "t,S", 0x44400000, 0xffe007ff, WR_1|RD_C1|LC, 0, I1, 0, 0 },
/* cfc2 is at the bottom of the table. */
/* cfc3 is at the bottom of the table. */
-{"cftc1", "d,E", 0x41000023, 0xffe007ff, WR_1|RD_C1|TRAP|LC, 0, 0, MT32, 0 },
+{"cftc1", "d,y", 0x41000023, 0xffe007ff, WR_1|RD_C1|TRAP|LC, 0, 0, MT32, 0 },
{"cftc1", "d,T", 0x41000023, 0xffe007ff, WR_1|RD_C1|TRAP|LC, 0, 0, MT32, 0 },
-{"cftc2", "d,E", 0x41000025, 0xffe007ff, WR_1|RD_C2|TRAP|LC, 0, 0, MT32, IOCT|IOCTP|IOCT2 },
+{"cftc2", "d,y", 0x41000025, 0xffe007ff, WR_1|RD_C2|TRAP|LC, 0, 0, MT32, IOCT|IOCTP|IOCT2 },
{"cins32", "t,r,+p,+s", 0x70000033, 0xfc00003f, WR_1|RD_2, 0, IOCT, 0, 0 },
{"cins", "t,r,+P,+S", 0x70000033, 0xfc00003f, WR_1|RD_2, 0, IOCT, 0, 0 }, /* cins32 */
{"cins", "t,r,+p,+S", 0x70000032, 0xfc00003f, WR_1|RD_2, 0, IOCT, 0, 0 },
@@ -990,13 +992,13 @@ const struct mips_opcode mips_builtin_op
{"clz", "d,s", 0x00000050, 0xfc1f07ff, WR_1|RD_2, 0, I37, 0, 0 },
{"clz", "U,s", 0x70000020, 0xfc0007ff, WR_1|RD_2, 0, I32|N55, 0, I37 },
/* ctc0 is at the bottom of the table. */
-{"ctc1", "t,G", 0x44c00000, 0xffe007ff, RD_1|WR_CC|CM, 0, I1, 0, 0 },
+{"ctc1", "t,g", 0x44c00000, 0xffe007ff, RD_1|WR_CC|CM, 0, I1, 0, 0 },
{"ctc1", "t,S", 0x44c00000, 0xffe007ff, RD_1|WR_CC|CM, 0, I1, 0, 0 },
/* ctc2 is at the bottom of the table. */
/* ctc3 is at the bottom of the table. */
-{"cttc1", "t,G", 0x41800023, 0xffe007ff, RD_1|WR_CC|TRAP|CM, 0, 0, MT32, 0 },
+{"cttc1", "t,g", 0x41800023, 0xffe007ff, RD_1|WR_CC|TRAP|CM, 0, 0, MT32, 0 },
{"cttc1", "t,S", 0x41800023, 0xffe007ff, RD_1|WR_CC|TRAP|CM, 0, 0, MT32, 0 },
-{"cttc2", "t,G", 0x41800025, 0xffe007ff, RD_1|WR_CC|TRAP|CM, 0, 0, MT32, IOCT|IOCTP|IOCT2 },
+{"cttc2", "t,g", 0x41800025, 0xffe007ff, RD_1|WR_CC|TRAP|CM, 0, 0, MT32, IOCT|IOCTP|IOCT2 },
{"cvt.d.l", "D,S", 0x46a00021, 0xffff003f, WR_1|RD_2|FP_D, 0, I3_33, 0, 0 },
{"cvt.d.s", "D,S", 0x46000021, 0xffff003f, WR_1|RD_2|FP_S|FP_D, 0, I1, 0, SF },
{"cvt.d.w", "D,S", 0x46800021, 0xffff003f, WR_1|RD_2|FP_S|FP_D, 0, I1, 0, SF },
@@ -2106,8 +2108,8 @@ const struct mips_opcode mips_builtin_op
/* Coprocessor 0 move instructions cfc0 and ctc0 conflict with the
mfhc0 and mthc0 XPA instructions, so they have been placed here
to allow the XPA instructions to take precedence. */
-{"ctc0", "t,G", 0x40c00000, 0xffe007ff, RD_1|WR_CC|CM, 0, I1, 0, IOCT|IOCTP|IOCT2 },
-{"cfc0", "t,G", 0x40400000, 0xffe007ff, WR_1|RD_C0|LC, 0, I1, 0, IOCT|IOCTP|IOCT2 },
+{"cfc0", "t,g", 0x40400000, 0xffe007ff, WR_1|RD_C0|LC, 0, I1, 0, IOCT|IOCTP|IOCT2 },
+{"ctc0", "t,g", 0x40c00000, 0xffe007ff, RD_1|WR_CC|CM, 0, I1, 0, IOCT|IOCTP|IOCT2 },
/* Coprocessor 2 move/branch operations overlap with VR5400 .ob format
instructions so they are here for the latters to take precedence. */
@@ -2121,11 +2123,11 @@ const struct mips_opcode mips_builtin_op
{"bc2t", "N,p", 0x49010000, 0xffe30000, RD_CC|CBD, 0, I32, 0, IOCT|IOCTP|IOCT2|I37 },
{"bc2tl", "p", 0x49030000, 0xffff0000, RD_CC|CBL, 0, I2|T3, 0, IOCT|IOCTP|IOCT2|I37 },
{"bc2tl", "N,p", 0x49030000, 0xffe30000, RD_CC|CBL, 0, I32, 0, IOCT|IOCTP|IOCT2|I37 },
-{"cfc2", "t,G", 0x48400000, 0xffe007ff, WR_1|RD_C2|LC, 0, I1, 0, IOCT|IOCTP|IOCT2|EE },
+{"cfc2", "t,g", 0x48400000, 0xffe007ff, WR_1|RD_C2|LC, 0, I1, 0, IOCT|IOCTP|IOCT2|EE },
{"cfc2", "t,+9", 0x48400000, 0xffe007ff, WR_1|RD_C2|LC, 0, EE, 0, 0 },
{"cfc2.i", "t,+9", 0x48400001, 0xffe007ff, WR_1|RD_C2|LC, 0, EE, 0, 0 },
{"cfc2.ni", "t,+9", 0x48400000, 0xffe007ff, WR_1|RD_C2|LC, 0, EE, 0, 0 },
-{"ctc2", "t,G", 0x48c00000, 0xffe007ff, RD_1|WR_CC|CM, 0, I1, 0, IOCT|IOCTP|IOCT2|EE },
+{"ctc2", "t,g", 0x48c00000, 0xffe007ff, RD_1|WR_CC|CM, 0, I1, 0, IOCT|IOCTP|IOCT2|EE },
{"ctc2", "t,+9", 0x48c00000, 0xffe007ff, RD_1|WR_CC|CM, 0, EE, 0, 0 },
{"ctc2.i", "t,+9", 0x48c00001, 0xffe007ff, RD_1|WR_CC|CM, 0, EE, 0, 0 },
{"ctc2.ni", "t,+9", 0x48c00000, 0xffe007ff, RD_1|WR_CC|CM, 0, EE, 0, 0 },
@@ -2157,8 +2159,8 @@ const struct mips_opcode mips_builtin_op
{"bc3fl", "p", 0x4d020000, 0xffff0000, RD_CC|CBL, 0, I2|T3, 0, IOCT|IOCTP|IOCT2|EE|I37 },
{"bc3t", "p", 0x4d010000, 0xffff0000, RD_CC|CBD, 0, I1, 0, IOCT|IOCTP|IOCT2|EE|I37 },
{"bc3tl", "p", 0x4d030000, 0xffff0000, RD_CC|CBL, 0, I2|T3, 0, IOCT|IOCTP|IOCT2|EE|I37 },
-{"cfc3", "t,G", 0x4c400000, 0xffe007ff, WR_1|RD_C3|LC, 0, I1, 0, IOCT|IOCTP|IOCT2|EE|I37 },
-{"ctc3", "t,G", 0x4cc00000, 0xffe007ff, RD_1|WR_CC|CM, 0, I1, 0, IOCT|IOCTP|IOCT2|EE|I37 },
+{"cfc3", "t,g", 0x4c400000, 0xffe007ff, WR_1|RD_C3|LC, 0, I1, 0, IOCT|IOCTP|IOCT2|EE|I37 },
+{"ctc3", "t,g", 0x4cc00000, 0xffe007ff, RD_1|WR_CC|CM, 0, I1, 0, IOCT|IOCTP|IOCT2|EE|I37 },
{"dmfc3", "t,G", 0x4c200000, 0xffe007ff, WR_1|RD_C3|LC, 0, I3, 0, IOCT|IOCTP|IOCT2|EE|I37 },
{"dmtc3", "t,G", 0x4ca00000, 0xffe007ff, RD_1|WR_C3|WR_CC|CM, 0, I3, 0, IOCT|IOCTP|IOCT2|EE|I37 },
{"mfc3", "t,G", 0x4c000000, 0xffe007ff, WR_1|RD_C3|LC, 0, I1, 0, IOCT|IOCTP|IOCT2|EE|I37 },
^ permalink raw reply [flat|nested] 19+ messages in thread
* [committed 07/18] MIPS/GAS/testsuite: Add tests for coprocessor access instructions
2021-05-29 1:36 [committed 00/18] MIPS coprocessor opcodes handling fixes Maciej W. Rozycki
` (5 preceding siblings ...)
2021-05-29 1:37 ` [committed 06/18] MIPS/opcodes: Do not use CP0 register names for control registers Maciej W. Rozycki
@ 2021-05-29 1:37 ` Maciej W. Rozycki
2021-05-29 1:37 ` [committed 08/18] MIPS/opcodes: Add legacy CP1 control register names Maciej W. Rozycki
` (10 subsequent siblings)
17 siblings, 0 replies; 19+ messages in thread
From: Maciej W. Rozycki @ 2021-05-29 1:37 UTC (permalink / raw)
To: binutils
Cover basic CP0, CP2, CP3 move, load and store instructions across the
relevant ISA levels. Omit CP0 move and CP1 instructions as they are
covered elsewhere.
gas/
* testsuite/gas/mips/cp0c.d: New test.
* testsuite/gas/mips/cp0m.d: New test.
* testsuite/gas/mips/r3900@cp0m.d: New test.
* testsuite/gas/mips/cp2.d: New test.
* testsuite/gas/mips/micromips@cp2.d: New test.
* testsuite/gas/mips/cp2m.d: New test.
* testsuite/gas/mips/mipsr6@cp2m.d: New test.
* testsuite/gas/mips/micromips@cp2m.d: New test.
* testsuite/gas/mips/cp2d.d: New test.
* testsuite/gas/mips/mipsr6@cp2d.d: New test.
* testsuite/gas/mips/micromips@cp2d.d: New test.
* testsuite/gas/mips/cp2-64.d: New test.
* testsuite/gas/mips/micromips@cp2-64.d: New test.
* testsuite/gas/mips/cp3.d: New test.
* testsuite/gas/mips/cp3m.d: New test.
* testsuite/gas/mips/cp3d.d: New test.
* testsuite/gas/mips/cp0c.s: New test source.
* testsuite/gas/mips/cp0m.s: New test source.
* testsuite/gas/mips/cp2.s: New test source.
* testsuite/gas/mips/cp2m.s: New test source.
* testsuite/gas/mips/cp2d.s: New test source.
* testsuite/gas/mips/cp2-64.s: New test source.
* testsuite/gas/mips/cp3.s: New test source.
* testsuite/gas/mips/cp3m.s: New test source.
* testsuite/gas/mips/cp3d.s: New test source.
* testsuite/gas/mips/mips.exp: Run the new tests.
---
gas/testsuite/gas/mips/cp0c.d | 72 +++++++++++++++
gas/testsuite/gas/mips/cp0c.s | 72 +++++++++++++++
gas/testsuite/gas/mips/cp0m.d | 72 +++++++++++++++
gas/testsuite/gas/mips/cp0m.s | 72 +++++++++++++++
gas/testsuite/gas/mips/cp2-64.d | 72 +++++++++++++++
gas/testsuite/gas/mips/cp2-64.s | 72 +++++++++++++++
gas/testsuite/gas/mips/cp2.d | 136 +++++++++++++++++++++++++++++
gas/testsuite/gas/mips/cp2.s | 138 ++++++++++++++++++++++++++++++
gas/testsuite/gas/mips/cp2d.d | 72 +++++++++++++++
gas/testsuite/gas/mips/cp2d.s | 71 +++++++++++++++
gas/testsuite/gas/mips/cp2m.d | 72 +++++++++++++++
gas/testsuite/gas/mips/cp2m.s | 72 +++++++++++++++
gas/testsuite/gas/mips/cp3.d | 136 +++++++++++++++++++++++++++++
gas/testsuite/gas/mips/cp3.s | 138 ++++++++++++++++++++++++++++++
gas/testsuite/gas/mips/cp3d.d | 72 +++++++++++++++
gas/testsuite/gas/mips/cp3d.s | 72 +++++++++++++++
gas/testsuite/gas/mips/cp3m.d | 72 +++++++++++++++
gas/testsuite/gas/mips/cp3m.s | 72 +++++++++++++++
gas/testsuite/gas/mips/micromips@cp2-64.d | 73 +++++++++++++++
gas/testsuite/gas/mips/micromips@cp2.d | 137 +++++++++++++++++++++++++++++
gas/testsuite/gas/mips/micromips@cp2d.d | 73 +++++++++++++++
gas/testsuite/gas/mips/micromips@cp2m.d | 73 +++++++++++++++
gas/testsuite/gas/mips/mips.exp | 21 ++++
gas/testsuite/gas/mips/mipsr6@cp2d.d | 73 +++++++++++++++
gas/testsuite/gas/mips/mipsr6@cp2m.d | 73 +++++++++++++++
gas/testsuite/gas/mips/r3900@cp0m.d | 73 +++++++++++++++
26 files changed, 2151 insertions(+)
binutils-mips-opcodes-copx-test.diff
Index: binutils-gdb/gas/testsuite/gas/mips/cp0c.d
===================================================================
--- /dev/null
+++ binutils-gdb/gas/testsuite/gas/mips/cp0c.d
@@ -0,0 +1,72 @@
+#objdump: -d --prefix-addresses --show-raw-insn
+#name: MIPS CP0 control register move instructions
+#as: -32
+
+.*: +file format .*mips.*
+
+Disassembly of section \.text:
+[0-9a-f]+ <[^>]*> 40c00000 ctc0 zero,\$0
+[0-9a-f]+ <[^>]*> 40c00800 ctc0 zero,\$1
+[0-9a-f]+ <[^>]*> 40c01000 ctc0 zero,\$2
+[0-9a-f]+ <[^>]*> 40c01800 ctc0 zero,\$3
+[0-9a-f]+ <[^>]*> 40c02000 ctc0 zero,\$4
+[0-9a-f]+ <[^>]*> 40c02800 ctc0 zero,\$5
+[0-9a-f]+ <[^>]*> 40c03000 ctc0 zero,\$6
+[0-9a-f]+ <[^>]*> 40c03800 ctc0 zero,\$7
+[0-9a-f]+ <[^>]*> 40c04000 ctc0 zero,\$8
+[0-9a-f]+ <[^>]*> 40c04800 ctc0 zero,\$9
+[0-9a-f]+ <[^>]*> 40c05000 ctc0 zero,\$10
+[0-9a-f]+ <[^>]*> 40c05800 ctc0 zero,\$11
+[0-9a-f]+ <[^>]*> 40c06000 ctc0 zero,\$12
+[0-9a-f]+ <[^>]*> 40c06800 ctc0 zero,\$13
+[0-9a-f]+ <[^>]*> 40c07000 ctc0 zero,\$14
+[0-9a-f]+ <[^>]*> 40c07800 ctc0 zero,\$15
+[0-9a-f]+ <[^>]*> 40c08000 ctc0 zero,\$16
+[0-9a-f]+ <[^>]*> 40c08800 ctc0 zero,\$17
+[0-9a-f]+ <[^>]*> 40c09000 ctc0 zero,\$18
+[0-9a-f]+ <[^>]*> 40c09800 ctc0 zero,\$19
+[0-9a-f]+ <[^>]*> 40c0a000 ctc0 zero,\$20
+[0-9a-f]+ <[^>]*> 40c0a800 ctc0 zero,\$21
+[0-9a-f]+ <[^>]*> 40c0b000 ctc0 zero,\$22
+[0-9a-f]+ <[^>]*> 40c0b800 ctc0 zero,\$23
+[0-9a-f]+ <[^>]*> 40c0c000 ctc0 zero,\$24
+[0-9a-f]+ <[^>]*> 40c0c800 ctc0 zero,\$25
+[0-9a-f]+ <[^>]*> 40c0d000 ctc0 zero,\$26
+[0-9a-f]+ <[^>]*> 40c0d800 ctc0 zero,\$27
+[0-9a-f]+ <[^>]*> 40c0e000 ctc0 zero,\$28
+[0-9a-f]+ <[^>]*> 40c0e800 ctc0 zero,\$29
+[0-9a-f]+ <[^>]*> 40c0f000 ctc0 zero,\$30
+[0-9a-f]+ <[^>]*> 40c0f800 ctc0 zero,\$31
+[0-9a-f]+ <[^>]*> 40400000 cfc0 zero,\$0
+[0-9a-f]+ <[^>]*> 40400800 cfc0 zero,\$1
+[0-9a-f]+ <[^>]*> 40401000 cfc0 zero,\$2
+[0-9a-f]+ <[^>]*> 40401800 cfc0 zero,\$3
+[0-9a-f]+ <[^>]*> 40402000 cfc0 zero,\$4
+[0-9a-f]+ <[^>]*> 40402800 cfc0 zero,\$5
+[0-9a-f]+ <[^>]*> 40403000 cfc0 zero,\$6
+[0-9a-f]+ <[^>]*> 40403800 cfc0 zero,\$7
+[0-9a-f]+ <[^>]*> 40404000 cfc0 zero,\$8
+[0-9a-f]+ <[^>]*> 40404800 cfc0 zero,\$9
+[0-9a-f]+ <[^>]*> 40405000 cfc0 zero,\$10
+[0-9a-f]+ <[^>]*> 40405800 cfc0 zero,\$11
+[0-9a-f]+ <[^>]*> 40406000 cfc0 zero,\$12
+[0-9a-f]+ <[^>]*> 40406800 cfc0 zero,\$13
+[0-9a-f]+ <[^>]*> 40407000 cfc0 zero,\$14
+[0-9a-f]+ <[^>]*> 40407800 cfc0 zero,\$15
+[0-9a-f]+ <[^>]*> 40408000 cfc0 zero,\$16
+[0-9a-f]+ <[^>]*> 40408800 cfc0 zero,\$17
+[0-9a-f]+ <[^>]*> 40409000 cfc0 zero,\$18
+[0-9a-f]+ <[^>]*> 40409800 cfc0 zero,\$19
+[0-9a-f]+ <[^>]*> 4040a000 cfc0 zero,\$20
+[0-9a-f]+ <[^>]*> 4040a800 cfc0 zero,\$21
+[0-9a-f]+ <[^>]*> 4040b000 cfc0 zero,\$22
+[0-9a-f]+ <[^>]*> 4040b800 cfc0 zero,\$23
+[0-9a-f]+ <[^>]*> 4040c000 cfc0 zero,\$24
+[0-9a-f]+ <[^>]*> 4040c800 cfc0 zero,\$25
+[0-9a-f]+ <[^>]*> 4040d000 cfc0 zero,\$26
+[0-9a-f]+ <[^>]*> 4040d800 cfc0 zero,\$27
+[0-9a-f]+ <[^>]*> 4040e000 cfc0 zero,\$28
+[0-9a-f]+ <[^>]*> 4040e800 cfc0 zero,\$29
+[0-9a-f]+ <[^>]*> 4040f000 cfc0 zero,\$30
+[0-9a-f]+ <[^>]*> 4040f800 cfc0 zero,\$31
+ \.\.\.
Index: binutils-gdb/gas/testsuite/gas/mips/cp0c.s
===================================================================
--- /dev/null
+++ binutils-gdb/gas/testsuite/gas/mips/cp0c.s
@@ -0,0 +1,72 @@
+ .text
+ .set noreorder
+foo:
+ ctc0 $0, $0
+ ctc0 $0, $1
+ ctc0 $0, $2
+ ctc0 $0, $3
+ ctc0 $0, $4
+ ctc0 $0, $5
+ ctc0 $0, $6
+ ctc0 $0, $7
+ ctc0 $0, $8
+ ctc0 $0, $9
+ ctc0 $0, $10
+ ctc0 $0, $11
+ ctc0 $0, $12
+ ctc0 $0, $13
+ ctc0 $0, $14
+ ctc0 $0, $15
+ ctc0 $0, $16
+ ctc0 $0, $17
+ ctc0 $0, $18
+ ctc0 $0, $19
+ ctc0 $0, $20
+ ctc0 $0, $21
+ ctc0 $0, $22
+ ctc0 $0, $23
+ ctc0 $0, $24
+ ctc0 $0, $25
+ ctc0 $0, $26
+ ctc0 $0, $27
+ ctc0 $0, $28
+ ctc0 $0, $29
+ ctc0 $0, $30
+ ctc0 $0, $31
+
+ cfc0 $0, $0
+ cfc0 $0, $1
+ cfc0 $0, $2
+ cfc0 $0, $3
+ cfc0 $0, $4
+ cfc0 $0, $5
+ cfc0 $0, $6
+ cfc0 $0, $7
+ cfc0 $0, $8
+ cfc0 $0, $9
+ cfc0 $0, $10
+ cfc0 $0, $11
+ cfc0 $0, $12
+ cfc0 $0, $13
+ cfc0 $0, $14
+ cfc0 $0, $15
+ cfc0 $0, $16
+ cfc0 $0, $17
+ cfc0 $0, $18
+ cfc0 $0, $19
+ cfc0 $0, $20
+ cfc0 $0, $21
+ cfc0 $0, $22
+ cfc0 $0, $23
+ cfc0 $0, $24
+ cfc0 $0, $25
+ cfc0 $0, $26
+ cfc0 $0, $27
+ cfc0 $0, $28
+ cfc0 $0, $29
+ cfc0 $0, $30
+ cfc0 $0, $31
+
+# Force some (non-delay-slot) zero bytes, to make 'objdump' print ...
+ .align 4, 0
+ .space 16
Index: binutils-gdb/gas/testsuite/gas/mips/cp0m.d
===================================================================
--- /dev/null
+++ binutils-gdb/gas/testsuite/gas/mips/cp0m.d
@@ -0,0 +1,72 @@
+#objdump: -d --prefix-addresses --show-raw-insn
+#name: MIPS CP0 memory access instructions
+#as: -32
+
+.*: +file format .*mips.*
+
+Disassembly of section \.text:
+[0-9a-f]+ <[^>]*> c0000000 lwc0 c0_index,0\(zero\)
+[0-9a-f]+ <[^>]*> c0010000 lwc0 c0_random,0\(zero\)
+[0-9a-f]+ <[^>]*> c0020000 lwc0 c0_entrylo,0\(zero\)
+[0-9a-f]+ <[^>]*> c0030000 lwc0 \$3,0\(zero\)
+[0-9a-f]+ <[^>]*> c0040000 lwc0 c0_context,0\(zero\)
+[0-9a-f]+ <[^>]*> c0050000 lwc0 \$5,0\(zero\)
+[0-9a-f]+ <[^>]*> c0060000 lwc0 \$6,0\(zero\)
+[0-9a-f]+ <[^>]*> c0070000 lwc0 \$7,0\(zero\)
+[0-9a-f]+ <[^>]*> c0080000 lwc0 c0_badvaddr,0\(zero\)
+[0-9a-f]+ <[^>]*> c0090000 lwc0 \$9,0\(zero\)
+[0-9a-f]+ <[^>]*> c00a0000 lwc0 c0_entryhi,0\(zero\)
+[0-9a-f]+ <[^>]*> c00b0000 lwc0 \$11,0\(zero\)
+[0-9a-f]+ <[^>]*> c00c0000 lwc0 c0_sr,0\(zero\)
+[0-9a-f]+ <[^>]*> c00d0000 lwc0 c0_cause,0\(zero\)
+[0-9a-f]+ <[^>]*> c00e0000 lwc0 c0_epc,0\(zero\)
+[0-9a-f]+ <[^>]*> c00f0000 lwc0 c0_prid,0\(zero\)
+[0-9a-f]+ <[^>]*> c0100000 lwc0 \$16,0\(zero\)
+[0-9a-f]+ <[^>]*> c0110000 lwc0 \$17,0\(zero\)
+[0-9a-f]+ <[^>]*> c0120000 lwc0 \$18,0\(zero\)
+[0-9a-f]+ <[^>]*> c0130000 lwc0 \$19,0\(zero\)
+[0-9a-f]+ <[^>]*> c0140000 lwc0 \$20,0\(zero\)
+[0-9a-f]+ <[^>]*> c0150000 lwc0 \$21,0\(zero\)
+[0-9a-f]+ <[^>]*> c0160000 lwc0 \$22,0\(zero\)
+[0-9a-f]+ <[^>]*> c0170000 lwc0 \$23,0\(zero\)
+[0-9a-f]+ <[^>]*> c0180000 lwc0 \$24,0\(zero\)
+[0-9a-f]+ <[^>]*> c0190000 lwc0 \$25,0\(zero\)
+[0-9a-f]+ <[^>]*> c01a0000 lwc0 \$26,0\(zero\)
+[0-9a-f]+ <[^>]*> c01b0000 lwc0 \$27,0\(zero\)
+[0-9a-f]+ <[^>]*> c01c0000 lwc0 \$28,0\(zero\)
+[0-9a-f]+ <[^>]*> c01d0000 lwc0 \$29,0\(zero\)
+[0-9a-f]+ <[^>]*> c01e0000 lwc0 \$30,0\(zero\)
+[0-9a-f]+ <[^>]*> c01f0000 lwc0 \$31,0\(zero\)
+[0-9a-f]+ <[^>]*> e0000000 swc0 c0_index,0\(zero\)
+[0-9a-f]+ <[^>]*> e0010000 swc0 c0_random,0\(zero\)
+[0-9a-f]+ <[^>]*> e0020000 swc0 c0_entrylo,0\(zero\)
+[0-9a-f]+ <[^>]*> e0030000 swc0 \$3,0\(zero\)
+[0-9a-f]+ <[^>]*> e0040000 swc0 c0_context,0\(zero\)
+[0-9a-f]+ <[^>]*> e0050000 swc0 \$5,0\(zero\)
+[0-9a-f]+ <[^>]*> e0060000 swc0 \$6,0\(zero\)
+[0-9a-f]+ <[^>]*> e0070000 swc0 \$7,0\(zero\)
+[0-9a-f]+ <[^>]*> e0080000 swc0 c0_badvaddr,0\(zero\)
+[0-9a-f]+ <[^>]*> e0090000 swc0 \$9,0\(zero\)
+[0-9a-f]+ <[^>]*> e00a0000 swc0 c0_entryhi,0\(zero\)
+[0-9a-f]+ <[^>]*> e00b0000 swc0 \$11,0\(zero\)
+[0-9a-f]+ <[^>]*> e00c0000 swc0 c0_sr,0\(zero\)
+[0-9a-f]+ <[^>]*> e00d0000 swc0 c0_cause,0\(zero\)
+[0-9a-f]+ <[^>]*> e00e0000 swc0 c0_epc,0\(zero\)
+[0-9a-f]+ <[^>]*> e00f0000 swc0 c0_prid,0\(zero\)
+[0-9a-f]+ <[^>]*> e0100000 swc0 \$16,0\(zero\)
+[0-9a-f]+ <[^>]*> e0110000 swc0 \$17,0\(zero\)
+[0-9a-f]+ <[^>]*> e0120000 swc0 \$18,0\(zero\)
+[0-9a-f]+ <[^>]*> e0130000 swc0 \$19,0\(zero\)
+[0-9a-f]+ <[^>]*> e0140000 swc0 \$20,0\(zero\)
+[0-9a-f]+ <[^>]*> e0150000 swc0 \$21,0\(zero\)
+[0-9a-f]+ <[^>]*> e0160000 swc0 \$22,0\(zero\)
+[0-9a-f]+ <[^>]*> e0170000 swc0 \$23,0\(zero\)
+[0-9a-f]+ <[^>]*> e0180000 swc0 \$24,0\(zero\)
+[0-9a-f]+ <[^>]*> e0190000 swc0 \$25,0\(zero\)
+[0-9a-f]+ <[^>]*> e01a0000 swc0 \$26,0\(zero\)
+[0-9a-f]+ <[^>]*> e01b0000 swc0 \$27,0\(zero\)
+[0-9a-f]+ <[^>]*> e01c0000 swc0 \$28,0\(zero\)
+[0-9a-f]+ <[^>]*> e01d0000 swc0 \$29,0\(zero\)
+[0-9a-f]+ <[^>]*> e01e0000 swc0 \$30,0\(zero\)
+[0-9a-f]+ <[^>]*> e01f0000 swc0 \$31,0\(zero\)
+ \.\.\.
Index: binutils-gdb/gas/testsuite/gas/mips/cp0m.s
===================================================================
--- /dev/null
+++ binutils-gdb/gas/testsuite/gas/mips/cp0m.s
@@ -0,0 +1,72 @@
+ .text
+ .set noreorder
+foo:
+ lwc0 $0, 0($0)
+ lwc0 $1, 0($0)
+ lwc0 $2, 0($0)
+ lwc0 $3, 0($0)
+ lwc0 $4, 0($0)
+ lwc0 $5, 0($0)
+ lwc0 $6, 0($0)
+ lwc0 $7, 0($0)
+ lwc0 $8, 0($0)
+ lwc0 $9, 0($0)
+ lwc0 $10, 0($0)
+ lwc0 $11, 0($0)
+ lwc0 $12, 0($0)
+ lwc0 $13, 0($0)
+ lwc0 $14, 0($0)
+ lwc0 $15, 0($0)
+ lwc0 $16, 0($0)
+ lwc0 $17, 0($0)
+ lwc0 $18, 0($0)
+ lwc0 $19, 0($0)
+ lwc0 $20, 0($0)
+ lwc0 $21, 0($0)
+ lwc0 $22, 0($0)
+ lwc0 $23, 0($0)
+ lwc0 $24, 0($0)
+ lwc0 $25, 0($0)
+ lwc0 $26, 0($0)
+ lwc0 $27, 0($0)
+ lwc0 $28, 0($0)
+ lwc0 $29, 0($0)
+ lwc0 $30, 0($0)
+ lwc0 $31, 0($0)
+
+ swc0 $0, 0($0)
+ swc0 $1, 0($0)
+ swc0 $2, 0($0)
+ swc0 $3, 0($0)
+ swc0 $4, 0($0)
+ swc0 $5, 0($0)
+ swc0 $6, 0($0)
+ swc0 $7, 0($0)
+ swc0 $8, 0($0)
+ swc0 $9, 0($0)
+ swc0 $10, 0($0)
+ swc0 $11, 0($0)
+ swc0 $12, 0($0)
+ swc0 $13, 0($0)
+ swc0 $14, 0($0)
+ swc0 $15, 0($0)
+ swc0 $16, 0($0)
+ swc0 $17, 0($0)
+ swc0 $18, 0($0)
+ swc0 $19, 0($0)
+ swc0 $20, 0($0)
+ swc0 $21, 0($0)
+ swc0 $22, 0($0)
+ swc0 $23, 0($0)
+ swc0 $24, 0($0)
+ swc0 $25, 0($0)
+ swc0 $26, 0($0)
+ swc0 $27, 0($0)
+ swc0 $28, 0($0)
+ swc0 $29, 0($0)
+ swc0 $30, 0($0)
+ swc0 $31, 0($0)
+
+# Force some (non-delay-slot) zero bytes, to make 'objdump' print ...
+ .align 4, 0
+ .space 16
Index: binutils-gdb/gas/testsuite/gas/mips/cp2-64.d
===================================================================
--- /dev/null
+++ binutils-gdb/gas/testsuite/gas/mips/cp2-64.d
@@ -0,0 +1,72 @@
+#objdump: -d --prefix-addresses --show-raw-insn
+#name: MIPS CP2 64-bit move instructions
+#as: -32
+
+.*: +file format .*mips.*
+
+Disassembly of section \.text:
+[0-9a-f]+ <[^>]*> 48a00000 dmtc2 zero,\$0
+[0-9a-f]+ <[^>]*> 48a00800 dmtc2 zero,\$1
+[0-9a-f]+ <[^>]*> 48a01000 dmtc2 zero,\$2
+[0-9a-f]+ <[^>]*> 48a01800 dmtc2 zero,\$3
+[0-9a-f]+ <[^>]*> 48a02000 dmtc2 zero,\$4
+[0-9a-f]+ <[^>]*> 48a02800 dmtc2 zero,\$5
+[0-9a-f]+ <[^>]*> 48a03000 dmtc2 zero,\$6
+[0-9a-f]+ <[^>]*> 48a03800 dmtc2 zero,\$7
+[0-9a-f]+ <[^>]*> 48a04000 dmtc2 zero,\$8
+[0-9a-f]+ <[^>]*> 48a04800 dmtc2 zero,\$9
+[0-9a-f]+ <[^>]*> 48a05000 dmtc2 zero,\$10
+[0-9a-f]+ <[^>]*> 48a05800 dmtc2 zero,\$11
+[0-9a-f]+ <[^>]*> 48a06000 dmtc2 zero,\$12
+[0-9a-f]+ <[^>]*> 48a06800 dmtc2 zero,\$13
+[0-9a-f]+ <[^>]*> 48a07000 dmtc2 zero,\$14
+[0-9a-f]+ <[^>]*> 48a07800 dmtc2 zero,\$15
+[0-9a-f]+ <[^>]*> 48a08000 dmtc2 zero,\$16
+[0-9a-f]+ <[^>]*> 48a08800 dmtc2 zero,\$17
+[0-9a-f]+ <[^>]*> 48a09000 dmtc2 zero,\$18
+[0-9a-f]+ <[^>]*> 48a09800 dmtc2 zero,\$19
+[0-9a-f]+ <[^>]*> 48a0a000 dmtc2 zero,\$20
+[0-9a-f]+ <[^>]*> 48a0a800 dmtc2 zero,\$21
+[0-9a-f]+ <[^>]*> 48a0b000 dmtc2 zero,\$22
+[0-9a-f]+ <[^>]*> 48a0b800 dmtc2 zero,\$23
+[0-9a-f]+ <[^>]*> 48a0c000 dmtc2 zero,\$24
+[0-9a-f]+ <[^>]*> 48a0c800 dmtc2 zero,\$25
+[0-9a-f]+ <[^>]*> 48a0d000 dmtc2 zero,\$26
+[0-9a-f]+ <[^>]*> 48a0d800 dmtc2 zero,\$27
+[0-9a-f]+ <[^>]*> 48a0e000 dmtc2 zero,\$28
+[0-9a-f]+ <[^>]*> 48a0e800 dmtc2 zero,\$29
+[0-9a-f]+ <[^>]*> 48a0f000 dmtc2 zero,\$30
+[0-9a-f]+ <[^>]*> 48a0f800 dmtc2 zero,\$31
+[0-9a-f]+ <[^>]*> 48200000 dmfc2 zero,\$0
+[0-9a-f]+ <[^>]*> 48200800 dmfc2 zero,\$1
+[0-9a-f]+ <[^>]*> 48201000 dmfc2 zero,\$2
+[0-9a-f]+ <[^>]*> 48201800 dmfc2 zero,\$3
+[0-9a-f]+ <[^>]*> 48202000 dmfc2 zero,\$4
+[0-9a-f]+ <[^>]*> 48202800 dmfc2 zero,\$5
+[0-9a-f]+ <[^>]*> 48203000 dmfc2 zero,\$6
+[0-9a-f]+ <[^>]*> 48203800 dmfc2 zero,\$7
+[0-9a-f]+ <[^>]*> 48204000 dmfc2 zero,\$8
+[0-9a-f]+ <[^>]*> 48204800 dmfc2 zero,\$9
+[0-9a-f]+ <[^>]*> 48205000 dmfc2 zero,\$10
+[0-9a-f]+ <[^>]*> 48205800 dmfc2 zero,\$11
+[0-9a-f]+ <[^>]*> 48206000 dmfc2 zero,\$12
+[0-9a-f]+ <[^>]*> 48206800 dmfc2 zero,\$13
+[0-9a-f]+ <[^>]*> 48207000 dmfc2 zero,\$14
+[0-9a-f]+ <[^>]*> 48207800 dmfc2 zero,\$15
+[0-9a-f]+ <[^>]*> 48208000 dmfc2 zero,\$16
+[0-9a-f]+ <[^>]*> 48208800 dmfc2 zero,\$17
+[0-9a-f]+ <[^>]*> 48209000 dmfc2 zero,\$18
+[0-9a-f]+ <[^>]*> 48209800 dmfc2 zero,\$19
+[0-9a-f]+ <[^>]*> 4820a000 dmfc2 zero,\$20
+[0-9a-f]+ <[^>]*> 4820a800 dmfc2 zero,\$21
+[0-9a-f]+ <[^>]*> 4820b000 dmfc2 zero,\$22
+[0-9a-f]+ <[^>]*> 4820b800 dmfc2 zero,\$23
+[0-9a-f]+ <[^>]*> 4820c000 dmfc2 zero,\$24
+[0-9a-f]+ <[^>]*> 4820c800 dmfc2 zero,\$25
+[0-9a-f]+ <[^>]*> 4820d000 dmfc2 zero,\$26
+[0-9a-f]+ <[^>]*> 4820d800 dmfc2 zero,\$27
+[0-9a-f]+ <[^>]*> 4820e000 dmfc2 zero,\$28
+[0-9a-f]+ <[^>]*> 4820e800 dmfc2 zero,\$29
+[0-9a-f]+ <[^>]*> 4820f000 dmfc2 zero,\$30
+[0-9a-f]+ <[^>]*> 4820f800 dmfc2 zero,\$31
+ \.\.\.
Index: binutils-gdb/gas/testsuite/gas/mips/cp2-64.s
===================================================================
--- /dev/null
+++ binutils-gdb/gas/testsuite/gas/mips/cp2-64.s
@@ -0,0 +1,72 @@
+ .text
+ .set noreorder
+foo:
+ dmtc2 $0, $0
+ dmtc2 $0, $1
+ dmtc2 $0, $2
+ dmtc2 $0, $3
+ dmtc2 $0, $4
+ dmtc2 $0, $5
+ dmtc2 $0, $6
+ dmtc2 $0, $7
+ dmtc2 $0, $8
+ dmtc2 $0, $9
+ dmtc2 $0, $10
+ dmtc2 $0, $11
+ dmtc2 $0, $12
+ dmtc2 $0, $13
+ dmtc2 $0, $14
+ dmtc2 $0, $15
+ dmtc2 $0, $16
+ dmtc2 $0, $17
+ dmtc2 $0, $18
+ dmtc2 $0, $19
+ dmtc2 $0, $20
+ dmtc2 $0, $21
+ dmtc2 $0, $22
+ dmtc2 $0, $23
+ dmtc2 $0, $24
+ dmtc2 $0, $25
+ dmtc2 $0, $26
+ dmtc2 $0, $27
+ dmtc2 $0, $28
+ dmtc2 $0, $29
+ dmtc2 $0, $30
+ dmtc2 $0, $31
+
+ dmfc2 $0, $0
+ dmfc2 $0, $1
+ dmfc2 $0, $2
+ dmfc2 $0, $3
+ dmfc2 $0, $4
+ dmfc2 $0, $5
+ dmfc2 $0, $6
+ dmfc2 $0, $7
+ dmfc2 $0, $8
+ dmfc2 $0, $9
+ dmfc2 $0, $10
+ dmfc2 $0, $11
+ dmfc2 $0, $12
+ dmfc2 $0, $13
+ dmfc2 $0, $14
+ dmfc2 $0, $15
+ dmfc2 $0, $16
+ dmfc2 $0, $17
+ dmfc2 $0, $18
+ dmfc2 $0, $19
+ dmfc2 $0, $20
+ dmfc2 $0, $21
+ dmfc2 $0, $22
+ dmfc2 $0, $23
+ dmfc2 $0, $24
+ dmfc2 $0, $25
+ dmfc2 $0, $26
+ dmfc2 $0, $27
+ dmfc2 $0, $28
+ dmfc2 $0, $29
+ dmfc2 $0, $30
+ dmfc2 $0, $31
+
+# Force some (non-delay-slot) zero bytes, to make 'objdump' print ...
+ .align 4, 0
+ .space 16
Index: binutils-gdb/gas/testsuite/gas/mips/cp2.d
===================================================================
--- /dev/null
+++ binutils-gdb/gas/testsuite/gas/mips/cp2.d
@@ -0,0 +1,136 @@
+#objdump: -d --prefix-addresses --show-raw-insn
+#name: MIPS CP2 register move instructions
+#as: -32
+
+.*: +file format .*mips.*
+
+Disassembly of section \.text:
+[0-9a-f]+ <[^>]*> 48800000 mtc2 zero,\$0
+[0-9a-f]+ <[^>]*> 48800800 mtc2 zero,\$1
+[0-9a-f]+ <[^>]*> 48801000 mtc2 zero,\$2
+[0-9a-f]+ <[^>]*> 48801800 mtc2 zero,\$3
+[0-9a-f]+ <[^>]*> 48802000 mtc2 zero,\$4
+[0-9a-f]+ <[^>]*> 48802800 mtc2 zero,\$5
+[0-9a-f]+ <[^>]*> 48803000 mtc2 zero,\$6
+[0-9a-f]+ <[^>]*> 48803800 mtc2 zero,\$7
+[0-9a-f]+ <[^>]*> 48804000 mtc2 zero,\$8
+[0-9a-f]+ <[^>]*> 48804800 mtc2 zero,\$9
+[0-9a-f]+ <[^>]*> 48805000 mtc2 zero,\$10
+[0-9a-f]+ <[^>]*> 48805800 mtc2 zero,\$11
+[0-9a-f]+ <[^>]*> 48806000 mtc2 zero,\$12
+[0-9a-f]+ <[^>]*> 48806800 mtc2 zero,\$13
+[0-9a-f]+ <[^>]*> 48807000 mtc2 zero,\$14
+[0-9a-f]+ <[^>]*> 48807800 mtc2 zero,\$15
+[0-9a-f]+ <[^>]*> 48808000 mtc2 zero,\$16
+[0-9a-f]+ <[^>]*> 48808800 mtc2 zero,\$17
+[0-9a-f]+ <[^>]*> 48809000 mtc2 zero,\$18
+[0-9a-f]+ <[^>]*> 48809800 mtc2 zero,\$19
+[0-9a-f]+ <[^>]*> 4880a000 mtc2 zero,\$20
+[0-9a-f]+ <[^>]*> 4880a800 mtc2 zero,\$21
+[0-9a-f]+ <[^>]*> 4880b000 mtc2 zero,\$22
+[0-9a-f]+ <[^>]*> 4880b800 mtc2 zero,\$23
+[0-9a-f]+ <[^>]*> 4880c000 mtc2 zero,\$24
+[0-9a-f]+ <[^>]*> 4880c800 mtc2 zero,\$25
+[0-9a-f]+ <[^>]*> 4880d000 mtc2 zero,\$26
+[0-9a-f]+ <[^>]*> 4880d800 mtc2 zero,\$27
+[0-9a-f]+ <[^>]*> 4880e000 mtc2 zero,\$28
+[0-9a-f]+ <[^>]*> 4880e800 mtc2 zero,\$29
+[0-9a-f]+ <[^>]*> 4880f000 mtc2 zero,\$30
+[0-9a-f]+ <[^>]*> 4880f800 mtc2 zero,\$31
+[0-9a-f]+ <[^>]*> 48000000 mfc2 zero,\$0
+[0-9a-f]+ <[^>]*> 48000800 mfc2 zero,\$1
+[0-9a-f]+ <[^>]*> 48001000 mfc2 zero,\$2
+[0-9a-f]+ <[^>]*> 48001800 mfc2 zero,\$3
+[0-9a-f]+ <[^>]*> 48002000 mfc2 zero,\$4
+[0-9a-f]+ <[^>]*> 48002800 mfc2 zero,\$5
+[0-9a-f]+ <[^>]*> 48003000 mfc2 zero,\$6
+[0-9a-f]+ <[^>]*> 48003800 mfc2 zero,\$7
+[0-9a-f]+ <[^>]*> 48004000 mfc2 zero,\$8
+[0-9a-f]+ <[^>]*> 48004800 mfc2 zero,\$9
+[0-9a-f]+ <[^>]*> 48005000 mfc2 zero,\$10
+[0-9a-f]+ <[^>]*> 48005800 mfc2 zero,\$11
+[0-9a-f]+ <[^>]*> 48006000 mfc2 zero,\$12
+[0-9a-f]+ <[^>]*> 48006800 mfc2 zero,\$13
+[0-9a-f]+ <[^>]*> 48007000 mfc2 zero,\$14
+[0-9a-f]+ <[^>]*> 48007800 mfc2 zero,\$15
+[0-9a-f]+ <[^>]*> 48008000 mfc2 zero,\$16
+[0-9a-f]+ <[^>]*> 48008800 mfc2 zero,\$17
+[0-9a-f]+ <[^>]*> 48009000 mfc2 zero,\$18
+[0-9a-f]+ <[^>]*> 48009800 mfc2 zero,\$19
+[0-9a-f]+ <[^>]*> 4800a000 mfc2 zero,\$20
+[0-9a-f]+ <[^>]*> 4800a800 mfc2 zero,\$21
+[0-9a-f]+ <[^>]*> 4800b000 mfc2 zero,\$22
+[0-9a-f]+ <[^>]*> 4800b800 mfc2 zero,\$23
+[0-9a-f]+ <[^>]*> 4800c000 mfc2 zero,\$24
+[0-9a-f]+ <[^>]*> 4800c800 mfc2 zero,\$25
+[0-9a-f]+ <[^>]*> 4800d000 mfc2 zero,\$26
+[0-9a-f]+ <[^>]*> 4800d800 mfc2 zero,\$27
+[0-9a-f]+ <[^>]*> 4800e000 mfc2 zero,\$28
+[0-9a-f]+ <[^>]*> 4800e800 mfc2 zero,\$29
+[0-9a-f]+ <[^>]*> 4800f000 mfc2 zero,\$30
+[0-9a-f]+ <[^>]*> 4800f800 mfc2 zero,\$31
+[0-9a-f]+ <[^>]*> 48c00000 ctc2 zero,\$0
+[0-9a-f]+ <[^>]*> 48c00800 ctc2 zero,\$1
+[0-9a-f]+ <[^>]*> 48c01000 ctc2 zero,\$2
+[0-9a-f]+ <[^>]*> 48c01800 ctc2 zero,\$3
+[0-9a-f]+ <[^>]*> 48c02000 ctc2 zero,\$4
+[0-9a-f]+ <[^>]*> 48c02800 ctc2 zero,\$5
+[0-9a-f]+ <[^>]*> 48c03000 ctc2 zero,\$6
+[0-9a-f]+ <[^>]*> 48c03800 ctc2 zero,\$7
+[0-9a-f]+ <[^>]*> 48c04000 ctc2 zero,\$8
+[0-9a-f]+ <[^>]*> 48c04800 ctc2 zero,\$9
+[0-9a-f]+ <[^>]*> 48c05000 ctc2 zero,\$10
+[0-9a-f]+ <[^>]*> 48c05800 ctc2 zero,\$11
+[0-9a-f]+ <[^>]*> 48c06000 ctc2 zero,\$12
+[0-9a-f]+ <[^>]*> 48c06800 ctc2 zero,\$13
+[0-9a-f]+ <[^>]*> 48c07000 ctc2 zero,\$14
+[0-9a-f]+ <[^>]*> 48c07800 ctc2 zero,\$15
+[0-9a-f]+ <[^>]*> 48c08000 ctc2 zero,\$16
+[0-9a-f]+ <[^>]*> 48c08800 ctc2 zero,\$17
+[0-9a-f]+ <[^>]*> 48c09000 ctc2 zero,\$18
+[0-9a-f]+ <[^>]*> 48c09800 ctc2 zero,\$19
+[0-9a-f]+ <[^>]*> 48c0a000 ctc2 zero,\$20
+[0-9a-f]+ <[^>]*> 48c0a800 ctc2 zero,\$21
+[0-9a-f]+ <[^>]*> 48c0b000 ctc2 zero,\$22
+[0-9a-f]+ <[^>]*> 48c0b800 ctc2 zero,\$23
+[0-9a-f]+ <[^>]*> 48c0c000 ctc2 zero,\$24
+[0-9a-f]+ <[^>]*> 48c0c800 ctc2 zero,\$25
+[0-9a-f]+ <[^>]*> 48c0d000 ctc2 zero,\$26
+[0-9a-f]+ <[^>]*> 48c0d800 ctc2 zero,\$27
+[0-9a-f]+ <[^>]*> 48c0e000 ctc2 zero,\$28
+[0-9a-f]+ <[^>]*> 48c0e800 ctc2 zero,\$29
+[0-9a-f]+ <[^>]*> 48c0f000 ctc2 zero,\$30
+[0-9a-f]+ <[^>]*> 48c0f800 ctc2 zero,\$31
+[0-9a-f]+ <[^>]*> 48400000 cfc2 zero,\$0
+[0-9a-f]+ <[^>]*> 48400800 cfc2 zero,\$1
+[0-9a-f]+ <[^>]*> 48401000 cfc2 zero,\$2
+[0-9a-f]+ <[^>]*> 48401800 cfc2 zero,\$3
+[0-9a-f]+ <[^>]*> 48402000 cfc2 zero,\$4
+[0-9a-f]+ <[^>]*> 48402800 cfc2 zero,\$5
+[0-9a-f]+ <[^>]*> 48403000 cfc2 zero,\$6
+[0-9a-f]+ <[^>]*> 48403800 cfc2 zero,\$7
+[0-9a-f]+ <[^>]*> 48404000 cfc2 zero,\$8
+[0-9a-f]+ <[^>]*> 48404800 cfc2 zero,\$9
+[0-9a-f]+ <[^>]*> 48405000 cfc2 zero,\$10
+[0-9a-f]+ <[^>]*> 48405800 cfc2 zero,\$11
+[0-9a-f]+ <[^>]*> 48406000 cfc2 zero,\$12
+[0-9a-f]+ <[^>]*> 48406800 cfc2 zero,\$13
+[0-9a-f]+ <[^>]*> 48407000 cfc2 zero,\$14
+[0-9a-f]+ <[^>]*> 48407800 cfc2 zero,\$15
+[0-9a-f]+ <[^>]*> 48408000 cfc2 zero,\$16
+[0-9a-f]+ <[^>]*> 48408800 cfc2 zero,\$17
+[0-9a-f]+ <[^>]*> 48409000 cfc2 zero,\$18
+[0-9a-f]+ <[^>]*> 48409800 cfc2 zero,\$19
+[0-9a-f]+ <[^>]*> 4840a000 cfc2 zero,\$20
+[0-9a-f]+ <[^>]*> 4840a800 cfc2 zero,\$21
+[0-9a-f]+ <[^>]*> 4840b000 cfc2 zero,\$22
+[0-9a-f]+ <[^>]*> 4840b800 cfc2 zero,\$23
+[0-9a-f]+ <[^>]*> 4840c000 cfc2 zero,\$24
+[0-9a-f]+ <[^>]*> 4840c800 cfc2 zero,\$25
+[0-9a-f]+ <[^>]*> 4840d000 cfc2 zero,\$26
+[0-9a-f]+ <[^>]*> 4840d800 cfc2 zero,\$27
+[0-9a-f]+ <[^>]*> 4840e000 cfc2 zero,\$28
+[0-9a-f]+ <[^>]*> 4840e800 cfc2 zero,\$29
+[0-9a-f]+ <[^>]*> 4840f000 cfc2 zero,\$30
+[0-9a-f]+ <[^>]*> 4840f800 cfc2 zero,\$31
+ \.\.\.
Index: binutils-gdb/gas/testsuite/gas/mips/cp2.s
===================================================================
--- /dev/null
+++ binutils-gdb/gas/testsuite/gas/mips/cp2.s
@@ -0,0 +1,138 @@
+ .text
+ .set noreorder
+foo:
+ mtc2 $0, $0
+ mtc2 $0, $1
+ mtc2 $0, $2
+ mtc2 $0, $3
+ mtc2 $0, $4
+ mtc2 $0, $5
+ mtc2 $0, $6
+ mtc2 $0, $7
+ mtc2 $0, $8
+ mtc2 $0, $9
+ mtc2 $0, $10
+ mtc2 $0, $11
+ mtc2 $0, $12
+ mtc2 $0, $13
+ mtc2 $0, $14
+ mtc2 $0, $15
+ mtc2 $0, $16
+ mtc2 $0, $17
+ mtc2 $0, $18
+ mtc2 $0, $19
+ mtc2 $0, $20
+ mtc2 $0, $21
+ mtc2 $0, $22
+ mtc2 $0, $23
+ mtc2 $0, $24
+ mtc2 $0, $25
+ mtc2 $0, $26
+ mtc2 $0, $27
+ mtc2 $0, $28
+ mtc2 $0, $29
+ mtc2 $0, $30
+ mtc2 $0, $31
+
+ mfc2 $0, $0
+ mfc2 $0, $1
+ mfc2 $0, $2
+ mfc2 $0, $3
+ mfc2 $0, $4
+ mfc2 $0, $5
+ mfc2 $0, $6
+ mfc2 $0, $7
+ mfc2 $0, $8
+ mfc2 $0, $9
+ mfc2 $0, $10
+ mfc2 $0, $11
+ mfc2 $0, $12
+ mfc2 $0, $13
+ mfc2 $0, $14
+ mfc2 $0, $15
+ mfc2 $0, $16
+ mfc2 $0, $17
+ mfc2 $0, $18
+ mfc2 $0, $19
+ mfc2 $0, $20
+ mfc2 $0, $21
+ mfc2 $0, $22
+ mfc2 $0, $23
+ mfc2 $0, $24
+ mfc2 $0, $25
+ mfc2 $0, $26
+ mfc2 $0, $27
+ mfc2 $0, $28
+ mfc2 $0, $29
+ mfc2 $0, $30
+ mfc2 $0, $31
+
+ ctc2 $0, $0
+ ctc2 $0, $1
+ ctc2 $0, $2
+ ctc2 $0, $3
+ ctc2 $0, $4
+ ctc2 $0, $5
+ ctc2 $0, $6
+ ctc2 $0, $7
+ ctc2 $0, $8
+ ctc2 $0, $9
+ ctc2 $0, $10
+ ctc2 $0, $11
+ ctc2 $0, $12
+ ctc2 $0, $13
+ ctc2 $0, $14
+ ctc2 $0, $15
+ ctc2 $0, $16
+ ctc2 $0, $17
+ ctc2 $0, $18
+ ctc2 $0, $19
+ ctc2 $0, $20
+ ctc2 $0, $21
+ ctc2 $0, $22
+ ctc2 $0, $23
+ ctc2 $0, $24
+ ctc2 $0, $25
+ ctc2 $0, $26
+ ctc2 $0, $27
+ ctc2 $0, $28
+ ctc2 $0, $29
+ ctc2 $0, $30
+ ctc2 $0, $31
+
+ cfc2 $0, $0
+ cfc2 $0, $1
+ cfc2 $0, $2
+ cfc2 $0, $3
+ cfc2 $0, $4
+ cfc2 $0, $5
+ cfc2 $0, $6
+ cfc2 $0, $7
+ cfc2 $0, $8
+ cfc2 $0, $9
+ cfc2 $0, $10
+ cfc2 $0, $11
+ cfc2 $0, $12
+ cfc2 $0, $13
+ cfc2 $0, $14
+ cfc2 $0, $15
+ cfc2 $0, $16
+ cfc2 $0, $17
+ cfc2 $0, $18
+ cfc2 $0, $19
+ cfc2 $0, $20
+ cfc2 $0, $21
+ cfc2 $0, $22
+ cfc2 $0, $23
+ cfc2 $0, $24
+ cfc2 $0, $25
+ cfc2 $0, $26
+ cfc2 $0, $27
+ cfc2 $0, $28
+ cfc2 $0, $29
+ cfc2 $0, $30
+ cfc2 $0, $31
+
+# Force some (non-delay-slot) zero bytes, to make 'objdump' print ...
+ .align 4, 0
+ .space 16
Index: binutils-gdb/gas/testsuite/gas/mips/cp2d.d
===================================================================
--- /dev/null
+++ binutils-gdb/gas/testsuite/gas/mips/cp2d.d
@@ -0,0 +1,72 @@
+#objdump: -d --prefix-addresses --show-raw-insn
+#name: MIPS CP2 doubleword memory access instructions
+#as: -32
+
+.*: +file format .*mips.*
+
+Disassembly of section \.text:
+[0-9a-f]+ <[^>]*> d8000000 ldc2 \$0,0\(zero\)
+[0-9a-f]+ <[^>]*> d8010000 ldc2 \$1,0\(zero\)
+[0-9a-f]+ <[^>]*> d8020000 ldc2 \$2,0\(zero\)
+[0-9a-f]+ <[^>]*> d8030000 ldc2 \$3,0\(zero\)
+[0-9a-f]+ <[^>]*> d8040000 ldc2 \$4,0\(zero\)
+[0-9a-f]+ <[^>]*> d8050000 ldc2 \$5,0\(zero\)
+[0-9a-f]+ <[^>]*> d8060000 ldc2 \$6,0\(zero\)
+[0-9a-f]+ <[^>]*> d8070000 ldc2 \$7,0\(zero\)
+[0-9a-f]+ <[^>]*> d8080000 ldc2 \$8,0\(zero\)
+[0-9a-f]+ <[^>]*> d8090000 ldc2 \$9,0\(zero\)
+[0-9a-f]+ <[^>]*> d80a0000 ldc2 \$10,0\(zero\)
+[0-9a-f]+ <[^>]*> d80b0000 ldc2 \$11,0\(zero\)
+[0-9a-f]+ <[^>]*> d80c0000 ldc2 \$12,0\(zero\)
+[0-9a-f]+ <[^>]*> d80d0000 ldc2 \$13,0\(zero\)
+[0-9a-f]+ <[^>]*> d80e0000 ldc2 \$14,0\(zero\)
+[0-9a-f]+ <[^>]*> d80f0000 ldc2 \$15,0\(zero\)
+[0-9a-f]+ <[^>]*> d8100000 ldc2 \$16,0\(zero\)
+[0-9a-f]+ <[^>]*> d8110000 ldc2 \$17,0\(zero\)
+[0-9a-f]+ <[^>]*> d8120000 ldc2 \$18,0\(zero\)
+[0-9a-f]+ <[^>]*> d8130000 ldc2 \$19,0\(zero\)
+[0-9a-f]+ <[^>]*> d8140000 ldc2 \$20,0\(zero\)
+[0-9a-f]+ <[^>]*> d8150000 ldc2 \$21,0\(zero\)
+[0-9a-f]+ <[^>]*> d8160000 ldc2 \$22,0\(zero\)
+[0-9a-f]+ <[^>]*> d8170000 ldc2 \$23,0\(zero\)
+[0-9a-f]+ <[^>]*> d8180000 ldc2 \$24,0\(zero\)
+[0-9a-f]+ <[^>]*> d8190000 ldc2 \$25,0\(zero\)
+[0-9a-f]+ <[^>]*> d81a0000 ldc2 \$26,0\(zero\)
+[0-9a-f]+ <[^>]*> d81b0000 ldc2 \$27,0\(zero\)
+[0-9a-f]+ <[^>]*> d81c0000 ldc2 \$28,0\(zero\)
+[0-9a-f]+ <[^>]*> d81d0000 ldc2 \$29,0\(zero\)
+[0-9a-f]+ <[^>]*> d81e0000 ldc2 \$30,0\(zero\)
+[0-9a-f]+ <[^>]*> d81f0000 ldc2 \$31,0\(zero\)
+[0-9a-f]+ <[^>]*> f8000000 sdc2 \$0,0\(zero\)
+[0-9a-f]+ <[^>]*> f8010000 sdc2 \$1,0\(zero\)
+[0-9a-f]+ <[^>]*> f8020000 sdc2 \$2,0\(zero\)
+[0-9a-f]+ <[^>]*> f8030000 sdc2 \$3,0\(zero\)
+[0-9a-f]+ <[^>]*> f8040000 sdc2 \$4,0\(zero\)
+[0-9a-f]+ <[^>]*> f8050000 sdc2 \$5,0\(zero\)
+[0-9a-f]+ <[^>]*> f8060000 sdc2 \$6,0\(zero\)
+[0-9a-f]+ <[^>]*> f8070000 sdc2 \$7,0\(zero\)
+[0-9a-f]+ <[^>]*> f8080000 sdc2 \$8,0\(zero\)
+[0-9a-f]+ <[^>]*> f8090000 sdc2 \$9,0\(zero\)
+[0-9a-f]+ <[^>]*> f80a0000 sdc2 \$10,0\(zero\)
+[0-9a-f]+ <[^>]*> f80b0000 sdc2 \$11,0\(zero\)
+[0-9a-f]+ <[^>]*> f80c0000 sdc2 \$12,0\(zero\)
+[0-9a-f]+ <[^>]*> f80d0000 sdc2 \$13,0\(zero\)
+[0-9a-f]+ <[^>]*> f80e0000 sdc2 \$14,0\(zero\)
+[0-9a-f]+ <[^>]*> f80f0000 sdc2 \$15,0\(zero\)
+[0-9a-f]+ <[^>]*> f8100000 sdc2 \$16,0\(zero\)
+[0-9a-f]+ <[^>]*> f8110000 sdc2 \$17,0\(zero\)
+[0-9a-f]+ <[^>]*> f8120000 sdc2 \$18,0\(zero\)
+[0-9a-f]+ <[^>]*> f8130000 sdc2 \$19,0\(zero\)
+[0-9a-f]+ <[^>]*> f8140000 sdc2 \$20,0\(zero\)
+[0-9a-f]+ <[^>]*> f8150000 sdc2 \$21,0\(zero\)
+[0-9a-f]+ <[^>]*> f8160000 sdc2 \$22,0\(zero\)
+[0-9a-f]+ <[^>]*> f8170000 sdc2 \$23,0\(zero\)
+[0-9a-f]+ <[^>]*> f8180000 sdc2 \$24,0\(zero\)
+[0-9a-f]+ <[^>]*> f8190000 sdc2 \$25,0\(zero\)
+[0-9a-f]+ <[^>]*> f81a0000 sdc2 \$26,0\(zero\)
+[0-9a-f]+ <[^>]*> f81b0000 sdc2 \$27,0\(zero\)
+[0-9a-f]+ <[^>]*> f81c0000 sdc2 \$28,0\(zero\)
+[0-9a-f]+ <[^>]*> f81d0000 sdc2 \$29,0\(zero\)
+[0-9a-f]+ <[^>]*> f81e0000 sdc2 \$30,0\(zero\)
+[0-9a-f]+ <[^>]*> f81f0000 sdc2 \$31,0\(zero\)
+ \.\.\.
Index: binutils-gdb/gas/testsuite/gas/mips/cp2d.s
===================================================================
--- /dev/null
+++ binutils-gdb/gas/testsuite/gas/mips/cp2d.s
@@ -0,0 +1,71 @@
+ .text
+foo:
+ ldc2 $0, 0($0)
+ ldc2 $1, 0($0)
+ ldc2 $2, 0($0)
+ ldc2 $3, 0($0)
+ ldc2 $4, 0($0)
+ ldc2 $5, 0($0)
+ ldc2 $6, 0($0)
+ ldc2 $7, 0($0)
+ ldc2 $8, 0($0)
+ ldc2 $9, 0($0)
+ ldc2 $10, 0($0)
+ ldc2 $11, 0($0)
+ ldc2 $12, 0($0)
+ ldc2 $13, 0($0)
+ ldc2 $14, 0($0)
+ ldc2 $15, 0($0)
+ ldc2 $16, 0($0)
+ ldc2 $17, 0($0)
+ ldc2 $18, 0($0)
+ ldc2 $19, 0($0)
+ ldc2 $20, 0($0)
+ ldc2 $21, 0($0)
+ ldc2 $22, 0($0)
+ ldc2 $23, 0($0)
+ ldc2 $24, 0($0)
+ ldc2 $25, 0($0)
+ ldc2 $26, 0($0)
+ ldc2 $27, 0($0)
+ ldc2 $28, 0($0)
+ ldc2 $29, 0($0)
+ ldc2 $30, 0($0)
+ ldc2 $31, 0($0)
+
+ sdc2 $0, 0($0)
+ sdc2 $1, 0($0)
+ sdc2 $2, 0($0)
+ sdc2 $3, 0($0)
+ sdc2 $4, 0($0)
+ sdc2 $5, 0($0)
+ sdc2 $6, 0($0)
+ sdc2 $7, 0($0)
+ sdc2 $8, 0($0)
+ sdc2 $9, 0($0)
+ sdc2 $10, 0($0)
+ sdc2 $11, 0($0)
+ sdc2 $12, 0($0)
+ sdc2 $13, 0($0)
+ sdc2 $14, 0($0)
+ sdc2 $15, 0($0)
+ sdc2 $16, 0($0)
+ sdc2 $17, 0($0)
+ sdc2 $18, 0($0)
+ sdc2 $19, 0($0)
+ sdc2 $20, 0($0)
+ sdc2 $21, 0($0)
+ sdc2 $22, 0($0)
+ sdc2 $23, 0($0)
+ sdc2 $24, 0($0)
+ sdc2 $25, 0($0)
+ sdc2 $26, 0($0)
+ sdc2 $27, 0($0)
+ sdc2 $28, 0($0)
+ sdc2 $29, 0($0)
+ sdc2 $30, 0($0)
+ sdc2 $31, 0($0)
+
+# Force some (non-delay-slot) zero bytes, to make 'objdump' print ...
+ .align 4, 0
+ .space 16
Index: binutils-gdb/gas/testsuite/gas/mips/cp2m.d
===================================================================
--- /dev/null
+++ binutils-gdb/gas/testsuite/gas/mips/cp2m.d
@@ -0,0 +1,72 @@
+#objdump: -d --prefix-addresses --show-raw-insn
+#name: MIPS CP2 memory access instructions
+#as: -32
+
+.*: +file format .*mips.*
+
+Disassembly of section \.text:
+[0-9a-f]+ <[^>]*> c8000000 lwc2 \$0,0\(zero\)
+[0-9a-f]+ <[^>]*> c8010000 lwc2 \$1,0\(zero\)
+[0-9a-f]+ <[^>]*> c8020000 lwc2 \$2,0\(zero\)
+[0-9a-f]+ <[^>]*> c8030000 lwc2 \$3,0\(zero\)
+[0-9a-f]+ <[^>]*> c8040000 lwc2 \$4,0\(zero\)
+[0-9a-f]+ <[^>]*> c8050000 lwc2 \$5,0\(zero\)
+[0-9a-f]+ <[^>]*> c8060000 lwc2 \$6,0\(zero\)
+[0-9a-f]+ <[^>]*> c8070000 lwc2 \$7,0\(zero\)
+[0-9a-f]+ <[^>]*> c8080000 lwc2 \$8,0\(zero\)
+[0-9a-f]+ <[^>]*> c8090000 lwc2 \$9,0\(zero\)
+[0-9a-f]+ <[^>]*> c80a0000 lwc2 \$10,0\(zero\)
+[0-9a-f]+ <[^>]*> c80b0000 lwc2 \$11,0\(zero\)
+[0-9a-f]+ <[^>]*> c80c0000 lwc2 \$12,0\(zero\)
+[0-9a-f]+ <[^>]*> c80d0000 lwc2 \$13,0\(zero\)
+[0-9a-f]+ <[^>]*> c80e0000 lwc2 \$14,0\(zero\)
+[0-9a-f]+ <[^>]*> c80f0000 lwc2 \$15,0\(zero\)
+[0-9a-f]+ <[^>]*> c8100000 lwc2 \$16,0\(zero\)
+[0-9a-f]+ <[^>]*> c8110000 lwc2 \$17,0\(zero\)
+[0-9a-f]+ <[^>]*> c8120000 lwc2 \$18,0\(zero\)
+[0-9a-f]+ <[^>]*> c8130000 lwc2 \$19,0\(zero\)
+[0-9a-f]+ <[^>]*> c8140000 lwc2 \$20,0\(zero\)
+[0-9a-f]+ <[^>]*> c8150000 lwc2 \$21,0\(zero\)
+[0-9a-f]+ <[^>]*> c8160000 lwc2 \$22,0\(zero\)
+[0-9a-f]+ <[^>]*> c8170000 lwc2 \$23,0\(zero\)
+[0-9a-f]+ <[^>]*> c8180000 lwc2 \$24,0\(zero\)
+[0-9a-f]+ <[^>]*> c8190000 lwc2 \$25,0\(zero\)
+[0-9a-f]+ <[^>]*> c81a0000 lwc2 \$26,0\(zero\)
+[0-9a-f]+ <[^>]*> c81b0000 lwc2 \$27,0\(zero\)
+[0-9a-f]+ <[^>]*> c81c0000 lwc2 \$28,0\(zero\)
+[0-9a-f]+ <[^>]*> c81d0000 lwc2 \$29,0\(zero\)
+[0-9a-f]+ <[^>]*> c81e0000 lwc2 \$30,0\(zero\)
+[0-9a-f]+ <[^>]*> c81f0000 lwc2 \$31,0\(zero\)
+[0-9a-f]+ <[^>]*> e8000000 swc2 \$0,0\(zero\)
+[0-9a-f]+ <[^>]*> e8010000 swc2 \$1,0\(zero\)
+[0-9a-f]+ <[^>]*> e8020000 swc2 \$2,0\(zero\)
+[0-9a-f]+ <[^>]*> e8030000 swc2 \$3,0\(zero\)
+[0-9a-f]+ <[^>]*> e8040000 swc2 \$4,0\(zero\)
+[0-9a-f]+ <[^>]*> e8050000 swc2 \$5,0\(zero\)
+[0-9a-f]+ <[^>]*> e8060000 swc2 \$6,0\(zero\)
+[0-9a-f]+ <[^>]*> e8070000 swc2 \$7,0\(zero\)
+[0-9a-f]+ <[^>]*> e8080000 swc2 \$8,0\(zero\)
+[0-9a-f]+ <[^>]*> e8090000 swc2 \$9,0\(zero\)
+[0-9a-f]+ <[^>]*> e80a0000 swc2 \$10,0\(zero\)
+[0-9a-f]+ <[^>]*> e80b0000 swc2 \$11,0\(zero\)
+[0-9a-f]+ <[^>]*> e80c0000 swc2 \$12,0\(zero\)
+[0-9a-f]+ <[^>]*> e80d0000 swc2 \$13,0\(zero\)
+[0-9a-f]+ <[^>]*> e80e0000 swc2 \$14,0\(zero\)
+[0-9a-f]+ <[^>]*> e80f0000 swc2 \$15,0\(zero\)
+[0-9a-f]+ <[^>]*> e8100000 swc2 \$16,0\(zero\)
+[0-9a-f]+ <[^>]*> e8110000 swc2 \$17,0\(zero\)
+[0-9a-f]+ <[^>]*> e8120000 swc2 \$18,0\(zero\)
+[0-9a-f]+ <[^>]*> e8130000 swc2 \$19,0\(zero\)
+[0-9a-f]+ <[^>]*> e8140000 swc2 \$20,0\(zero\)
+[0-9a-f]+ <[^>]*> e8150000 swc2 \$21,0\(zero\)
+[0-9a-f]+ <[^>]*> e8160000 swc2 \$22,0\(zero\)
+[0-9a-f]+ <[^>]*> e8170000 swc2 \$23,0\(zero\)
+[0-9a-f]+ <[^>]*> e8180000 swc2 \$24,0\(zero\)
+[0-9a-f]+ <[^>]*> e8190000 swc2 \$25,0\(zero\)
+[0-9a-f]+ <[^>]*> e81a0000 swc2 \$26,0\(zero\)
+[0-9a-f]+ <[^>]*> e81b0000 swc2 \$27,0\(zero\)
+[0-9a-f]+ <[^>]*> e81c0000 swc2 \$28,0\(zero\)
+[0-9a-f]+ <[^>]*> e81d0000 swc2 \$29,0\(zero\)
+[0-9a-f]+ <[^>]*> e81e0000 swc2 \$30,0\(zero\)
+[0-9a-f]+ <[^>]*> e81f0000 swc2 \$31,0\(zero\)
+ \.\.\.
Index: binutils-gdb/gas/testsuite/gas/mips/cp2m.s
===================================================================
--- /dev/null
+++ binutils-gdb/gas/testsuite/gas/mips/cp2m.s
@@ -0,0 +1,72 @@
+ .text
+ .set noreorder
+foo:
+ lwc2 $0, 0($0)
+ lwc2 $1, 0($0)
+ lwc2 $2, 0($0)
+ lwc2 $3, 0($0)
+ lwc2 $4, 0($0)
+ lwc2 $5, 0($0)
+ lwc2 $6, 0($0)
+ lwc2 $7, 0($0)
+ lwc2 $8, 0($0)
+ lwc2 $9, 0($0)
+ lwc2 $10, 0($0)
+ lwc2 $11, 0($0)
+ lwc2 $12, 0($0)
+ lwc2 $13, 0($0)
+ lwc2 $14, 0($0)
+ lwc2 $15, 0($0)
+ lwc2 $16, 0($0)
+ lwc2 $17, 0($0)
+ lwc2 $18, 0($0)
+ lwc2 $19, 0($0)
+ lwc2 $20, 0($0)
+ lwc2 $21, 0($0)
+ lwc2 $22, 0($0)
+ lwc2 $23, 0($0)
+ lwc2 $24, 0($0)
+ lwc2 $25, 0($0)
+ lwc2 $26, 0($0)
+ lwc2 $27, 0($0)
+ lwc2 $28, 0($0)
+ lwc2 $29, 0($0)
+ lwc2 $30, 0($0)
+ lwc2 $31, 0($0)
+
+ swc2 $0, 0($0)
+ swc2 $1, 0($0)
+ swc2 $2, 0($0)
+ swc2 $3, 0($0)
+ swc2 $4, 0($0)
+ swc2 $5, 0($0)
+ swc2 $6, 0($0)
+ swc2 $7, 0($0)
+ swc2 $8, 0($0)
+ swc2 $9, 0($0)
+ swc2 $10, 0($0)
+ swc2 $11, 0($0)
+ swc2 $12, 0($0)
+ swc2 $13, 0($0)
+ swc2 $14, 0($0)
+ swc2 $15, 0($0)
+ swc2 $16, 0($0)
+ swc2 $17, 0($0)
+ swc2 $18, 0($0)
+ swc2 $19, 0($0)
+ swc2 $20, 0($0)
+ swc2 $21, 0($0)
+ swc2 $22, 0($0)
+ swc2 $23, 0($0)
+ swc2 $24, 0($0)
+ swc2 $25, 0($0)
+ swc2 $26, 0($0)
+ swc2 $27, 0($0)
+ swc2 $28, 0($0)
+ swc2 $29, 0($0)
+ swc2 $30, 0($0)
+ swc2 $31, 0($0)
+
+# Force some (non-delay-slot) zero bytes, to make 'objdump' print ...
+ .align 4, 0
+ .space 16
Index: binutils-gdb/gas/testsuite/gas/mips/cp3.d
===================================================================
--- /dev/null
+++ binutils-gdb/gas/testsuite/gas/mips/cp3.d
@@ -0,0 +1,136 @@
+#objdump: -d --prefix-addresses --show-raw-insn
+#name: MIPS CP3 register move instructions
+#as: -32
+
+.*: +file format .*mips.*
+
+Disassembly of section \.text:
+[0-9a-f]+ <[^>]*> 4c800000 mtc3 zero,\$0
+[0-9a-f]+ <[^>]*> 4c800800 mtc3 zero,\$1
+[0-9a-f]+ <[^>]*> 4c801000 mtc3 zero,\$2
+[0-9a-f]+ <[^>]*> 4c801800 mtc3 zero,\$3
+[0-9a-f]+ <[^>]*> 4c802000 mtc3 zero,\$4
+[0-9a-f]+ <[^>]*> 4c802800 mtc3 zero,\$5
+[0-9a-f]+ <[^>]*> 4c803000 mtc3 zero,\$6
+[0-9a-f]+ <[^>]*> 4c803800 mtc3 zero,\$7
+[0-9a-f]+ <[^>]*> 4c804000 mtc3 zero,\$8
+[0-9a-f]+ <[^>]*> 4c804800 mtc3 zero,\$9
+[0-9a-f]+ <[^>]*> 4c805000 mtc3 zero,\$10
+[0-9a-f]+ <[^>]*> 4c805800 mtc3 zero,\$11
+[0-9a-f]+ <[^>]*> 4c806000 mtc3 zero,\$12
+[0-9a-f]+ <[^>]*> 4c806800 mtc3 zero,\$13
+[0-9a-f]+ <[^>]*> 4c807000 mtc3 zero,\$14
+[0-9a-f]+ <[^>]*> 4c807800 mtc3 zero,\$15
+[0-9a-f]+ <[^>]*> 4c808000 mtc3 zero,\$16
+[0-9a-f]+ <[^>]*> 4c808800 mtc3 zero,\$17
+[0-9a-f]+ <[^>]*> 4c809000 mtc3 zero,\$18
+[0-9a-f]+ <[^>]*> 4c809800 mtc3 zero,\$19
+[0-9a-f]+ <[^>]*> 4c80a000 mtc3 zero,\$20
+[0-9a-f]+ <[^>]*> 4c80a800 mtc3 zero,\$21
+[0-9a-f]+ <[^>]*> 4c80b000 mtc3 zero,\$22
+[0-9a-f]+ <[^>]*> 4c80b800 mtc3 zero,\$23
+[0-9a-f]+ <[^>]*> 4c80c000 mtc3 zero,\$24
+[0-9a-f]+ <[^>]*> 4c80c800 mtc3 zero,\$25
+[0-9a-f]+ <[^>]*> 4c80d000 mtc3 zero,\$26
+[0-9a-f]+ <[^>]*> 4c80d800 mtc3 zero,\$27
+[0-9a-f]+ <[^>]*> 4c80e000 mtc3 zero,\$28
+[0-9a-f]+ <[^>]*> 4c80e800 mtc3 zero,\$29
+[0-9a-f]+ <[^>]*> 4c80f000 mtc3 zero,\$30
+[0-9a-f]+ <[^>]*> 4c80f800 mtc3 zero,\$31
+[0-9a-f]+ <[^>]*> 4c000000 mfc3 zero,\$0
+[0-9a-f]+ <[^>]*> 4c000800 mfc3 zero,\$1
+[0-9a-f]+ <[^>]*> 4c001000 mfc3 zero,\$2
+[0-9a-f]+ <[^>]*> 4c001800 mfc3 zero,\$3
+[0-9a-f]+ <[^>]*> 4c002000 mfc3 zero,\$4
+[0-9a-f]+ <[^>]*> 4c002800 mfc3 zero,\$5
+[0-9a-f]+ <[^>]*> 4c003000 mfc3 zero,\$6
+[0-9a-f]+ <[^>]*> 4c003800 mfc3 zero,\$7
+[0-9a-f]+ <[^>]*> 4c004000 mfc3 zero,\$8
+[0-9a-f]+ <[^>]*> 4c004800 mfc3 zero,\$9
+[0-9a-f]+ <[^>]*> 4c005000 mfc3 zero,\$10
+[0-9a-f]+ <[^>]*> 4c005800 mfc3 zero,\$11
+[0-9a-f]+ <[^>]*> 4c006000 mfc3 zero,\$12
+[0-9a-f]+ <[^>]*> 4c006800 mfc3 zero,\$13
+[0-9a-f]+ <[^>]*> 4c007000 mfc3 zero,\$14
+[0-9a-f]+ <[^>]*> 4c007800 mfc3 zero,\$15
+[0-9a-f]+ <[^>]*> 4c008000 mfc3 zero,\$16
+[0-9a-f]+ <[^>]*> 4c008800 mfc3 zero,\$17
+[0-9a-f]+ <[^>]*> 4c009000 mfc3 zero,\$18
+[0-9a-f]+ <[^>]*> 4c009800 mfc3 zero,\$19
+[0-9a-f]+ <[^>]*> 4c00a000 mfc3 zero,\$20
+[0-9a-f]+ <[^>]*> 4c00a800 mfc3 zero,\$21
+[0-9a-f]+ <[^>]*> 4c00b000 mfc3 zero,\$22
+[0-9a-f]+ <[^>]*> 4c00b800 mfc3 zero,\$23
+[0-9a-f]+ <[^>]*> 4c00c000 mfc3 zero,\$24
+[0-9a-f]+ <[^>]*> 4c00c800 mfc3 zero,\$25
+[0-9a-f]+ <[^>]*> 4c00d000 mfc3 zero,\$26
+[0-9a-f]+ <[^>]*> 4c00d800 mfc3 zero,\$27
+[0-9a-f]+ <[^>]*> 4c00e000 mfc3 zero,\$28
+[0-9a-f]+ <[^>]*> 4c00e800 mfc3 zero,\$29
+[0-9a-f]+ <[^>]*> 4c00f000 mfc3 zero,\$30
+[0-9a-f]+ <[^>]*> 4c00f800 mfc3 zero,\$31
+[0-9a-f]+ <[^>]*> 4cc00000 ctc3 zero,\$0
+[0-9a-f]+ <[^>]*> 4cc00800 ctc3 zero,\$1
+[0-9a-f]+ <[^>]*> 4cc01000 ctc3 zero,\$2
+[0-9a-f]+ <[^>]*> 4cc01800 ctc3 zero,\$3
+[0-9a-f]+ <[^>]*> 4cc02000 ctc3 zero,\$4
+[0-9a-f]+ <[^>]*> 4cc02800 ctc3 zero,\$5
+[0-9a-f]+ <[^>]*> 4cc03000 ctc3 zero,\$6
+[0-9a-f]+ <[^>]*> 4cc03800 ctc3 zero,\$7
+[0-9a-f]+ <[^>]*> 4cc04000 ctc3 zero,\$8
+[0-9a-f]+ <[^>]*> 4cc04800 ctc3 zero,\$9
+[0-9a-f]+ <[^>]*> 4cc05000 ctc3 zero,\$10
+[0-9a-f]+ <[^>]*> 4cc05800 ctc3 zero,\$11
+[0-9a-f]+ <[^>]*> 4cc06000 ctc3 zero,\$12
+[0-9a-f]+ <[^>]*> 4cc06800 ctc3 zero,\$13
+[0-9a-f]+ <[^>]*> 4cc07000 ctc3 zero,\$14
+[0-9a-f]+ <[^>]*> 4cc07800 ctc3 zero,\$15
+[0-9a-f]+ <[^>]*> 4cc08000 ctc3 zero,\$16
+[0-9a-f]+ <[^>]*> 4cc08800 ctc3 zero,\$17
+[0-9a-f]+ <[^>]*> 4cc09000 ctc3 zero,\$18
+[0-9a-f]+ <[^>]*> 4cc09800 ctc3 zero,\$19
+[0-9a-f]+ <[^>]*> 4cc0a000 ctc3 zero,\$20
+[0-9a-f]+ <[^>]*> 4cc0a800 ctc3 zero,\$21
+[0-9a-f]+ <[^>]*> 4cc0b000 ctc3 zero,\$22
+[0-9a-f]+ <[^>]*> 4cc0b800 ctc3 zero,\$23
+[0-9a-f]+ <[^>]*> 4cc0c000 ctc3 zero,\$24
+[0-9a-f]+ <[^>]*> 4cc0c800 ctc3 zero,\$25
+[0-9a-f]+ <[^>]*> 4cc0d000 ctc3 zero,\$26
+[0-9a-f]+ <[^>]*> 4cc0d800 ctc3 zero,\$27
+[0-9a-f]+ <[^>]*> 4cc0e000 ctc3 zero,\$28
+[0-9a-f]+ <[^>]*> 4cc0e800 ctc3 zero,\$29
+[0-9a-f]+ <[^>]*> 4cc0f000 ctc3 zero,\$30
+[0-9a-f]+ <[^>]*> 4cc0f800 ctc3 zero,\$31
+[0-9a-f]+ <[^>]*> 4c400000 cfc3 zero,\$0
+[0-9a-f]+ <[^>]*> 4c400800 cfc3 zero,\$1
+[0-9a-f]+ <[^>]*> 4c401000 cfc3 zero,\$2
+[0-9a-f]+ <[^>]*> 4c401800 cfc3 zero,\$3
+[0-9a-f]+ <[^>]*> 4c402000 cfc3 zero,\$4
+[0-9a-f]+ <[^>]*> 4c402800 cfc3 zero,\$5
+[0-9a-f]+ <[^>]*> 4c403000 cfc3 zero,\$6
+[0-9a-f]+ <[^>]*> 4c403800 cfc3 zero,\$7
+[0-9a-f]+ <[^>]*> 4c404000 cfc3 zero,\$8
+[0-9a-f]+ <[^>]*> 4c404800 cfc3 zero,\$9
+[0-9a-f]+ <[^>]*> 4c405000 cfc3 zero,\$10
+[0-9a-f]+ <[^>]*> 4c405800 cfc3 zero,\$11
+[0-9a-f]+ <[^>]*> 4c406000 cfc3 zero,\$12
+[0-9a-f]+ <[^>]*> 4c406800 cfc3 zero,\$13
+[0-9a-f]+ <[^>]*> 4c407000 cfc3 zero,\$14
+[0-9a-f]+ <[^>]*> 4c407800 cfc3 zero,\$15
+[0-9a-f]+ <[^>]*> 4c408000 cfc3 zero,\$16
+[0-9a-f]+ <[^>]*> 4c408800 cfc3 zero,\$17
+[0-9a-f]+ <[^>]*> 4c409000 cfc3 zero,\$18
+[0-9a-f]+ <[^>]*> 4c409800 cfc3 zero,\$19
+[0-9a-f]+ <[^>]*> 4c40a000 cfc3 zero,\$20
+[0-9a-f]+ <[^>]*> 4c40a800 cfc3 zero,\$21
+[0-9a-f]+ <[^>]*> 4c40b000 cfc3 zero,\$22
+[0-9a-f]+ <[^>]*> 4c40b800 cfc3 zero,\$23
+[0-9a-f]+ <[^>]*> 4c40c000 cfc3 zero,\$24
+[0-9a-f]+ <[^>]*> 4c40c800 cfc3 zero,\$25
+[0-9a-f]+ <[^>]*> 4c40d000 cfc3 zero,\$26
+[0-9a-f]+ <[^>]*> 4c40d800 cfc3 zero,\$27
+[0-9a-f]+ <[^>]*> 4c40e000 cfc3 zero,\$28
+[0-9a-f]+ <[^>]*> 4c40e800 cfc3 zero,\$29
+[0-9a-f]+ <[^>]*> 4c40f000 cfc3 zero,\$30
+[0-9a-f]+ <[^>]*> 4c40f800 cfc3 zero,\$31
+ \.\.\.
Index: binutils-gdb/gas/testsuite/gas/mips/cp3.s
===================================================================
--- /dev/null
+++ binutils-gdb/gas/testsuite/gas/mips/cp3.s
@@ -0,0 +1,138 @@
+ .text
+ .set noreorder
+foo:
+ mtc3 $0, $0
+ mtc3 $0, $1
+ mtc3 $0, $2
+ mtc3 $0, $3
+ mtc3 $0, $4
+ mtc3 $0, $5
+ mtc3 $0, $6
+ mtc3 $0, $7
+ mtc3 $0, $8
+ mtc3 $0, $9
+ mtc3 $0, $10
+ mtc3 $0, $11
+ mtc3 $0, $12
+ mtc3 $0, $13
+ mtc3 $0, $14
+ mtc3 $0, $15
+ mtc3 $0, $16
+ mtc3 $0, $17
+ mtc3 $0, $18
+ mtc3 $0, $19
+ mtc3 $0, $20
+ mtc3 $0, $21
+ mtc3 $0, $22
+ mtc3 $0, $23
+ mtc3 $0, $24
+ mtc3 $0, $25
+ mtc3 $0, $26
+ mtc3 $0, $27
+ mtc3 $0, $28
+ mtc3 $0, $29
+ mtc3 $0, $30
+ mtc3 $0, $31
+
+ mfc3 $0, $0
+ mfc3 $0, $1
+ mfc3 $0, $2
+ mfc3 $0, $3
+ mfc3 $0, $4
+ mfc3 $0, $5
+ mfc3 $0, $6
+ mfc3 $0, $7
+ mfc3 $0, $8
+ mfc3 $0, $9
+ mfc3 $0, $10
+ mfc3 $0, $11
+ mfc3 $0, $12
+ mfc3 $0, $13
+ mfc3 $0, $14
+ mfc3 $0, $15
+ mfc3 $0, $16
+ mfc3 $0, $17
+ mfc3 $0, $18
+ mfc3 $0, $19
+ mfc3 $0, $20
+ mfc3 $0, $21
+ mfc3 $0, $22
+ mfc3 $0, $23
+ mfc3 $0, $24
+ mfc3 $0, $25
+ mfc3 $0, $26
+ mfc3 $0, $27
+ mfc3 $0, $28
+ mfc3 $0, $29
+ mfc3 $0, $30
+ mfc3 $0, $31
+
+ ctc3 $0, $0
+ ctc3 $0, $1
+ ctc3 $0, $2
+ ctc3 $0, $3
+ ctc3 $0, $4
+ ctc3 $0, $5
+ ctc3 $0, $6
+ ctc3 $0, $7
+ ctc3 $0, $8
+ ctc3 $0, $9
+ ctc3 $0, $10
+ ctc3 $0, $11
+ ctc3 $0, $12
+ ctc3 $0, $13
+ ctc3 $0, $14
+ ctc3 $0, $15
+ ctc3 $0, $16
+ ctc3 $0, $17
+ ctc3 $0, $18
+ ctc3 $0, $19
+ ctc3 $0, $20
+ ctc3 $0, $21
+ ctc3 $0, $22
+ ctc3 $0, $23
+ ctc3 $0, $24
+ ctc3 $0, $25
+ ctc3 $0, $26
+ ctc3 $0, $27
+ ctc3 $0, $28
+ ctc3 $0, $29
+ ctc3 $0, $30
+ ctc3 $0, $31
+
+ cfc3 $0, $0
+ cfc3 $0, $1
+ cfc3 $0, $2
+ cfc3 $0, $3
+ cfc3 $0, $4
+ cfc3 $0, $5
+ cfc3 $0, $6
+ cfc3 $0, $7
+ cfc3 $0, $8
+ cfc3 $0, $9
+ cfc3 $0, $10
+ cfc3 $0, $11
+ cfc3 $0, $12
+ cfc3 $0, $13
+ cfc3 $0, $14
+ cfc3 $0, $15
+ cfc3 $0, $16
+ cfc3 $0, $17
+ cfc3 $0, $18
+ cfc3 $0, $19
+ cfc3 $0, $20
+ cfc3 $0, $21
+ cfc3 $0, $22
+ cfc3 $0, $23
+ cfc3 $0, $24
+ cfc3 $0, $25
+ cfc3 $0, $26
+ cfc3 $0, $27
+ cfc3 $0, $28
+ cfc3 $0, $29
+ cfc3 $0, $30
+ cfc3 $0, $31
+
+# Force some (non-delay-slot) zero bytes, to make 'objdump' print ...
+ .align 4, 0
+ .space 16
Index: binutils-gdb/gas/testsuite/gas/mips/cp3d.d
===================================================================
--- /dev/null
+++ binutils-gdb/gas/testsuite/gas/mips/cp3d.d
@@ -0,0 +1,72 @@
+#objdump: -d --prefix-addresses --show-raw-insn
+#name: MIPS CP3 doubleword memory access instructions
+#as: -32
+
+.*: +file format .*mips.*
+
+Disassembly of section \.text:
+[0-9a-f]+ <[^>]*> dc000000 ldc3 \$0,0\(zero\)
+[0-9a-f]+ <[^>]*> dc010000 ldc3 \$1,0\(zero\)
+[0-9a-f]+ <[^>]*> dc020000 ldc3 \$2,0\(zero\)
+[0-9a-f]+ <[^>]*> dc030000 ldc3 \$3,0\(zero\)
+[0-9a-f]+ <[^>]*> dc040000 ldc3 \$4,0\(zero\)
+[0-9a-f]+ <[^>]*> dc050000 ldc3 \$5,0\(zero\)
+[0-9a-f]+ <[^>]*> dc060000 ldc3 \$6,0\(zero\)
+[0-9a-f]+ <[^>]*> dc070000 ldc3 \$7,0\(zero\)
+[0-9a-f]+ <[^>]*> dc080000 ldc3 \$8,0\(zero\)
+[0-9a-f]+ <[^>]*> dc090000 ldc3 \$9,0\(zero\)
+[0-9a-f]+ <[^>]*> dc0a0000 ldc3 \$10,0\(zero\)
+[0-9a-f]+ <[^>]*> dc0b0000 ldc3 \$11,0\(zero\)
+[0-9a-f]+ <[^>]*> dc0c0000 ldc3 \$12,0\(zero\)
+[0-9a-f]+ <[^>]*> dc0d0000 ldc3 \$13,0\(zero\)
+[0-9a-f]+ <[^>]*> dc0e0000 ldc3 \$14,0\(zero\)
+[0-9a-f]+ <[^>]*> dc0f0000 ldc3 \$15,0\(zero\)
+[0-9a-f]+ <[^>]*> dc100000 ldc3 \$16,0\(zero\)
+[0-9a-f]+ <[^>]*> dc110000 ldc3 \$17,0\(zero\)
+[0-9a-f]+ <[^>]*> dc120000 ldc3 \$18,0\(zero\)
+[0-9a-f]+ <[^>]*> dc130000 ldc3 \$19,0\(zero\)
+[0-9a-f]+ <[^>]*> dc140000 ldc3 \$20,0\(zero\)
+[0-9a-f]+ <[^>]*> dc150000 ldc3 \$21,0\(zero\)
+[0-9a-f]+ <[^>]*> dc160000 ldc3 \$22,0\(zero\)
+[0-9a-f]+ <[^>]*> dc170000 ldc3 \$23,0\(zero\)
+[0-9a-f]+ <[^>]*> dc180000 ldc3 \$24,0\(zero\)
+[0-9a-f]+ <[^>]*> dc190000 ldc3 \$25,0\(zero\)
+[0-9a-f]+ <[^>]*> dc1a0000 ldc3 \$26,0\(zero\)
+[0-9a-f]+ <[^>]*> dc1b0000 ldc3 \$27,0\(zero\)
+[0-9a-f]+ <[^>]*> dc1c0000 ldc3 \$28,0\(zero\)
+[0-9a-f]+ <[^>]*> dc1d0000 ldc3 \$29,0\(zero\)
+[0-9a-f]+ <[^>]*> dc1e0000 ldc3 \$30,0\(zero\)
+[0-9a-f]+ <[^>]*> dc1f0000 ldc3 \$31,0\(zero\)
+[0-9a-f]+ <[^>]*> fc000000 sdc3 \$0,0\(zero\)
+[0-9a-f]+ <[^>]*> fc010000 sdc3 \$1,0\(zero\)
+[0-9a-f]+ <[^>]*> fc020000 sdc3 \$2,0\(zero\)
+[0-9a-f]+ <[^>]*> fc030000 sdc3 \$3,0\(zero\)
+[0-9a-f]+ <[^>]*> fc040000 sdc3 \$4,0\(zero\)
+[0-9a-f]+ <[^>]*> fc050000 sdc3 \$5,0\(zero\)
+[0-9a-f]+ <[^>]*> fc060000 sdc3 \$6,0\(zero\)
+[0-9a-f]+ <[^>]*> fc070000 sdc3 \$7,0\(zero\)
+[0-9a-f]+ <[^>]*> fc080000 sdc3 \$8,0\(zero\)
+[0-9a-f]+ <[^>]*> fc090000 sdc3 \$9,0\(zero\)
+[0-9a-f]+ <[^>]*> fc0a0000 sdc3 \$10,0\(zero\)
+[0-9a-f]+ <[^>]*> fc0b0000 sdc3 \$11,0\(zero\)
+[0-9a-f]+ <[^>]*> fc0c0000 sdc3 \$12,0\(zero\)
+[0-9a-f]+ <[^>]*> fc0d0000 sdc3 \$13,0\(zero\)
+[0-9a-f]+ <[^>]*> fc0e0000 sdc3 \$14,0\(zero\)
+[0-9a-f]+ <[^>]*> fc0f0000 sdc3 \$15,0\(zero\)
+[0-9a-f]+ <[^>]*> fc100000 sdc3 \$16,0\(zero\)
+[0-9a-f]+ <[^>]*> fc110000 sdc3 \$17,0\(zero\)
+[0-9a-f]+ <[^>]*> fc120000 sdc3 \$18,0\(zero\)
+[0-9a-f]+ <[^>]*> fc130000 sdc3 \$19,0\(zero\)
+[0-9a-f]+ <[^>]*> fc140000 sdc3 \$20,0\(zero\)
+[0-9a-f]+ <[^>]*> fc150000 sdc3 \$21,0\(zero\)
+[0-9a-f]+ <[^>]*> fc160000 sdc3 \$22,0\(zero\)
+[0-9a-f]+ <[^>]*> fc170000 sdc3 \$23,0\(zero\)
+[0-9a-f]+ <[^>]*> fc180000 sdc3 \$24,0\(zero\)
+[0-9a-f]+ <[^>]*> fc190000 sdc3 \$25,0\(zero\)
+[0-9a-f]+ <[^>]*> fc1a0000 sdc3 \$26,0\(zero\)
+[0-9a-f]+ <[^>]*> fc1b0000 sdc3 \$27,0\(zero\)
+[0-9a-f]+ <[^>]*> fc1c0000 sdc3 \$28,0\(zero\)
+[0-9a-f]+ <[^>]*> fc1d0000 sdc3 \$29,0\(zero\)
+[0-9a-f]+ <[^>]*> fc1e0000 sdc3 \$30,0\(zero\)
+[0-9a-f]+ <[^>]*> fc1f0000 sdc3 \$31,0\(zero\)
+ \.\.\.
Index: binutils-gdb/gas/testsuite/gas/mips/cp3d.s
===================================================================
--- /dev/null
+++ binutils-gdb/gas/testsuite/gas/mips/cp3d.s
@@ -0,0 +1,72 @@
+ .text
+ .set noreorder
+foo:
+ ldc3 $0, 0($0)
+ ldc3 $1, 0($0)
+ ldc3 $2, 0($0)
+ ldc3 $3, 0($0)
+ ldc3 $4, 0($0)
+ ldc3 $5, 0($0)
+ ldc3 $6, 0($0)
+ ldc3 $7, 0($0)
+ ldc3 $8, 0($0)
+ ldc3 $9, 0($0)
+ ldc3 $10, 0($0)
+ ldc3 $11, 0($0)
+ ldc3 $12, 0($0)
+ ldc3 $13, 0($0)
+ ldc3 $14, 0($0)
+ ldc3 $15, 0($0)
+ ldc3 $16, 0($0)
+ ldc3 $17, 0($0)
+ ldc3 $18, 0($0)
+ ldc3 $19, 0($0)
+ ldc3 $20, 0($0)
+ ldc3 $21, 0($0)
+ ldc3 $22, 0($0)
+ ldc3 $23, 0($0)
+ ldc3 $24, 0($0)
+ ldc3 $25, 0($0)
+ ldc3 $26, 0($0)
+ ldc3 $27, 0($0)
+ ldc3 $28, 0($0)
+ ldc3 $29, 0($0)
+ ldc3 $30, 0($0)
+ ldc3 $31, 0($0)
+
+ sdc3 $0, 0($0)
+ sdc3 $1, 0($0)
+ sdc3 $2, 0($0)
+ sdc3 $3, 0($0)
+ sdc3 $4, 0($0)
+ sdc3 $5, 0($0)
+ sdc3 $6, 0($0)
+ sdc3 $7, 0($0)
+ sdc3 $8, 0($0)
+ sdc3 $9, 0($0)
+ sdc3 $10, 0($0)
+ sdc3 $11, 0($0)
+ sdc3 $12, 0($0)
+ sdc3 $13, 0($0)
+ sdc3 $14, 0($0)
+ sdc3 $15, 0($0)
+ sdc3 $16, 0($0)
+ sdc3 $17, 0($0)
+ sdc3 $18, 0($0)
+ sdc3 $19, 0($0)
+ sdc3 $20, 0($0)
+ sdc3 $21, 0($0)
+ sdc3 $22, 0($0)
+ sdc3 $23, 0($0)
+ sdc3 $24, 0($0)
+ sdc3 $25, 0($0)
+ sdc3 $26, 0($0)
+ sdc3 $27, 0($0)
+ sdc3 $28, 0($0)
+ sdc3 $29, 0($0)
+ sdc3 $30, 0($0)
+ sdc3 $31, 0($0)
+
+# Force some (non-delay-slot) zero bytes, to make 'objdump' print ...
+ .align 4, 0
+ .space 16
Index: binutils-gdb/gas/testsuite/gas/mips/cp3m.d
===================================================================
--- /dev/null
+++ binutils-gdb/gas/testsuite/gas/mips/cp3m.d
@@ -0,0 +1,72 @@
+#objdump: -d --prefix-addresses --show-raw-insn
+#name: MIPS CP3 memory access instructions
+#as: -32
+
+.*: +file format .*mips.*
+
+Disassembly of section \.text:
+[0-9a-f]+ <[^>]*> cc000000 lwc3 \$0,0\(zero\)
+[0-9a-f]+ <[^>]*> cc010000 lwc3 \$1,0\(zero\)
+[0-9a-f]+ <[^>]*> cc020000 lwc3 \$2,0\(zero\)
+[0-9a-f]+ <[^>]*> cc030000 lwc3 \$3,0\(zero\)
+[0-9a-f]+ <[^>]*> cc040000 lwc3 \$4,0\(zero\)
+[0-9a-f]+ <[^>]*> cc050000 lwc3 \$5,0\(zero\)
+[0-9a-f]+ <[^>]*> cc060000 lwc3 \$6,0\(zero\)
+[0-9a-f]+ <[^>]*> cc070000 lwc3 \$7,0\(zero\)
+[0-9a-f]+ <[^>]*> cc080000 lwc3 \$8,0\(zero\)
+[0-9a-f]+ <[^>]*> cc090000 lwc3 \$9,0\(zero\)
+[0-9a-f]+ <[^>]*> cc0a0000 lwc3 \$10,0\(zero\)
+[0-9a-f]+ <[^>]*> cc0b0000 lwc3 \$11,0\(zero\)
+[0-9a-f]+ <[^>]*> cc0c0000 lwc3 \$12,0\(zero\)
+[0-9a-f]+ <[^>]*> cc0d0000 lwc3 \$13,0\(zero\)
+[0-9a-f]+ <[^>]*> cc0e0000 lwc3 \$14,0\(zero\)
+[0-9a-f]+ <[^>]*> cc0f0000 lwc3 \$15,0\(zero\)
+[0-9a-f]+ <[^>]*> cc100000 lwc3 \$16,0\(zero\)
+[0-9a-f]+ <[^>]*> cc110000 lwc3 \$17,0\(zero\)
+[0-9a-f]+ <[^>]*> cc120000 lwc3 \$18,0\(zero\)
+[0-9a-f]+ <[^>]*> cc130000 lwc3 \$19,0\(zero\)
+[0-9a-f]+ <[^>]*> cc140000 lwc3 \$20,0\(zero\)
+[0-9a-f]+ <[^>]*> cc150000 lwc3 \$21,0\(zero\)
+[0-9a-f]+ <[^>]*> cc160000 lwc3 \$22,0\(zero\)
+[0-9a-f]+ <[^>]*> cc170000 lwc3 \$23,0\(zero\)
+[0-9a-f]+ <[^>]*> cc180000 lwc3 \$24,0\(zero\)
+[0-9a-f]+ <[^>]*> cc190000 lwc3 \$25,0\(zero\)
+[0-9a-f]+ <[^>]*> cc1a0000 lwc3 \$26,0\(zero\)
+[0-9a-f]+ <[^>]*> cc1b0000 lwc3 \$27,0\(zero\)
+[0-9a-f]+ <[^>]*> cc1c0000 lwc3 \$28,0\(zero\)
+[0-9a-f]+ <[^>]*> cc1d0000 lwc3 \$29,0\(zero\)
+[0-9a-f]+ <[^>]*> cc1e0000 lwc3 \$30,0\(zero\)
+[0-9a-f]+ <[^>]*> cc1f0000 lwc3 \$31,0\(zero\)
+[0-9a-f]+ <[^>]*> ec000000 swc3 \$0,0\(zero\)
+[0-9a-f]+ <[^>]*> ec010000 swc3 \$1,0\(zero\)
+[0-9a-f]+ <[^>]*> ec020000 swc3 \$2,0\(zero\)
+[0-9a-f]+ <[^>]*> ec030000 swc3 \$3,0\(zero\)
+[0-9a-f]+ <[^>]*> ec040000 swc3 \$4,0\(zero\)
+[0-9a-f]+ <[^>]*> ec050000 swc3 \$5,0\(zero\)
+[0-9a-f]+ <[^>]*> ec060000 swc3 \$6,0\(zero\)
+[0-9a-f]+ <[^>]*> ec070000 swc3 \$7,0\(zero\)
+[0-9a-f]+ <[^>]*> ec080000 swc3 \$8,0\(zero\)
+[0-9a-f]+ <[^>]*> ec090000 swc3 \$9,0\(zero\)
+[0-9a-f]+ <[^>]*> ec0a0000 swc3 \$10,0\(zero\)
+[0-9a-f]+ <[^>]*> ec0b0000 swc3 \$11,0\(zero\)
+[0-9a-f]+ <[^>]*> ec0c0000 swc3 \$12,0\(zero\)
+[0-9a-f]+ <[^>]*> ec0d0000 swc3 \$13,0\(zero\)
+[0-9a-f]+ <[^>]*> ec0e0000 swc3 \$14,0\(zero\)
+[0-9a-f]+ <[^>]*> ec0f0000 swc3 \$15,0\(zero\)
+[0-9a-f]+ <[^>]*> ec100000 swc3 \$16,0\(zero\)
+[0-9a-f]+ <[^>]*> ec110000 swc3 \$17,0\(zero\)
+[0-9a-f]+ <[^>]*> ec120000 swc3 \$18,0\(zero\)
+[0-9a-f]+ <[^>]*> ec130000 swc3 \$19,0\(zero\)
+[0-9a-f]+ <[^>]*> ec140000 swc3 \$20,0\(zero\)
+[0-9a-f]+ <[^>]*> ec150000 swc3 \$21,0\(zero\)
+[0-9a-f]+ <[^>]*> ec160000 swc3 \$22,0\(zero\)
+[0-9a-f]+ <[^>]*> ec170000 swc3 \$23,0\(zero\)
+[0-9a-f]+ <[^>]*> ec180000 swc3 \$24,0\(zero\)
+[0-9a-f]+ <[^>]*> ec190000 swc3 \$25,0\(zero\)
+[0-9a-f]+ <[^>]*> ec1a0000 swc3 \$26,0\(zero\)
+[0-9a-f]+ <[^>]*> ec1b0000 swc3 \$27,0\(zero\)
+[0-9a-f]+ <[^>]*> ec1c0000 swc3 \$28,0\(zero\)
+[0-9a-f]+ <[^>]*> ec1d0000 swc3 \$29,0\(zero\)
+[0-9a-f]+ <[^>]*> ec1e0000 swc3 \$30,0\(zero\)
+[0-9a-f]+ <[^>]*> ec1f0000 swc3 \$31,0\(zero\)
+ \.\.\.
Index: binutils-gdb/gas/testsuite/gas/mips/cp3m.s
===================================================================
--- /dev/null
+++ binutils-gdb/gas/testsuite/gas/mips/cp3m.s
@@ -0,0 +1,72 @@
+ .text
+ .set noreorder
+foo:
+ lwc3 $0, 0($0)
+ lwc3 $1, 0($0)
+ lwc3 $2, 0($0)
+ lwc3 $3, 0($0)
+ lwc3 $4, 0($0)
+ lwc3 $5, 0($0)
+ lwc3 $6, 0($0)
+ lwc3 $7, 0($0)
+ lwc3 $8, 0($0)
+ lwc3 $9, 0($0)
+ lwc3 $10, 0($0)
+ lwc3 $11, 0($0)
+ lwc3 $12, 0($0)
+ lwc3 $13, 0($0)
+ lwc3 $14, 0($0)
+ lwc3 $15, 0($0)
+ lwc3 $16, 0($0)
+ lwc3 $17, 0($0)
+ lwc3 $18, 0($0)
+ lwc3 $19, 0($0)
+ lwc3 $20, 0($0)
+ lwc3 $21, 0($0)
+ lwc3 $22, 0($0)
+ lwc3 $23, 0($0)
+ lwc3 $24, 0($0)
+ lwc3 $25, 0($0)
+ lwc3 $26, 0($0)
+ lwc3 $27, 0($0)
+ lwc3 $28, 0($0)
+ lwc3 $29, 0($0)
+ lwc3 $30, 0($0)
+ lwc3 $31, 0($0)
+
+ swc3 $0, 0($0)
+ swc3 $1, 0($0)
+ swc3 $2, 0($0)
+ swc3 $3, 0($0)
+ swc3 $4, 0($0)
+ swc3 $5, 0($0)
+ swc3 $6, 0($0)
+ swc3 $7, 0($0)
+ swc3 $8, 0($0)
+ swc3 $9, 0($0)
+ swc3 $10, 0($0)
+ swc3 $11, 0($0)
+ swc3 $12, 0($0)
+ swc3 $13, 0($0)
+ swc3 $14, 0($0)
+ swc3 $15, 0($0)
+ swc3 $16, 0($0)
+ swc3 $17, 0($0)
+ swc3 $18, 0($0)
+ swc3 $19, 0($0)
+ swc3 $20, 0($0)
+ swc3 $21, 0($0)
+ swc3 $22, 0($0)
+ swc3 $23, 0($0)
+ swc3 $24, 0($0)
+ swc3 $25, 0($0)
+ swc3 $26, 0($0)
+ swc3 $27, 0($0)
+ swc3 $28, 0($0)
+ swc3 $29, 0($0)
+ swc3 $30, 0($0)
+ swc3 $31, 0($0)
+
+# Force some (non-delay-slot) zero bytes, to make 'objdump' print ...
+ .align 4, 0
+ .space 16
Index: binutils-gdb/gas/testsuite/gas/mips/micromips@cp2-64.d
===================================================================
--- /dev/null
+++ binutils-gdb/gas/testsuite/gas/mips/micromips@cp2-64.d
@@ -0,0 +1,73 @@
+#objdump: -d --prefix-addresses --show-raw-insn
+#name: MIPS CP2 64-bit move instructions
+#as: -32
+#source: cp2-64\.s
+
+.*: +file format .*mips.*
+
+Disassembly of section \.text:
+[0-9a-f]+ <[^>]*> 0000 7d3c dmtc2 zero,\$0
+[0-9a-f]+ <[^>]*> 0001 7d3c dmtc2 zero,\$1
+[0-9a-f]+ <[^>]*> 0002 7d3c dmtc2 zero,\$2
+[0-9a-f]+ <[^>]*> 0003 7d3c dmtc2 zero,\$3
+[0-9a-f]+ <[^>]*> 0004 7d3c dmtc2 zero,\$4
+[0-9a-f]+ <[^>]*> 0005 7d3c dmtc2 zero,\$5
+[0-9a-f]+ <[^>]*> 0006 7d3c dmtc2 zero,\$6
+[0-9a-f]+ <[^>]*> 0007 7d3c dmtc2 zero,\$7
+[0-9a-f]+ <[^>]*> 0008 7d3c dmtc2 zero,\$8
+[0-9a-f]+ <[^>]*> 0009 7d3c dmtc2 zero,\$9
+[0-9a-f]+ <[^>]*> 000a 7d3c dmtc2 zero,\$10
+[0-9a-f]+ <[^>]*> 000b 7d3c dmtc2 zero,\$11
+[0-9a-f]+ <[^>]*> 000c 7d3c dmtc2 zero,\$12
+[0-9a-f]+ <[^>]*> 000d 7d3c dmtc2 zero,\$13
+[0-9a-f]+ <[^>]*> 000e 7d3c dmtc2 zero,\$14
+[0-9a-f]+ <[^>]*> 000f 7d3c dmtc2 zero,\$15
+[0-9a-f]+ <[^>]*> 0010 7d3c dmtc2 zero,\$16
+[0-9a-f]+ <[^>]*> 0011 7d3c dmtc2 zero,\$17
+[0-9a-f]+ <[^>]*> 0012 7d3c dmtc2 zero,\$18
+[0-9a-f]+ <[^>]*> 0013 7d3c dmtc2 zero,\$19
+[0-9a-f]+ <[^>]*> 0014 7d3c dmtc2 zero,\$20
+[0-9a-f]+ <[^>]*> 0015 7d3c dmtc2 zero,\$21
+[0-9a-f]+ <[^>]*> 0016 7d3c dmtc2 zero,\$22
+[0-9a-f]+ <[^>]*> 0017 7d3c dmtc2 zero,\$23
+[0-9a-f]+ <[^>]*> 0018 7d3c dmtc2 zero,\$24
+[0-9a-f]+ <[^>]*> 0019 7d3c dmtc2 zero,\$25
+[0-9a-f]+ <[^>]*> 001a 7d3c dmtc2 zero,\$26
+[0-9a-f]+ <[^>]*> 001b 7d3c dmtc2 zero,\$27
+[0-9a-f]+ <[^>]*> 001c 7d3c dmtc2 zero,\$28
+[0-9a-f]+ <[^>]*> 001d 7d3c dmtc2 zero,\$29
+[0-9a-f]+ <[^>]*> 001e 7d3c dmtc2 zero,\$30
+[0-9a-f]+ <[^>]*> 001f 7d3c dmtc2 zero,\$31
+[0-9a-f]+ <[^>]*> 0000 6d3c dmfc2 zero,\$0
+[0-9a-f]+ <[^>]*> 0001 6d3c dmfc2 zero,\$1
+[0-9a-f]+ <[^>]*> 0002 6d3c dmfc2 zero,\$2
+[0-9a-f]+ <[^>]*> 0003 6d3c dmfc2 zero,\$3
+[0-9a-f]+ <[^>]*> 0004 6d3c dmfc2 zero,\$4
+[0-9a-f]+ <[^>]*> 0005 6d3c dmfc2 zero,\$5
+[0-9a-f]+ <[^>]*> 0006 6d3c dmfc2 zero,\$6
+[0-9a-f]+ <[^>]*> 0007 6d3c dmfc2 zero,\$7
+[0-9a-f]+ <[^>]*> 0008 6d3c dmfc2 zero,\$8
+[0-9a-f]+ <[^>]*> 0009 6d3c dmfc2 zero,\$9
+[0-9a-f]+ <[^>]*> 000a 6d3c dmfc2 zero,\$10
+[0-9a-f]+ <[^>]*> 000b 6d3c dmfc2 zero,\$11
+[0-9a-f]+ <[^>]*> 000c 6d3c dmfc2 zero,\$12
+[0-9a-f]+ <[^>]*> 000d 6d3c dmfc2 zero,\$13
+[0-9a-f]+ <[^>]*> 000e 6d3c dmfc2 zero,\$14
+[0-9a-f]+ <[^>]*> 000f 6d3c dmfc2 zero,\$15
+[0-9a-f]+ <[^>]*> 0010 6d3c dmfc2 zero,\$16
+[0-9a-f]+ <[^>]*> 0011 6d3c dmfc2 zero,\$17
+[0-9a-f]+ <[^>]*> 0012 6d3c dmfc2 zero,\$18
+[0-9a-f]+ <[^>]*> 0013 6d3c dmfc2 zero,\$19
+[0-9a-f]+ <[^>]*> 0014 6d3c dmfc2 zero,\$20
+[0-9a-f]+ <[^>]*> 0015 6d3c dmfc2 zero,\$21
+[0-9a-f]+ <[^>]*> 0016 6d3c dmfc2 zero,\$22
+[0-9a-f]+ <[^>]*> 0017 6d3c dmfc2 zero,\$23
+[0-9a-f]+ <[^>]*> 0018 6d3c dmfc2 zero,\$24
+[0-9a-f]+ <[^>]*> 0019 6d3c dmfc2 zero,\$25
+[0-9a-f]+ <[^>]*> 001a 6d3c dmfc2 zero,\$26
+[0-9a-f]+ <[^>]*> 001b 6d3c dmfc2 zero,\$27
+[0-9a-f]+ <[^>]*> 001c 6d3c dmfc2 zero,\$28
+[0-9a-f]+ <[^>]*> 001d 6d3c dmfc2 zero,\$29
+[0-9a-f]+ <[^>]*> 001e 6d3c dmfc2 zero,\$30
+[0-9a-f]+ <[^>]*> 001f 6d3c dmfc2 zero,\$31
+ \.\.\.
Index: binutils-gdb/gas/testsuite/gas/mips/micromips@cp2.d
===================================================================
--- /dev/null
+++ binutils-gdb/gas/testsuite/gas/mips/micromips@cp2.d
@@ -0,0 +1,137 @@
+#objdump: -d --prefix-addresses --show-raw-insn
+#name: MIPS CP2 register move instructions
+#as: -32
+#source: cp2.s
+
+.*: +file format .*mips.*
+
+Disassembly of section \.text:
+[0-9a-f]+ <[^>]*> 0000 5d3c mtc2 zero,\$0
+[0-9a-f]+ <[^>]*> 0001 5d3c mtc2 zero,\$1
+[0-9a-f]+ <[^>]*> 0002 5d3c mtc2 zero,\$2
+[0-9a-f]+ <[^>]*> 0003 5d3c mtc2 zero,\$3
+[0-9a-f]+ <[^>]*> 0004 5d3c mtc2 zero,\$4
+[0-9a-f]+ <[^>]*> 0005 5d3c mtc2 zero,\$5
+[0-9a-f]+ <[^>]*> 0006 5d3c mtc2 zero,\$6
+[0-9a-f]+ <[^>]*> 0007 5d3c mtc2 zero,\$7
+[0-9a-f]+ <[^>]*> 0008 5d3c mtc2 zero,\$8
+[0-9a-f]+ <[^>]*> 0009 5d3c mtc2 zero,\$9
+[0-9a-f]+ <[^>]*> 000a 5d3c mtc2 zero,\$10
+[0-9a-f]+ <[^>]*> 000b 5d3c mtc2 zero,\$11
+[0-9a-f]+ <[^>]*> 000c 5d3c mtc2 zero,\$12
+[0-9a-f]+ <[^>]*> 000d 5d3c mtc2 zero,\$13
+[0-9a-f]+ <[^>]*> 000e 5d3c mtc2 zero,\$14
+[0-9a-f]+ <[^>]*> 000f 5d3c mtc2 zero,\$15
+[0-9a-f]+ <[^>]*> 0010 5d3c mtc2 zero,\$16
+[0-9a-f]+ <[^>]*> 0011 5d3c mtc2 zero,\$17
+[0-9a-f]+ <[^>]*> 0012 5d3c mtc2 zero,\$18
+[0-9a-f]+ <[^>]*> 0013 5d3c mtc2 zero,\$19
+[0-9a-f]+ <[^>]*> 0014 5d3c mtc2 zero,\$20
+[0-9a-f]+ <[^>]*> 0015 5d3c mtc2 zero,\$21
+[0-9a-f]+ <[^>]*> 0016 5d3c mtc2 zero,\$22
+[0-9a-f]+ <[^>]*> 0017 5d3c mtc2 zero,\$23
+[0-9a-f]+ <[^>]*> 0018 5d3c mtc2 zero,\$24
+[0-9a-f]+ <[^>]*> 0019 5d3c mtc2 zero,\$25
+[0-9a-f]+ <[^>]*> 001a 5d3c mtc2 zero,\$26
+[0-9a-f]+ <[^>]*> 001b 5d3c mtc2 zero,\$27
+[0-9a-f]+ <[^>]*> 001c 5d3c mtc2 zero,\$28
+[0-9a-f]+ <[^>]*> 001d 5d3c mtc2 zero,\$29
+[0-9a-f]+ <[^>]*> 001e 5d3c mtc2 zero,\$30
+[0-9a-f]+ <[^>]*> 001f 5d3c mtc2 zero,\$31
+[0-9a-f]+ <[^>]*> 0000 4d3c mfc2 zero,\$0
+[0-9a-f]+ <[^>]*> 0001 4d3c mfc2 zero,\$1
+[0-9a-f]+ <[^>]*> 0002 4d3c mfc2 zero,\$2
+[0-9a-f]+ <[^>]*> 0003 4d3c mfc2 zero,\$3
+[0-9a-f]+ <[^>]*> 0004 4d3c mfc2 zero,\$4
+[0-9a-f]+ <[^>]*> 0005 4d3c mfc2 zero,\$5
+[0-9a-f]+ <[^>]*> 0006 4d3c mfc2 zero,\$6
+[0-9a-f]+ <[^>]*> 0007 4d3c mfc2 zero,\$7
+[0-9a-f]+ <[^>]*> 0008 4d3c mfc2 zero,\$8
+[0-9a-f]+ <[^>]*> 0009 4d3c mfc2 zero,\$9
+[0-9a-f]+ <[^>]*> 000a 4d3c mfc2 zero,\$10
+[0-9a-f]+ <[^>]*> 000b 4d3c mfc2 zero,\$11
+[0-9a-f]+ <[^>]*> 000c 4d3c mfc2 zero,\$12
+[0-9a-f]+ <[^>]*> 000d 4d3c mfc2 zero,\$13
+[0-9a-f]+ <[^>]*> 000e 4d3c mfc2 zero,\$14
+[0-9a-f]+ <[^>]*> 000f 4d3c mfc2 zero,\$15
+[0-9a-f]+ <[^>]*> 0010 4d3c mfc2 zero,\$16
+[0-9a-f]+ <[^>]*> 0011 4d3c mfc2 zero,\$17
+[0-9a-f]+ <[^>]*> 0012 4d3c mfc2 zero,\$18
+[0-9a-f]+ <[^>]*> 0013 4d3c mfc2 zero,\$19
+[0-9a-f]+ <[^>]*> 0014 4d3c mfc2 zero,\$20
+[0-9a-f]+ <[^>]*> 0015 4d3c mfc2 zero,\$21
+[0-9a-f]+ <[^>]*> 0016 4d3c mfc2 zero,\$22
+[0-9a-f]+ <[^>]*> 0017 4d3c mfc2 zero,\$23
+[0-9a-f]+ <[^>]*> 0018 4d3c mfc2 zero,\$24
+[0-9a-f]+ <[^>]*> 0019 4d3c mfc2 zero,\$25
+[0-9a-f]+ <[^>]*> 001a 4d3c mfc2 zero,\$26
+[0-9a-f]+ <[^>]*> 001b 4d3c mfc2 zero,\$27
+[0-9a-f]+ <[^>]*> 001c 4d3c mfc2 zero,\$28
+[0-9a-f]+ <[^>]*> 001d 4d3c mfc2 zero,\$29
+[0-9a-f]+ <[^>]*> 001e 4d3c mfc2 zero,\$30
+[0-9a-f]+ <[^>]*> 001f 4d3c mfc2 zero,\$31
+[0-9a-f]+ <[^>]*> 0000 dd3c ctc2 zero,\$0
+[0-9a-f]+ <[^>]*> 0001 dd3c ctc2 zero,\$1
+[0-9a-f]+ <[^>]*> 0002 dd3c ctc2 zero,\$2
+[0-9a-f]+ <[^>]*> 0003 dd3c ctc2 zero,\$3
+[0-9a-f]+ <[^>]*> 0004 dd3c ctc2 zero,\$4
+[0-9a-f]+ <[^>]*> 0005 dd3c ctc2 zero,\$5
+[0-9a-f]+ <[^>]*> 0006 dd3c ctc2 zero,\$6
+[0-9a-f]+ <[^>]*> 0007 dd3c ctc2 zero,\$7
+[0-9a-f]+ <[^>]*> 0008 dd3c ctc2 zero,\$8
+[0-9a-f]+ <[^>]*> 0009 dd3c ctc2 zero,\$9
+[0-9a-f]+ <[^>]*> 000a dd3c ctc2 zero,\$10
+[0-9a-f]+ <[^>]*> 000b dd3c ctc2 zero,\$11
+[0-9a-f]+ <[^>]*> 000c dd3c ctc2 zero,\$12
+[0-9a-f]+ <[^>]*> 000d dd3c ctc2 zero,\$13
+[0-9a-f]+ <[^>]*> 000e dd3c ctc2 zero,\$14
+[0-9a-f]+ <[^>]*> 000f dd3c ctc2 zero,\$15
+[0-9a-f]+ <[^>]*> 0010 dd3c ctc2 zero,\$16
+[0-9a-f]+ <[^>]*> 0011 dd3c ctc2 zero,\$17
+[0-9a-f]+ <[^>]*> 0012 dd3c ctc2 zero,\$18
+[0-9a-f]+ <[^>]*> 0013 dd3c ctc2 zero,\$19
+[0-9a-f]+ <[^>]*> 0014 dd3c ctc2 zero,\$20
+[0-9a-f]+ <[^>]*> 0015 dd3c ctc2 zero,\$21
+[0-9a-f]+ <[^>]*> 0016 dd3c ctc2 zero,\$22
+[0-9a-f]+ <[^>]*> 0017 dd3c ctc2 zero,\$23
+[0-9a-f]+ <[^>]*> 0018 dd3c ctc2 zero,\$24
+[0-9a-f]+ <[^>]*> 0019 dd3c ctc2 zero,\$25
+[0-9a-f]+ <[^>]*> 001a dd3c ctc2 zero,\$26
+[0-9a-f]+ <[^>]*> 001b dd3c ctc2 zero,\$27
+[0-9a-f]+ <[^>]*> 001c dd3c ctc2 zero,\$28
+[0-9a-f]+ <[^>]*> 001d dd3c ctc2 zero,\$29
+[0-9a-f]+ <[^>]*> 001e dd3c ctc2 zero,\$30
+[0-9a-f]+ <[^>]*> 001f dd3c ctc2 zero,\$31
+[0-9a-f]+ <[^>]*> 0000 cd3c cfc2 zero,\$0
+[0-9a-f]+ <[^>]*> 0001 cd3c cfc2 zero,\$1
+[0-9a-f]+ <[^>]*> 0002 cd3c cfc2 zero,\$2
+[0-9a-f]+ <[^>]*> 0003 cd3c cfc2 zero,\$3
+[0-9a-f]+ <[^>]*> 0004 cd3c cfc2 zero,\$4
+[0-9a-f]+ <[^>]*> 0005 cd3c cfc2 zero,\$5
+[0-9a-f]+ <[^>]*> 0006 cd3c cfc2 zero,\$6
+[0-9a-f]+ <[^>]*> 0007 cd3c cfc2 zero,\$7
+[0-9a-f]+ <[^>]*> 0008 cd3c cfc2 zero,\$8
+[0-9a-f]+ <[^>]*> 0009 cd3c cfc2 zero,\$9
+[0-9a-f]+ <[^>]*> 000a cd3c cfc2 zero,\$10
+[0-9a-f]+ <[^>]*> 000b cd3c cfc2 zero,\$11
+[0-9a-f]+ <[^>]*> 000c cd3c cfc2 zero,\$12
+[0-9a-f]+ <[^>]*> 000d cd3c cfc2 zero,\$13
+[0-9a-f]+ <[^>]*> 000e cd3c cfc2 zero,\$14
+[0-9a-f]+ <[^>]*> 000f cd3c cfc2 zero,\$15
+[0-9a-f]+ <[^>]*> 0010 cd3c cfc2 zero,\$16
+[0-9a-f]+ <[^>]*> 0011 cd3c cfc2 zero,\$17
+[0-9a-f]+ <[^>]*> 0012 cd3c cfc2 zero,\$18
+[0-9a-f]+ <[^>]*> 0013 cd3c cfc2 zero,\$19
+[0-9a-f]+ <[^>]*> 0014 cd3c cfc2 zero,\$20
+[0-9a-f]+ <[^>]*> 0015 cd3c cfc2 zero,\$21
+[0-9a-f]+ <[^>]*> 0016 cd3c cfc2 zero,\$22
+[0-9a-f]+ <[^>]*> 0017 cd3c cfc2 zero,\$23
+[0-9a-f]+ <[^>]*> 0018 cd3c cfc2 zero,\$24
+[0-9a-f]+ <[^>]*> 0019 cd3c cfc2 zero,\$25
+[0-9a-f]+ <[^>]*> 001a cd3c cfc2 zero,\$26
+[0-9a-f]+ <[^>]*> 001b cd3c cfc2 zero,\$27
+[0-9a-f]+ <[^>]*> 001c cd3c cfc2 zero,\$28
+[0-9a-f]+ <[^>]*> 001d cd3c cfc2 zero,\$29
+[0-9a-f]+ <[^>]*> 001e cd3c cfc2 zero,\$30
+[0-9a-f]+ <[^>]*> 001f cd3c cfc2 zero,\$31
+ \.\.\.
Index: binutils-gdb/gas/testsuite/gas/mips/micromips@cp2d.d
===================================================================
--- /dev/null
+++ binutils-gdb/gas/testsuite/gas/mips/micromips@cp2d.d
@@ -0,0 +1,73 @@
+#objdump: -d --prefix-addresses --show-raw-insn
+#name: MIPS CP2 doubleword memory access instructions
+#as: -32
+#source: cp2d\.s
+
+.*: +file format .*mips.*
+
+Disassembly of section \.text:
+[0-9a-f]+ <[^>]*> 2000 2000 ldc2 \$0,0\(zero\)
+[0-9a-f]+ <[^>]*> 2020 2000 ldc2 \$1,0\(zero\)
+[0-9a-f]+ <[^>]*> 2040 2000 ldc2 \$2,0\(zero\)
+[0-9a-f]+ <[^>]*> 2060 2000 ldc2 \$3,0\(zero\)
+[0-9a-f]+ <[^>]*> 2080 2000 ldc2 \$4,0\(zero\)
+[0-9a-f]+ <[^>]*> 20a0 2000 ldc2 \$5,0\(zero\)
+[0-9a-f]+ <[^>]*> 20c0 2000 ldc2 \$6,0\(zero\)
+[0-9a-f]+ <[^>]*> 20e0 2000 ldc2 \$7,0\(zero\)
+[0-9a-f]+ <[^>]*> 2100 2000 ldc2 \$8,0\(zero\)
+[0-9a-f]+ <[^>]*> 2120 2000 ldc2 \$9,0\(zero\)
+[0-9a-f]+ <[^>]*> 2140 2000 ldc2 \$10,0\(zero\)
+[0-9a-f]+ <[^>]*> 2160 2000 ldc2 \$11,0\(zero\)
+[0-9a-f]+ <[^>]*> 2180 2000 ldc2 \$12,0\(zero\)
+[0-9a-f]+ <[^>]*> 21a0 2000 ldc2 \$13,0\(zero\)
+[0-9a-f]+ <[^>]*> 21c0 2000 ldc2 \$14,0\(zero\)
+[0-9a-f]+ <[^>]*> 21e0 2000 ldc2 \$15,0\(zero\)
+[0-9a-f]+ <[^>]*> 2200 2000 ldc2 \$16,0\(zero\)
+[0-9a-f]+ <[^>]*> 2220 2000 ldc2 \$17,0\(zero\)
+[0-9a-f]+ <[^>]*> 2240 2000 ldc2 \$18,0\(zero\)
+[0-9a-f]+ <[^>]*> 2260 2000 ldc2 \$19,0\(zero\)
+[0-9a-f]+ <[^>]*> 2280 2000 ldc2 \$20,0\(zero\)
+[0-9a-f]+ <[^>]*> 22a0 2000 ldc2 \$21,0\(zero\)
+[0-9a-f]+ <[^>]*> 22c0 2000 ldc2 \$22,0\(zero\)
+[0-9a-f]+ <[^>]*> 22e0 2000 ldc2 \$23,0\(zero\)
+[0-9a-f]+ <[^>]*> 2300 2000 ldc2 \$24,0\(zero\)
+[0-9a-f]+ <[^>]*> 2320 2000 ldc2 \$25,0\(zero\)
+[0-9a-f]+ <[^>]*> 2340 2000 ldc2 \$26,0\(zero\)
+[0-9a-f]+ <[^>]*> 2360 2000 ldc2 \$27,0\(zero\)
+[0-9a-f]+ <[^>]*> 2380 2000 ldc2 \$28,0\(zero\)
+[0-9a-f]+ <[^>]*> 23a0 2000 ldc2 \$29,0\(zero\)
+[0-9a-f]+ <[^>]*> 23c0 2000 ldc2 \$30,0\(zero\)
+[0-9a-f]+ <[^>]*> 23e0 2000 ldc2 \$31,0\(zero\)
+[0-9a-f]+ <[^>]*> 2000 a000 sdc2 \$0,0\(zero\)
+[0-9a-f]+ <[^>]*> 2020 a000 sdc2 \$1,0\(zero\)
+[0-9a-f]+ <[^>]*> 2040 a000 sdc2 \$2,0\(zero\)
+[0-9a-f]+ <[^>]*> 2060 a000 sdc2 \$3,0\(zero\)
+[0-9a-f]+ <[^>]*> 2080 a000 sdc2 \$4,0\(zero\)
+[0-9a-f]+ <[^>]*> 20a0 a000 sdc2 \$5,0\(zero\)
+[0-9a-f]+ <[^>]*> 20c0 a000 sdc2 \$6,0\(zero\)
+[0-9a-f]+ <[^>]*> 20e0 a000 sdc2 \$7,0\(zero\)
+[0-9a-f]+ <[^>]*> 2100 a000 sdc2 \$8,0\(zero\)
+[0-9a-f]+ <[^>]*> 2120 a000 sdc2 \$9,0\(zero\)
+[0-9a-f]+ <[^>]*> 2140 a000 sdc2 \$10,0\(zero\)
+[0-9a-f]+ <[^>]*> 2160 a000 sdc2 \$11,0\(zero\)
+[0-9a-f]+ <[^>]*> 2180 a000 sdc2 \$12,0\(zero\)
+[0-9a-f]+ <[^>]*> 21a0 a000 sdc2 \$13,0\(zero\)
+[0-9a-f]+ <[^>]*> 21c0 a000 sdc2 \$14,0\(zero\)
+[0-9a-f]+ <[^>]*> 21e0 a000 sdc2 \$15,0\(zero\)
+[0-9a-f]+ <[^>]*> 2200 a000 sdc2 \$16,0\(zero\)
+[0-9a-f]+ <[^>]*> 2220 a000 sdc2 \$17,0\(zero\)
+[0-9a-f]+ <[^>]*> 2240 a000 sdc2 \$18,0\(zero\)
+[0-9a-f]+ <[^>]*> 2260 a000 sdc2 \$19,0\(zero\)
+[0-9a-f]+ <[^>]*> 2280 a000 sdc2 \$20,0\(zero\)
+[0-9a-f]+ <[^>]*> 22a0 a000 sdc2 \$21,0\(zero\)
+[0-9a-f]+ <[^>]*> 22c0 a000 sdc2 \$22,0\(zero\)
+[0-9a-f]+ <[^>]*> 22e0 a000 sdc2 \$23,0\(zero\)
+[0-9a-f]+ <[^>]*> 2300 a000 sdc2 \$24,0\(zero\)
+[0-9a-f]+ <[^>]*> 2320 a000 sdc2 \$25,0\(zero\)
+[0-9a-f]+ <[^>]*> 2340 a000 sdc2 \$26,0\(zero\)
+[0-9a-f]+ <[^>]*> 2360 a000 sdc2 \$27,0\(zero\)
+[0-9a-f]+ <[^>]*> 2380 a000 sdc2 \$28,0\(zero\)
+[0-9a-f]+ <[^>]*> 23a0 a000 sdc2 \$29,0\(zero\)
+[0-9a-f]+ <[^>]*> 23c0 a000 sdc2 \$30,0\(zero\)
+[0-9a-f]+ <[^>]*> 23e0 a000 sdc2 \$31,0\(zero\)
+ \.\.\.
Index: binutils-gdb/gas/testsuite/gas/mips/micromips@cp2m.d
===================================================================
--- /dev/null
+++ binutils-gdb/gas/testsuite/gas/mips/micromips@cp2m.d
@@ -0,0 +1,73 @@
+#objdump: -d --prefix-addresses --show-raw-insn
+#name: MIPS CP2 memory access instructions
+#as: -32
+#source: cp2m.s
+
+.*: +file format .*mips.*
+
+Disassembly of section \.text:
+[0-9a-f]+ <[^>]*> 2000 0000 lwc2 \$0,0\(zero\)
+[0-9a-f]+ <[^>]*> 2020 0000 lwc2 \$1,0\(zero\)
+[0-9a-f]+ <[^>]*> 2040 0000 lwc2 \$2,0\(zero\)
+[0-9a-f]+ <[^>]*> 2060 0000 lwc2 \$3,0\(zero\)
+[0-9a-f]+ <[^>]*> 2080 0000 lwc2 \$4,0\(zero\)
+[0-9a-f]+ <[^>]*> 20a0 0000 lwc2 \$5,0\(zero\)
+[0-9a-f]+ <[^>]*> 20c0 0000 lwc2 \$6,0\(zero\)
+[0-9a-f]+ <[^>]*> 20e0 0000 lwc2 \$7,0\(zero\)
+[0-9a-f]+ <[^>]*> 2100 0000 lwc2 \$8,0\(zero\)
+[0-9a-f]+ <[^>]*> 2120 0000 lwc2 \$9,0\(zero\)
+[0-9a-f]+ <[^>]*> 2140 0000 lwc2 \$10,0\(zero\)
+[0-9a-f]+ <[^>]*> 2160 0000 lwc2 \$11,0\(zero\)
+[0-9a-f]+ <[^>]*> 2180 0000 lwc2 \$12,0\(zero\)
+[0-9a-f]+ <[^>]*> 21a0 0000 lwc2 \$13,0\(zero\)
+[0-9a-f]+ <[^>]*> 21c0 0000 lwc2 \$14,0\(zero\)
+[0-9a-f]+ <[^>]*> 21e0 0000 lwc2 \$15,0\(zero\)
+[0-9a-f]+ <[^>]*> 2200 0000 lwc2 \$16,0\(zero\)
+[0-9a-f]+ <[^>]*> 2220 0000 lwc2 \$17,0\(zero\)
+[0-9a-f]+ <[^>]*> 2240 0000 lwc2 \$18,0\(zero\)
+[0-9a-f]+ <[^>]*> 2260 0000 lwc2 \$19,0\(zero\)
+[0-9a-f]+ <[^>]*> 2280 0000 lwc2 \$20,0\(zero\)
+[0-9a-f]+ <[^>]*> 22a0 0000 lwc2 \$21,0\(zero\)
+[0-9a-f]+ <[^>]*> 22c0 0000 lwc2 \$22,0\(zero\)
+[0-9a-f]+ <[^>]*> 22e0 0000 lwc2 \$23,0\(zero\)
+[0-9a-f]+ <[^>]*> 2300 0000 lwc2 \$24,0\(zero\)
+[0-9a-f]+ <[^>]*> 2320 0000 lwc2 \$25,0\(zero\)
+[0-9a-f]+ <[^>]*> 2340 0000 lwc2 \$26,0\(zero\)
+[0-9a-f]+ <[^>]*> 2360 0000 lwc2 \$27,0\(zero\)
+[0-9a-f]+ <[^>]*> 2380 0000 lwc2 \$28,0\(zero\)
+[0-9a-f]+ <[^>]*> 23a0 0000 lwc2 \$29,0\(zero\)
+[0-9a-f]+ <[^>]*> 23c0 0000 lwc2 \$30,0\(zero\)
+[0-9a-f]+ <[^>]*> 23e0 0000 lwc2 \$31,0\(zero\)
+[0-9a-f]+ <[^>]*> 2000 8000 swc2 \$0,0\(zero\)
+[0-9a-f]+ <[^>]*> 2020 8000 swc2 \$1,0\(zero\)
+[0-9a-f]+ <[^>]*> 2040 8000 swc2 \$2,0\(zero\)
+[0-9a-f]+ <[^>]*> 2060 8000 swc2 \$3,0\(zero\)
+[0-9a-f]+ <[^>]*> 2080 8000 swc2 \$4,0\(zero\)
+[0-9a-f]+ <[^>]*> 20a0 8000 swc2 \$5,0\(zero\)
+[0-9a-f]+ <[^>]*> 20c0 8000 swc2 \$6,0\(zero\)
+[0-9a-f]+ <[^>]*> 20e0 8000 swc2 \$7,0\(zero\)
+[0-9a-f]+ <[^>]*> 2100 8000 swc2 \$8,0\(zero\)
+[0-9a-f]+ <[^>]*> 2120 8000 swc2 \$9,0\(zero\)
+[0-9a-f]+ <[^>]*> 2140 8000 swc2 \$10,0\(zero\)
+[0-9a-f]+ <[^>]*> 2160 8000 swc2 \$11,0\(zero\)
+[0-9a-f]+ <[^>]*> 2180 8000 swc2 \$12,0\(zero\)
+[0-9a-f]+ <[^>]*> 21a0 8000 swc2 \$13,0\(zero\)
+[0-9a-f]+ <[^>]*> 21c0 8000 swc2 \$14,0\(zero\)
+[0-9a-f]+ <[^>]*> 21e0 8000 swc2 \$15,0\(zero\)
+[0-9a-f]+ <[^>]*> 2200 8000 swc2 \$16,0\(zero\)
+[0-9a-f]+ <[^>]*> 2220 8000 swc2 \$17,0\(zero\)
+[0-9a-f]+ <[^>]*> 2240 8000 swc2 \$18,0\(zero\)
+[0-9a-f]+ <[^>]*> 2260 8000 swc2 \$19,0\(zero\)
+[0-9a-f]+ <[^>]*> 2280 8000 swc2 \$20,0\(zero\)
+[0-9a-f]+ <[^>]*> 22a0 8000 swc2 \$21,0\(zero\)
+[0-9a-f]+ <[^>]*> 22c0 8000 swc2 \$22,0\(zero\)
+[0-9a-f]+ <[^>]*> 22e0 8000 swc2 \$23,0\(zero\)
+[0-9a-f]+ <[^>]*> 2300 8000 swc2 \$24,0\(zero\)
+[0-9a-f]+ <[^>]*> 2320 8000 swc2 \$25,0\(zero\)
+[0-9a-f]+ <[^>]*> 2340 8000 swc2 \$26,0\(zero\)
+[0-9a-f]+ <[^>]*> 2360 8000 swc2 \$27,0\(zero\)
+[0-9a-f]+ <[^>]*> 2380 8000 swc2 \$28,0\(zero\)
+[0-9a-f]+ <[^>]*> 23a0 8000 swc2 \$29,0\(zero\)
+[0-9a-f]+ <[^>]*> 23c0 8000 swc2 \$30,0\(zero\)
+[0-9a-f]+ <[^>]*> 23e0 8000 swc2 \$31,0\(zero\)
+ \.\.\.
Index: binutils-gdb/gas/testsuite/gas/mips/mips.exp
===================================================================
--- binutils-gdb.orig/gas/testsuite/gas/mips/mips.exp
+++ binutils-gdb/gas/testsuite/gas/mips/mips.exp
@@ -1333,6 +1333,11 @@ if { [istarget mips*-*-vxworks*] } {
run_dump_test "cp0sel-names-mips64r2"
run_dump_test "cp0sel-names-sb1"
+ run_dump_test_arches "cp0c" [mips_arch_list_matching mips1 \
+ !mips32 !micromips]
+ run_dump_test_arches "cp0m" [mips_arch_list_matching mips1 \
+ !mips2 !micromips]
+
run_dump_test "cp1-names-numeric"
run_dump_test "cp1-names-r3000"
run_dump_test "cp1-names-r4000" \
@@ -1345,6 +1350,22 @@ if { [istarget mips*-*-vxworks*] } {
run_dump_test "cp1-names-mips64r2"
run_dump_test "cp1-names-sb1"
+ run_dump_test_arches "cp2" [mips_arch_list_matching mips1 \
+ !vr5400 !r5900 !octeon]
+ run_dump_test_arches "cp2-64" [mips_arch_list_matching mips3 \
+ !vr5400 !r5900 !octeon]
+ run_dump_test_arches "cp2m" [mips_arch_list_matching mips1 \
+ !vr5400 !r5900 !octeon]
+ run_dump_test_arches "cp2d" [mips_arch_list_matching mips2 \
+ !vr5400 !r5900 !octeon]
+
+ run_dump_test_arches "cp3" [mips_arch_list_matching mips1 \
+ !mips3 !mips32r2 !micromips]
+ run_dump_test_arches "cp3m" [mips_arch_list_matching mips1 \
+ !mips3 !mips32 !micromips]
+ run_dump_test_arches "cp3d" [mips_arch_list_matching mips2 \
+ !mips3 !mips32 !micromips]
+
run_dump_test "hwr-names-numeric"
run_dump_test "hwr-names-mips32r2"
run_dump_test "hwr-names-mips64r2"
Index: binutils-gdb/gas/testsuite/gas/mips/mipsr6@cp2d.d
===================================================================
--- /dev/null
+++ binutils-gdb/gas/testsuite/gas/mips/mipsr6@cp2d.d
@@ -0,0 +1,73 @@
+#objdump: -d --prefix-addresses --show-raw-insn
+#name: MIPS CP2 doubleword memory access instructions
+#as: -32
+#source: cp2d\.s
+
+.*: +file format .*mips.*
+
+Disassembly of section \.text:
+[0-9a-f]+ <[^>]*> 49c00000 ldc2 \$0,0\(zero\)
+[0-9a-f]+ <[^>]*> 49c10000 ldc2 \$1,0\(zero\)
+[0-9a-f]+ <[^>]*> 49c20000 ldc2 \$2,0\(zero\)
+[0-9a-f]+ <[^>]*> 49c30000 ldc2 \$3,0\(zero\)
+[0-9a-f]+ <[^>]*> 49c40000 ldc2 \$4,0\(zero\)
+[0-9a-f]+ <[^>]*> 49c50000 ldc2 \$5,0\(zero\)
+[0-9a-f]+ <[^>]*> 49c60000 ldc2 \$6,0\(zero\)
+[0-9a-f]+ <[^>]*> 49c70000 ldc2 \$7,0\(zero\)
+[0-9a-f]+ <[^>]*> 49c80000 ldc2 \$8,0\(zero\)
+[0-9a-f]+ <[^>]*> 49c90000 ldc2 \$9,0\(zero\)
+[0-9a-f]+ <[^>]*> 49ca0000 ldc2 \$10,0\(zero\)
+[0-9a-f]+ <[^>]*> 49cb0000 ldc2 \$11,0\(zero\)
+[0-9a-f]+ <[^>]*> 49cc0000 ldc2 \$12,0\(zero\)
+[0-9a-f]+ <[^>]*> 49cd0000 ldc2 \$13,0\(zero\)
+[0-9a-f]+ <[^>]*> 49ce0000 ldc2 \$14,0\(zero\)
+[0-9a-f]+ <[^>]*> 49cf0000 ldc2 \$15,0\(zero\)
+[0-9a-f]+ <[^>]*> 49d00000 ldc2 \$16,0\(zero\)
+[0-9a-f]+ <[^>]*> 49d10000 ldc2 \$17,0\(zero\)
+[0-9a-f]+ <[^>]*> 49d20000 ldc2 \$18,0\(zero\)
+[0-9a-f]+ <[^>]*> 49d30000 ldc2 \$19,0\(zero\)
+[0-9a-f]+ <[^>]*> 49d40000 ldc2 \$20,0\(zero\)
+[0-9a-f]+ <[^>]*> 49d50000 ldc2 \$21,0\(zero\)
+[0-9a-f]+ <[^>]*> 49d60000 ldc2 \$22,0\(zero\)
+[0-9a-f]+ <[^>]*> 49d70000 ldc2 \$23,0\(zero\)
+[0-9a-f]+ <[^>]*> 49d80000 ldc2 \$24,0\(zero\)
+[0-9a-f]+ <[^>]*> 49d90000 ldc2 \$25,0\(zero\)
+[0-9a-f]+ <[^>]*> 49da0000 ldc2 \$26,0\(zero\)
+[0-9a-f]+ <[^>]*> 49db0000 ldc2 \$27,0\(zero\)
+[0-9a-f]+ <[^>]*> 49dc0000 ldc2 \$28,0\(zero\)
+[0-9a-f]+ <[^>]*> 49dd0000 ldc2 \$29,0\(zero\)
+[0-9a-f]+ <[^>]*> 49de0000 ldc2 \$30,0\(zero\)
+[0-9a-f]+ <[^>]*> 49df0000 ldc2 \$31,0\(zero\)
+[0-9a-f]+ <[^>]*> 49e00000 sdc2 \$0,0\(zero\)
+[0-9a-f]+ <[^>]*> 49e10000 sdc2 \$1,0\(zero\)
+[0-9a-f]+ <[^>]*> 49e20000 sdc2 \$2,0\(zero\)
+[0-9a-f]+ <[^>]*> 49e30000 sdc2 \$3,0\(zero\)
+[0-9a-f]+ <[^>]*> 49e40000 sdc2 \$4,0\(zero\)
+[0-9a-f]+ <[^>]*> 49e50000 sdc2 \$5,0\(zero\)
+[0-9a-f]+ <[^>]*> 49e60000 sdc2 \$6,0\(zero\)
+[0-9a-f]+ <[^>]*> 49e70000 sdc2 \$7,0\(zero\)
+[0-9a-f]+ <[^>]*> 49e80000 sdc2 \$8,0\(zero\)
+[0-9a-f]+ <[^>]*> 49e90000 sdc2 \$9,0\(zero\)
+[0-9a-f]+ <[^>]*> 49ea0000 sdc2 \$10,0\(zero\)
+[0-9a-f]+ <[^>]*> 49eb0000 sdc2 \$11,0\(zero\)
+[0-9a-f]+ <[^>]*> 49ec0000 sdc2 \$12,0\(zero\)
+[0-9a-f]+ <[^>]*> 49ed0000 sdc2 \$13,0\(zero\)
+[0-9a-f]+ <[^>]*> 49ee0000 sdc2 \$14,0\(zero\)
+[0-9a-f]+ <[^>]*> 49ef0000 sdc2 \$15,0\(zero\)
+[0-9a-f]+ <[^>]*> 49f00000 sdc2 \$16,0\(zero\)
+[0-9a-f]+ <[^>]*> 49f10000 sdc2 \$17,0\(zero\)
+[0-9a-f]+ <[^>]*> 49f20000 sdc2 \$18,0\(zero\)
+[0-9a-f]+ <[^>]*> 49f30000 sdc2 \$19,0\(zero\)
+[0-9a-f]+ <[^>]*> 49f40000 sdc2 \$20,0\(zero\)
+[0-9a-f]+ <[^>]*> 49f50000 sdc2 \$21,0\(zero\)
+[0-9a-f]+ <[^>]*> 49f60000 sdc2 \$22,0\(zero\)
+[0-9a-f]+ <[^>]*> 49f70000 sdc2 \$23,0\(zero\)
+[0-9a-f]+ <[^>]*> 49f80000 sdc2 \$24,0\(zero\)
+[0-9a-f]+ <[^>]*> 49f90000 sdc2 \$25,0\(zero\)
+[0-9a-f]+ <[^>]*> 49fa0000 sdc2 \$26,0\(zero\)
+[0-9a-f]+ <[^>]*> 49fb0000 sdc2 \$27,0\(zero\)
+[0-9a-f]+ <[^>]*> 49fc0000 sdc2 \$28,0\(zero\)
+[0-9a-f]+ <[^>]*> 49fd0000 sdc2 \$29,0\(zero\)
+[0-9a-f]+ <[^>]*> 49fe0000 sdc2 \$30,0\(zero\)
+[0-9a-f]+ <[^>]*> 49ff0000 sdc2 \$31,0\(zero\)
+ \.\.\.
Index: binutils-gdb/gas/testsuite/gas/mips/mipsr6@cp2m.d
===================================================================
--- /dev/null
+++ binutils-gdb/gas/testsuite/gas/mips/mipsr6@cp2m.d
@@ -0,0 +1,73 @@
+#objdump: -d --prefix-addresses --show-raw-insn
+#name: MIPS CP2 memory access instructions
+#as: -32
+#source: cp2m.s
+
+.*: +file format .*mips.*
+
+Disassembly of section \.text:
+[0-9a-f]+ <[^>]*> 49400000 lwc2 \$0,0\(zero\)
+[0-9a-f]+ <[^>]*> 49410000 lwc2 \$1,0\(zero\)
+[0-9a-f]+ <[^>]*> 49420000 lwc2 \$2,0\(zero\)
+[0-9a-f]+ <[^>]*> 49430000 lwc2 \$3,0\(zero\)
+[0-9a-f]+ <[^>]*> 49440000 lwc2 \$4,0\(zero\)
+[0-9a-f]+ <[^>]*> 49450000 lwc2 \$5,0\(zero\)
+[0-9a-f]+ <[^>]*> 49460000 lwc2 \$6,0\(zero\)
+[0-9a-f]+ <[^>]*> 49470000 lwc2 \$7,0\(zero\)
+[0-9a-f]+ <[^>]*> 49480000 lwc2 \$8,0\(zero\)
+[0-9a-f]+ <[^>]*> 49490000 lwc2 \$9,0\(zero\)
+[0-9a-f]+ <[^>]*> 494a0000 lwc2 \$10,0\(zero\)
+[0-9a-f]+ <[^>]*> 494b0000 lwc2 \$11,0\(zero\)
+[0-9a-f]+ <[^>]*> 494c0000 lwc2 \$12,0\(zero\)
+[0-9a-f]+ <[^>]*> 494d0000 lwc2 \$13,0\(zero\)
+[0-9a-f]+ <[^>]*> 494e0000 lwc2 \$14,0\(zero\)
+[0-9a-f]+ <[^>]*> 494f0000 lwc2 \$15,0\(zero\)
+[0-9a-f]+ <[^>]*> 49500000 lwc2 \$16,0\(zero\)
+[0-9a-f]+ <[^>]*> 49510000 lwc2 \$17,0\(zero\)
+[0-9a-f]+ <[^>]*> 49520000 lwc2 \$18,0\(zero\)
+[0-9a-f]+ <[^>]*> 49530000 lwc2 \$19,0\(zero\)
+[0-9a-f]+ <[^>]*> 49540000 lwc2 \$20,0\(zero\)
+[0-9a-f]+ <[^>]*> 49550000 lwc2 \$21,0\(zero\)
+[0-9a-f]+ <[^>]*> 49560000 lwc2 \$22,0\(zero\)
+[0-9a-f]+ <[^>]*> 49570000 lwc2 \$23,0\(zero\)
+[0-9a-f]+ <[^>]*> 49580000 lwc2 \$24,0\(zero\)
+[0-9a-f]+ <[^>]*> 49590000 lwc2 \$25,0\(zero\)
+[0-9a-f]+ <[^>]*> 495a0000 lwc2 \$26,0\(zero\)
+[0-9a-f]+ <[^>]*> 495b0000 lwc2 \$27,0\(zero\)
+[0-9a-f]+ <[^>]*> 495c0000 lwc2 \$28,0\(zero\)
+[0-9a-f]+ <[^>]*> 495d0000 lwc2 \$29,0\(zero\)
+[0-9a-f]+ <[^>]*> 495e0000 lwc2 \$30,0\(zero\)
+[0-9a-f]+ <[^>]*> 495f0000 lwc2 \$31,0\(zero\)
+[0-9a-f]+ <[^>]*> 49600000 swc2 \$0,0\(zero\)
+[0-9a-f]+ <[^>]*> 49610000 swc2 \$1,0\(zero\)
+[0-9a-f]+ <[^>]*> 49620000 swc2 \$2,0\(zero\)
+[0-9a-f]+ <[^>]*> 49630000 swc2 \$3,0\(zero\)
+[0-9a-f]+ <[^>]*> 49640000 swc2 \$4,0\(zero\)
+[0-9a-f]+ <[^>]*> 49650000 swc2 \$5,0\(zero\)
+[0-9a-f]+ <[^>]*> 49660000 swc2 \$6,0\(zero\)
+[0-9a-f]+ <[^>]*> 49670000 swc2 \$7,0\(zero\)
+[0-9a-f]+ <[^>]*> 49680000 swc2 \$8,0\(zero\)
+[0-9a-f]+ <[^>]*> 49690000 swc2 \$9,0\(zero\)
+[0-9a-f]+ <[^>]*> 496a0000 swc2 \$10,0\(zero\)
+[0-9a-f]+ <[^>]*> 496b0000 swc2 \$11,0\(zero\)
+[0-9a-f]+ <[^>]*> 496c0000 swc2 \$12,0\(zero\)
+[0-9a-f]+ <[^>]*> 496d0000 swc2 \$13,0\(zero\)
+[0-9a-f]+ <[^>]*> 496e0000 swc2 \$14,0\(zero\)
+[0-9a-f]+ <[^>]*> 496f0000 swc2 \$15,0\(zero\)
+[0-9a-f]+ <[^>]*> 49700000 swc2 \$16,0\(zero\)
+[0-9a-f]+ <[^>]*> 49710000 swc2 \$17,0\(zero\)
+[0-9a-f]+ <[^>]*> 49720000 swc2 \$18,0\(zero\)
+[0-9a-f]+ <[^>]*> 49730000 swc2 \$19,0\(zero\)
+[0-9a-f]+ <[^>]*> 49740000 swc2 \$20,0\(zero\)
+[0-9a-f]+ <[^>]*> 49750000 swc2 \$21,0\(zero\)
+[0-9a-f]+ <[^>]*> 49760000 swc2 \$22,0\(zero\)
+[0-9a-f]+ <[^>]*> 49770000 swc2 \$23,0\(zero\)
+[0-9a-f]+ <[^>]*> 49780000 swc2 \$24,0\(zero\)
+[0-9a-f]+ <[^>]*> 49790000 swc2 \$25,0\(zero\)
+[0-9a-f]+ <[^>]*> 497a0000 swc2 \$26,0\(zero\)
+[0-9a-f]+ <[^>]*> 497b0000 swc2 \$27,0\(zero\)
+[0-9a-f]+ <[^>]*> 497c0000 swc2 \$28,0\(zero\)
+[0-9a-f]+ <[^>]*> 497d0000 swc2 \$29,0\(zero\)
+[0-9a-f]+ <[^>]*> 497e0000 swc2 \$30,0\(zero\)
+[0-9a-f]+ <[^>]*> 497f0000 swc2 \$31,0\(zero\)
+ \.\.\.
Index: binutils-gdb/gas/testsuite/gas/mips/r3900@cp0m.d
===================================================================
--- /dev/null
+++ binutils-gdb/gas/testsuite/gas/mips/r3900@cp0m.d
@@ -0,0 +1,73 @@
+#objdump: -d --prefix-addresses --show-raw-insn
+#name: MIPS CP0 memory access instructions
+#as: -32
+#source: cp0m.s
+
+.*: +file format .*mips.*
+
+Disassembly of section \.text:
+[0-9a-f]+ <[^>]*> c0000000 lwc0 \$0,0\(zero\)
+[0-9a-f]+ <[^>]*> c0010000 lwc0 \$1,0\(zero\)
+[0-9a-f]+ <[^>]*> c0020000 lwc0 \$2,0\(zero\)
+[0-9a-f]+ <[^>]*> c0030000 lwc0 c0_config,0\(zero\)
+[0-9a-f]+ <[^>]*> c0040000 lwc0 \$4,0\(zero\)
+[0-9a-f]+ <[^>]*> c0050000 lwc0 \$5,0\(zero\)
+[0-9a-f]+ <[^>]*> c0060000 lwc0 \$6,0\(zero\)
+[0-9a-f]+ <[^>]*> c0070000 lwc0 c0_cache,0\(zero\)
+[0-9a-f]+ <[^>]*> c0080000 lwc0 c0_badvaddr,0\(zero\)
+[0-9a-f]+ <[^>]*> c0090000 lwc0 \$9,0\(zero\)
+[0-9a-f]+ <[^>]*> c00a0000 lwc0 \$10,0\(zero\)
+[0-9a-f]+ <[^>]*> c00b0000 lwc0 \$11,0\(zero\)
+[0-9a-f]+ <[^>]*> c00c0000 lwc0 c0_sr,0\(zero\)
+[0-9a-f]+ <[^>]*> c00d0000 lwc0 c0_cause,0\(zero\)
+[0-9a-f]+ <[^>]*> c00e0000 lwc0 c0_epc,0\(zero\)
+[0-9a-f]+ <[^>]*> c00f0000 lwc0 c0_prid,0\(zero\)
+[0-9a-f]+ <[^>]*> c0100000 lwc0 c0_debug,0\(zero\)
+[0-9a-f]+ <[^>]*> c0110000 lwc0 c0_depc,0\(zero\)
+[0-9a-f]+ <[^>]*> c0120000 lwc0 \$18,0\(zero\)
+[0-9a-f]+ <[^>]*> c0130000 lwc0 \$19,0\(zero\)
+[0-9a-f]+ <[^>]*> c0140000 lwc0 \$20,0\(zero\)
+[0-9a-f]+ <[^>]*> c0150000 lwc0 \$21,0\(zero\)
+[0-9a-f]+ <[^>]*> c0160000 lwc0 \$22,0\(zero\)
+[0-9a-f]+ <[^>]*> c0170000 lwc0 \$23,0\(zero\)
+[0-9a-f]+ <[^>]*> c0180000 lwc0 \$24,0\(zero\)
+[0-9a-f]+ <[^>]*> c0190000 lwc0 \$25,0\(zero\)
+[0-9a-f]+ <[^>]*> c01a0000 lwc0 \$26,0\(zero\)
+[0-9a-f]+ <[^>]*> c01b0000 lwc0 \$27,0\(zero\)
+[0-9a-f]+ <[^>]*> c01c0000 lwc0 \$28,0\(zero\)
+[0-9a-f]+ <[^>]*> c01d0000 lwc0 \$29,0\(zero\)
+[0-9a-f]+ <[^>]*> c01e0000 lwc0 \$30,0\(zero\)
+[0-9a-f]+ <[^>]*> c01f0000 lwc0 \$31,0\(zero\)
+[0-9a-f]+ <[^>]*> e0000000 swc0 \$0,0\(zero\)
+[0-9a-f]+ <[^>]*> e0010000 swc0 \$1,0\(zero\)
+[0-9a-f]+ <[^>]*> e0020000 swc0 \$2,0\(zero\)
+[0-9a-f]+ <[^>]*> e0030000 swc0 c0_config,0\(zero\)
+[0-9a-f]+ <[^>]*> e0040000 swc0 \$4,0\(zero\)
+[0-9a-f]+ <[^>]*> e0050000 swc0 \$5,0\(zero\)
+[0-9a-f]+ <[^>]*> e0060000 swc0 \$6,0\(zero\)
+[0-9a-f]+ <[^>]*> e0070000 swc0 c0_cache,0\(zero\)
+[0-9a-f]+ <[^>]*> e0080000 swc0 c0_badvaddr,0\(zero\)
+[0-9a-f]+ <[^>]*> e0090000 swc0 \$9,0\(zero\)
+[0-9a-f]+ <[^>]*> e00a0000 swc0 \$10,0\(zero\)
+[0-9a-f]+ <[^>]*> e00b0000 swc0 \$11,0\(zero\)
+[0-9a-f]+ <[^>]*> e00c0000 swc0 c0_sr,0\(zero\)
+[0-9a-f]+ <[^>]*> e00d0000 swc0 c0_cause,0\(zero\)
+[0-9a-f]+ <[^>]*> e00e0000 swc0 c0_epc,0\(zero\)
+[0-9a-f]+ <[^>]*> e00f0000 swc0 c0_prid,0\(zero\)
+[0-9a-f]+ <[^>]*> e0100000 swc0 c0_debug,0\(zero\)
+[0-9a-f]+ <[^>]*> e0110000 swc0 c0_depc,0\(zero\)
+[0-9a-f]+ <[^>]*> e0120000 swc0 \$18,0\(zero\)
+[0-9a-f]+ <[^>]*> e0130000 swc0 \$19,0\(zero\)
+[0-9a-f]+ <[^>]*> e0140000 swc0 \$20,0\(zero\)
+[0-9a-f]+ <[^>]*> e0150000 swc0 \$21,0\(zero\)
+[0-9a-f]+ <[^>]*> e0160000 swc0 \$22,0\(zero\)
+[0-9a-f]+ <[^>]*> e0170000 swc0 \$23,0\(zero\)
+[0-9a-f]+ <[^>]*> e0180000 swc0 \$24,0\(zero\)
+[0-9a-f]+ <[^>]*> e0190000 swc0 \$25,0\(zero\)
+[0-9a-f]+ <[^>]*> e01a0000 swc0 \$26,0\(zero\)
+[0-9a-f]+ <[^>]*> e01b0000 swc0 \$27,0\(zero\)
+[0-9a-f]+ <[^>]*> e01c0000 swc0 \$28,0\(zero\)
+[0-9a-f]+ <[^>]*> e01d0000 swc0 \$29,0\(zero\)
+[0-9a-f]+ <[^>]*> e01e0000 swc0 \$30,0\(zero\)
+[0-9a-f]+ <[^>]*> e01f0000 swc0 \$31,0\(zero\)
+ \.\.\.
^ permalink raw reply [flat|nested] 19+ messages in thread
* [committed 08/18] MIPS/opcodes: Add legacy CP1 control register names
2021-05-29 1:36 [committed 00/18] MIPS coprocessor opcodes handling fixes Maciej W. Rozycki
` (6 preceding siblings ...)
2021-05-29 1:37 ` [committed 07/18] MIPS/GAS/testsuite: Add tests for coprocessor access instructions Maciej W. Rozycki
@ 2021-05-29 1:37 ` Maciej W. Rozycki
2021-05-29 1:37 ` [committed 09/18] MIPS/opcodes: Factor out ISA matching against flags Maciej W. Rozycki
` (9 subsequent siblings)
17 siblings, 0 replies; 19+ messages in thread
From: Maciej W. Rozycki @ 2021-05-29 1:37 UTC (permalink / raw)
To: binutils
The two CP1 control registers defined by legacy ISAs used to be referred
to by various names, such as FCR0, FCR31, FSR, however their documented
full names have always been the Implementation and Revision, and Control
and Status respectively, so the FIR and FCSR acronyms coming from modern
ISA revisions will be just as unambiguous while improving the clarity of
disassembly. Do not update the TX39 though as it did not have an FPU.
opcodes/
* mips-dis.c (mips_cp1_names_mips): New variable.
(mips_arch_choices): Use it rather than `mips_cp1_names_numeric'
for "r3000", "r4000", "r4010", "vr4100", "vr4111", "vr4120",
"r4300", "r4400", "r4600", "r4650", "r5000", "vr5400", "vr5500",
"r5900", "r6000", "rm7000", "rm9000", "r8000", "r10000",
"r12000", "r14000", "r16000", "mips5", "loongson2e", and
"loongson2f".
gas/
* testsuite/gas/mips/cp1-names-r3900.d: New test.
* testsuite/gas/mips/mips.exp: Run the new test.
* testsuite/gas/mips/branch-misc-3.d: Update disassembly
according to changes to opcodes.
* testsuite/gas/mips/cp1-names-r3000.d: Likewise.
* testsuite/gas/mips/cp1-names-r4000.d: Likewise.
* testsuite/gas/mips/relax-swap1-mips1.d: Likewise.
* testsuite/gas/mips/relax-swap1-mips2.d: Likewise.
* testsuite/gas/mips/trunc.d: Likewise.
---
gas/testsuite/gas/mips/branch-misc-3.d | 10 ++--
gas/testsuite/gas/mips/cp1-names-r3000.d | 8 +--
gas/testsuite/gas/mips/cp1-names-r3900.d | 5 ++
gas/testsuite/gas/mips/cp1-names-r4000.d | 8 +--
gas/testsuite/gas/mips/mips.exp | 1
gas/testsuite/gas/mips/relax-swap1-mips1.d | 8 +--
gas/testsuite/gas/mips/relax-swap1-mips2.d | 8 +--
gas/testsuite/gas/mips/trunc.d | 16 +++----
opcodes/mips-dis.c | 62 +++++++++++++++++------------
9 files changed, 72 insertions(+), 54 deletions(-)
binutils-mips-opcodes-cp1-names-mips.diff
Index: binutils-gdb/gas/testsuite/gas/mips/branch-misc-3.d
===================================================================
--- binutils-gdb.orig/gas/testsuite/gas/mips/branch-misc-3.d
+++ binutils-gdb/gas/testsuite/gas/mips/branch-misc-3.d
@@ -7,11 +7,11 @@
Disassembly .*:
0+00 <.*>:
-.* ctc1 a0,\$31
+.* ctc1 a0,c1_fcsr
.* b .*
.* nop
#
-.* ctc1 a0,\$31
+.* ctc1 a0,c1_fcsr
.* nop
.* nop
.* bc1t .*
@@ -26,13 +26,13 @@
.* bc1t .*
.* nop
#
-.* ctc1 a0,\$31
+.* ctc1 a0,c1_fcsr
.* addiu a1,a1,1
.* nop
.* bc1t .*
.* nop
#
-.* ctc1 a0,\$31
+.* ctc1 a0,c1_fcsr
.* addiu a1,a1,1
.* addiu a2,a2,1
.* bc1t .*
@@ -43,7 +43,7 @@
.* bc1t .*
.* nop
#
-.* ctc1 a0,\$31
+.* ctc1 a0,c1_fcsr
.* addiu a1,a1,1
.* addiu a2,a2,1
.* bc1t .*
Index: binutils-gdb/gas/testsuite/gas/mips/cp1-names-r3000.d
===================================================================
--- binutils-gdb.orig/gas/testsuite/gas/mips/cp1-names-r3000.d
+++ binutils-gdb/gas/testsuite/gas/mips/cp1-names-r3000.d
@@ -8,7 +8,7 @@
.*: +file format .*mips.*
Disassembly of section \.text:
-0+0000 <[^>]*> 44c00000 ctc1 \$0,\$0
+0+0000 <[^>]*> 44c00000 ctc1 \$0,c1_fir
0+0004 <[^>]*> 44c00800 ctc1 \$0,\$1
0+0008 <[^>]*> 44c01000 ctc1 \$0,\$2
0+000c <[^>]*> 44c01800 ctc1 \$0,\$3
@@ -39,8 +39,8 @@
0+0070 <[^>]*> 44c0e000 ctc1 \$0,\$28
0+0074 <[^>]*> 44c0e800 ctc1 \$0,\$29
0+0078 <[^>]*> 44c0f000 ctc1 \$0,\$30
-0+007c <[^>]*> 44c0f800 ctc1 \$0,\$31
-0+0080 <[^>]*> 44400000 cfc1 \$0,\$0
+0+007c <[^>]*> 44c0f800 ctc1 \$0,c1_fcsr
+0+0080 <[^>]*> 44400000 cfc1 \$0,c1_fir
0+0084 <[^>]*> 44400800 cfc1 \$0,\$1
0+0088 <[^>]*> 44401000 cfc1 \$0,\$2
0+008c <[^>]*> 44401800 cfc1 \$0,\$3
@@ -71,5 +71,5 @@
0+00f0 <[^>]*> 4440e000 cfc1 \$0,\$28
0+00f4 <[^>]*> 4440e800 cfc1 \$0,\$29
0+00f8 <[^>]*> 4440f000 cfc1 \$0,\$30
-0+00fc <[^>]*> 4440f800 cfc1 \$0,\$31
+0+00fc <[^>]*> 4440f800 cfc1 \$0,c1_fcsr
\.\.\.
Index: binutils-gdb/gas/testsuite/gas/mips/cp1-names-r3900.d
===================================================================
--- /dev/null
+++ binutils-gdb/gas/testsuite/gas/mips/cp1-names-r3900.d
@@ -0,0 +1,5 @@
+#objdump: -dr --prefix-addresses --show-raw-insn -M gpr-names=numeric,cp1-names=r3900
+#name: MIPS CP1 register disassembly (r3900)
+#as: -32 -march=r3900
+#source: cp1-names.s
+#dump: cp1-names-numeric.d
Index: binutils-gdb/gas/testsuite/gas/mips/cp1-names-r4000.d
===================================================================
--- binutils-gdb.orig/gas/testsuite/gas/mips/cp1-names-r4000.d
+++ binutils-gdb/gas/testsuite/gas/mips/cp1-names-r4000.d
@@ -8,7 +8,7 @@
.*: +file format .*mips.*
Disassembly of section \.text:
-0+0000 <[^>]*> 44c00000 ctc1 \$0,\$0
+0+0000 <[^>]*> 44c00000 ctc1 \$0,c1_fir
0+0004 <[^>]*> 44c00800 ctc1 \$0,\$1
0+0008 <[^>]*> 44c01000 ctc1 \$0,\$2
0+000c <[^>]*> 44c01800 ctc1 \$0,\$3
@@ -39,8 +39,8 @@
0+0070 <[^>]*> 44c0e000 ctc1 \$0,\$28
0+0074 <[^>]*> 44c0e800 ctc1 \$0,\$29
0+0078 <[^>]*> 44c0f000 ctc1 \$0,\$30
-0+007c <[^>]*> 44c0f800 ctc1 \$0,\$31
-0+0080 <[^>]*> 44400000 cfc1 \$0,\$0
+0+007c <[^>]*> 44c0f800 ctc1 \$0,c1_fcsr
+0+0080 <[^>]*> 44400000 cfc1 \$0,c1_fir
0+0084 <[^>]*> 44400800 cfc1 \$0,\$1
0+0088 <[^>]*> 44401000 cfc1 \$0,\$2
0+008c <[^>]*> 44401800 cfc1 \$0,\$3
@@ -71,5 +71,5 @@
0+00f0 <[^>]*> 4440e000 cfc1 \$0,\$28
0+00f4 <[^>]*> 4440e800 cfc1 \$0,\$29
0+00f8 <[^>]*> 4440f000 cfc1 \$0,\$30
-0+00fc <[^>]*> 4440f800 cfc1 \$0,\$31
+0+00fc <[^>]*> 4440f800 cfc1 \$0,c1_fcsr
\.\.\.
Index: binutils-gdb/gas/testsuite/gas/mips/mips.exp
===================================================================
--- binutils-gdb.orig/gas/testsuite/gas/mips/mips.exp
+++ binutils-gdb/gas/testsuite/gas/mips/mips.exp
@@ -1340,6 +1340,7 @@ if { [istarget mips*-*-vxworks*] } {
run_dump_test "cp1-names-numeric"
run_dump_test "cp1-names-r3000"
+ run_dump_test "cp1-names-r3900"
run_dump_test "cp1-names-r4000" \
{ { {name} {(r4000)} } { {objdump} {-M cp0-names=r4000} } }
run_dump_test "cp1-names-r4000" \
Index: binutils-gdb/gas/testsuite/gas/mips/relax-swap1-mips1.d
===================================================================
--- binutils-gdb.orig/gas/testsuite/gas/mips/relax-swap1-mips1.d
+++ binutils-gdb/gas/testsuite/gas/mips/relax-swap1-mips1.d
@@ -240,10 +240,10 @@
[ ]*2f0: R_MIPS_LO16 \.text
0+02f4 <[^>]*> jr at
0+02f8 <[^>]*> nop
-0+02fc <[^>]*> cfc1 v0,\$31
+0+02fc <[^>]*> cfc1 v0,c1_fcsr
0+0300 <[^>]*> b 00000000 <foo>
0+0304 <[^>]*> nop
-0+0308 <[^>]*> cfc1 v0,\$31
+0+0308 <[^>]*> cfc1 v0,c1_fcsr
0+030c <[^>]*> lw at,2\(gp\)
[ ]*30c: R_MIPS_GOT16 \.text
0+0310 <[^>]*> nop
@@ -251,10 +251,10 @@
[ ]*314: R_MIPS_LO16 \.text
0+0318 <[^>]*> jr at
0+031c <[^>]*> nop
-0+0320 <[^>]*> ctc1 v0,\$31
+0+0320 <[^>]*> ctc1 v0,c1_fcsr
0+0324 <[^>]*> b 00000000 <foo>
0+0328 <[^>]*> nop
-0+032c <[^>]*> ctc1 v0,\$31
+0+032c <[^>]*> ctc1 v0,c1_fcsr
0+0330 <[^>]*> lw at,2\(gp\)
[ ]*330: R_MIPS_GOT16 \.text
0+0334 <[^>]*> nop
Index: binutils-gdb/gas/testsuite/gas/mips/relax-swap1-mips2.d
===================================================================
--- binutils-gdb.orig/gas/testsuite/gas/mips/relax-swap1-mips2.d
+++ binutils-gdb/gas/testsuite/gas/mips/relax-swap1-mips2.d
@@ -211,20 +211,20 @@
[ ]*27c: R_MIPS_LO16 \.text
0+0280 <[^>]*> jr at
0+0284 <[^>]*> lwc1 \$f0,0\(a0\)
-0+0288 <[^>]*> cfc1 v0,\$31
+0+0288 <[^>]*> cfc1 v0,c1_fcsr
0+028c <[^>]*> b 00000000 <foo>
0+0290 <[^>]*> nop
-0+0294 <[^>]*> cfc1 v0,\$31
+0+0294 <[^>]*> cfc1 v0,c1_fcsr
0+0298 <[^>]*> lw at,2\(gp\)
[ ]*298: R_MIPS_GOT16 \.text
0+029c <[^>]*> addiu at,at,860
[ ]*29c: R_MIPS_LO16 \.text
0+02a0 <[^>]*> jr at
0+02a4 <[^>]*> nop
-0+02a8 <[^>]*> ctc1 v0,\$31
+0+02a8 <[^>]*> ctc1 v0,c1_fcsr
0+02ac <[^>]*> b 00000000 <foo>
0+02b0 <[^>]*> nop
-0+02b4 <[^>]*> ctc1 v0,\$31
+0+02b4 <[^>]*> ctc1 v0,c1_fcsr
0+02b8 <[^>]*> lw at,2\(gp\)
[ ]*2b8: R_MIPS_GOT16 \.text
0+02bc <[^>]*> addiu at,at,860
Index: binutils-gdb/gas/testsuite/gas/mips/trunc.d
===================================================================
--- binutils-gdb.orig/gas/testsuite/gas/mips/trunc.d
+++ binutils-gdb/gas/testsuite/gas/mips/trunc.d
@@ -7,25 +7,25 @@
.*: +file format .*mips.*
Disassembly of section .text:
-0+0000 <[^>]*> cfc1 a0,\$31
-0+0004 <[^>]*> cfc1 a0,\$31
+0+0000 <[^>]*> cfc1 a0,c1_fcsr
+0+0004 <[^>]*> cfc1 a0,c1_fcsr
0+0008 <[^>]*> nop
0+000c <[^>]*> ori at,a0,0x3
0+0010 <[^>]*> xori at,at,0x2
-0+0014 <[^>]*> ctc1 at,\$31
+0+0014 <[^>]*> ctc1 at,c1_fcsr
0+0018 <[^>]*> nop
0+001c <[^>]*> cvt.w.d \$f4,\$f6
-0+0020 <[^>]*> ctc1 a0,\$31
+0+0020 <[^>]*> ctc1 a0,c1_fcsr
0+0024 <[^>]*> nop
-0+0028 <[^>]*> cfc1 a0,\$31
-0+002c <[^>]*> cfc1 a0,\$31
+0+0028 <[^>]*> cfc1 a0,c1_fcsr
+0+002c <[^>]*> cfc1 a0,c1_fcsr
0+0030 <[^>]*> nop
0+0034 <[^>]*> ori at,a0,0x3
0+0038 <[^>]*> xori at,at,0x2
-0+003c <[^>]*> ctc1 at,\$31
+0+003c <[^>]*> ctc1 at,c1_fcsr
0+0040 <[^>]*> nop
0+0044 <[^>]*> cvt.w.s \$f4,\$f6
-0+0048 <[^>]*> ctc1 a0,\$31
+0+0048 <[^>]*> ctc1 a0,c1_fcsr
0+004c <[^>]*> nop
0+0050 <[^>]*> nop
#pass
Index: binutils-gdb/opcodes/mips-dis.c
===================================================================
--- binutils-gdb.orig/opcodes/mips-dis.c
+++ binutils-gdb/opcodes/mips-dis.c
@@ -182,6 +182,18 @@ static const char * const mips_cp0_names
"c0_taglo", "c0_taghi", "c0_errorepc", "c0_desave",
};
+static const char * const mips_cp1_names_mips[32] =
+{
+ "c1_fir", "$1", "$2", "$3",
+ "$4", "$5", "$6", "$7",
+ "$8", "$9", "$10", "$11",
+ "$12", "$13", "$14", "$15",
+ "$16", "$17", "$18", "$19",
+ "$20", "$21", "$22", "$23",
+ "$24", "$25", "$26", "$27",
+ "$28", "$29", "$30", "c1_fcsr"
+};
+
static const char * const mips_cp1_names_mips3264[32] =
{
"c1_fir", "c1_ufr", "$2", "$3",
@@ -466,76 +478,76 @@ const struct mips_arch_choice mips_arch_
mips_hwr_names_numeric },
{ "r3000", 1, bfd_mach_mips3000, CPU_R3000, ISA_MIPS1, 0,
- mips_cp0_names_r3000, NULL, 0, mips_cp1_names_numeric,
+ mips_cp0_names_r3000, NULL, 0, mips_cp1_names_mips,
mips_hwr_names_numeric },
{ "r3900", 1, bfd_mach_mips3900, CPU_R3900, ISA_MIPS1, 0,
mips_cp0_names_r3900, NULL, 0, mips_cp1_names_numeric,
mips_hwr_names_numeric },
{ "r4000", 1, bfd_mach_mips4000, CPU_R4000, ISA_MIPS3, 0,
- mips_cp0_names_r4000, NULL, 0, mips_cp1_names_numeric,
+ mips_cp0_names_r4000, NULL, 0, mips_cp1_names_mips,
mips_hwr_names_numeric },
{ "r4010", 1, bfd_mach_mips4010, CPU_R4010, ISA_MIPS2, 0,
- mips_cp0_names_numeric, NULL, 0, mips_cp1_names_numeric,
+ mips_cp0_names_numeric, NULL, 0, mips_cp1_names_mips,
mips_hwr_names_numeric },
{ "vr4100", 1, bfd_mach_mips4100, CPU_VR4100, ISA_MIPS3, 0,
- mips_cp0_names_numeric, NULL, 0, mips_cp1_names_numeric,
+ mips_cp0_names_numeric, NULL, 0, mips_cp1_names_mips,
mips_hwr_names_numeric },
{ "vr4111", 1, bfd_mach_mips4111, CPU_R4111, ISA_MIPS3, 0,
- mips_cp0_names_numeric, NULL, 0, mips_cp1_names_numeric,
+ mips_cp0_names_numeric, NULL, 0, mips_cp1_names_mips,
mips_hwr_names_numeric },
{ "vr4120", 1, bfd_mach_mips4120, CPU_VR4120, ISA_MIPS3, 0,
- mips_cp0_names_numeric, NULL, 0, mips_cp1_names_numeric,
+ mips_cp0_names_numeric, NULL, 0, mips_cp1_names_mips,
mips_hwr_names_numeric },
{ "r4300", 1, bfd_mach_mips4300, CPU_R4300, ISA_MIPS3, 0,
- mips_cp0_names_numeric, NULL, 0, mips_cp1_names_numeric,
+ mips_cp0_names_numeric, NULL, 0, mips_cp1_names_mips,
mips_hwr_names_numeric },
{ "r4400", 1, bfd_mach_mips4400, CPU_R4400, ISA_MIPS3, 0,
- mips_cp0_names_r4000, NULL, 0, mips_cp1_names_numeric,
+ mips_cp0_names_r4000, NULL, 0, mips_cp1_names_mips,
mips_hwr_names_numeric },
{ "r4600", 1, bfd_mach_mips4600, CPU_R4600, ISA_MIPS3, 0,
- mips_cp0_names_numeric, NULL, 0, mips_cp1_names_numeric,
+ mips_cp0_names_numeric, NULL, 0, mips_cp1_names_mips,
mips_hwr_names_numeric },
{ "r4650", 1, bfd_mach_mips4650, CPU_R4650, ISA_MIPS3, 0,
- mips_cp0_names_numeric, NULL, 0, mips_cp1_names_numeric,
+ mips_cp0_names_numeric, NULL, 0, mips_cp1_names_mips,
mips_hwr_names_numeric },
{ "r5000", 1, bfd_mach_mips5000, CPU_R5000, ISA_MIPS4, 0,
- mips_cp0_names_numeric, NULL, 0, mips_cp1_names_numeric,
+ mips_cp0_names_numeric, NULL, 0, mips_cp1_names_mips,
mips_hwr_names_numeric },
{ "vr5400", 1, bfd_mach_mips5400, CPU_VR5400, ISA_MIPS4, 0,
- mips_cp0_names_numeric, NULL, 0, mips_cp1_names_numeric,
+ mips_cp0_names_numeric, NULL, 0, mips_cp1_names_mips,
mips_hwr_names_numeric },
{ "vr5500", 1, bfd_mach_mips5500, CPU_VR5500, ISA_MIPS4, 0,
- mips_cp0_names_numeric, NULL, 0, mips_cp1_names_numeric,
+ mips_cp0_names_numeric, NULL, 0, mips_cp1_names_mips,
mips_hwr_names_numeric },
{ "r5900", 1, bfd_mach_mips5900, CPU_R5900, ISA_MIPS3, 0,
- mips_cp0_names_r5900, NULL, 0, mips_cp1_names_numeric,
+ mips_cp0_names_r5900, NULL, 0, mips_cp1_names_mips,
mips_hwr_names_numeric },
{ "r6000", 1, bfd_mach_mips6000, CPU_R6000, ISA_MIPS2, 0,
- mips_cp0_names_numeric, NULL, 0, mips_cp1_names_numeric,
+ mips_cp0_names_numeric, NULL, 0, mips_cp1_names_mips,
mips_hwr_names_numeric },
{ "rm7000", 1, bfd_mach_mips7000, CPU_RM7000, ISA_MIPS4, 0,
- mips_cp0_names_numeric, NULL, 0, mips_cp1_names_numeric,
+ mips_cp0_names_numeric, NULL, 0, mips_cp1_names_mips,
mips_hwr_names_numeric },
{ "rm9000", 1, bfd_mach_mips7000, CPU_RM7000, ISA_MIPS4, 0,
- mips_cp0_names_numeric, NULL, 0, mips_cp1_names_numeric,
+ mips_cp0_names_numeric, NULL, 0, mips_cp1_names_mips,
mips_hwr_names_numeric },
{ "r8000", 1, bfd_mach_mips8000, CPU_R8000, ISA_MIPS4, 0,
- mips_cp0_names_numeric, NULL, 0, mips_cp1_names_numeric,
+ mips_cp0_names_numeric, NULL, 0, mips_cp1_names_mips,
mips_hwr_names_numeric },
{ "r10000", 1, bfd_mach_mips10000, CPU_R10000, ISA_MIPS4, 0,
- mips_cp0_names_numeric, NULL, 0, mips_cp1_names_numeric,
+ mips_cp0_names_numeric, NULL, 0, mips_cp1_names_mips,
mips_hwr_names_numeric },
{ "r12000", 1, bfd_mach_mips12000, CPU_R12000, ISA_MIPS4, 0,
- mips_cp0_names_numeric, NULL, 0, mips_cp1_names_numeric,
+ mips_cp0_names_numeric, NULL, 0, mips_cp1_names_mips,
mips_hwr_names_numeric },
{ "r14000", 1, bfd_mach_mips14000, CPU_R14000, ISA_MIPS4, 0,
- mips_cp0_names_numeric, NULL, 0, mips_cp1_names_numeric,
+ mips_cp0_names_numeric, NULL, 0, mips_cp1_names_mips,
mips_hwr_names_numeric },
{ "r16000", 1, bfd_mach_mips16000, CPU_R16000, ISA_MIPS4, 0,
- mips_cp0_names_numeric, NULL, 0, mips_cp1_names_numeric,
+ mips_cp0_names_numeric, NULL, 0, mips_cp1_names_mips,
mips_hwr_names_numeric },
{ "mips5", 1, bfd_mach_mips5, CPU_MIPS5, ISA_MIPS5, 0,
- mips_cp0_names_numeric, NULL, 0, mips_cp1_names_numeric,
+ mips_cp0_names_numeric, NULL, 0, mips_cp1_names_mips,
mips_hwr_names_numeric },
/* For stock MIPS32, disassemble all applicable MIPS-specified ASEs.
@@ -636,11 +648,11 @@ const struct mips_arch_choice mips_arch_
{ "loongson2e", 1, bfd_mach_mips_loongson_2e, CPU_LOONGSON_2E,
ISA_MIPS3 | INSN_LOONGSON_2E, 0, mips_cp0_names_numeric,
- NULL, 0, mips_cp1_names_numeric, mips_hwr_names_numeric },
+ NULL, 0, mips_cp1_names_mips, mips_hwr_names_numeric },
{ "loongson2f", 1, bfd_mach_mips_loongson_2f, CPU_LOONGSON_2F,
ISA_MIPS3 | INSN_LOONGSON_2F, ASE_LOONGSON_MMI, mips_cp0_names_numeric,
- NULL, 0, mips_cp1_names_numeric, mips_hwr_names_numeric },
+ NULL, 0, mips_cp1_names_mips, mips_hwr_names_numeric },
/* The loongson3a is an alias of gs464 for compatibility */
{ "loongson3a", 1, bfd_mach_mips_gs464, CPU_GS464,
^ permalink raw reply [flat|nested] 19+ messages in thread
* [committed 09/18] MIPS/opcodes: Factor out ISA matching against flags
2021-05-29 1:36 [committed 00/18] MIPS coprocessor opcodes handling fixes Maciej W. Rozycki
` (7 preceding siblings ...)
2021-05-29 1:37 ` [committed 08/18] MIPS/opcodes: Add legacy CP1 control register names Maciej W. Rozycki
@ 2021-05-29 1:37 ` Maciej W. Rozycki
2021-05-29 1:37 ` [committed 10/18] MIPS/opcodes: Properly handle ISA exclusion Maciej W. Rozycki
` (8 subsequent siblings)
17 siblings, 0 replies; 19+ messages in thread
From: Maciej W. Rozycki @ 2021-05-29 1:37 UTC (permalink / raw)
To: binutils
In preparation for the next change factor out code for ISA matching
against instruction flags used in MIPS opcode tables, similarly to how
CPU matching is already done. No functional change, though for clarity
split the single `if' statement into multiple ones and use temporaries
rather than repeated expressions.
include/
* opcode/mips.h (isa_is_member): New inline function, factored
out from...
(opcode_is_member): ... here.
---
include/opcode/mips.h | 25 +++++++++++++++++++++----
1 file changed, 21 insertions(+), 4 deletions(-)
binutils-mips-opcodes-isa-is-member.diff
Index: binutils-gdb/include/opcode/mips.h
===================================================================
--- binutils-gdb.orig/include/opcode/mips.h
+++ binutils-gdb/include/opcode/mips.h
@@ -1471,6 +1471,26 @@ cpu_is_member (int cpu, unsigned int mas
}
}
+/* Return true if the given ISA is included in INSN_* mask MASK. */
+
+static inline bool
+isa_is_member (int isa, unsigned int mask)
+{
+ isa &= INSN_ISA_MASK;
+ mask &= INSN_ISA_MASK;
+
+ if (isa == 0)
+ return false;
+
+ if (mask == 0)
+ return false;
+
+ if (((mips_isa_table[isa - 1] >> (mask - 1)) & 1) == 0)
+ return false;
+
+ return true;
+}
+
/* Test for membership in an ISA including chip specific ISAs. INSN
is pointer to an element of the opcode table; ISA is the specified
ISA/ASE bitmask to test against; and CPU is the CPU specific ISA to
@@ -1483,10 +1503,7 @@ opcode_is_member (const struct mips_opco
if (!cpu_is_member (cpu, insn->exclusions))
{
/* Test for ISA level compatibility. */
- if ((isa & INSN_ISA_MASK) != 0
- && (insn->membership & INSN_ISA_MASK) != 0
- && ((mips_isa_table[(isa & INSN_ISA_MASK) - 1]
- >> ((insn->membership & INSN_ISA_MASK) - 1)) & 1) != 0)
+ if (isa_is_member (isa, insn->membership))
return true;
/* Test for ASE compatibility. */
^ permalink raw reply [flat|nested] 19+ messages in thread
* [committed 10/18] MIPS/opcodes: Properly handle ISA exclusion
2021-05-29 1:36 [committed 00/18] MIPS coprocessor opcodes handling fixes Maciej W. Rozycki
` (8 preceding siblings ...)
2021-05-29 1:37 ` [committed 09/18] MIPS/opcodes: Factor out ISA matching against flags Maciej W. Rozycki
@ 2021-05-29 1:37 ` Maciej W. Rozycki
2021-05-29 1:37 ` [committed 11/18] MIPS/opcodes: Disassemble the RFE instruction Maciej W. Rozycki
` (7 subsequent siblings)
17 siblings, 0 replies; 19+ messages in thread
From: Maciej W. Rozycki @ 2021-05-29 1:37 UTC (permalink / raw)
To: binutils
Remove the hack used for MIPSr6 ISA exclusion from `cpu_is_member' and
handle the exclusion for any ISA levels properly in `opcode_is_member'.
Flatten the structure of the `if' statements there. No functional
change for the existing opcode tables.
include/
* opcode/mips.h (cpu_is_member): Remove code for MIPSr6 ISA
exclusion.
(opcode_is_member): Handle ISA level exclusion.
---
include/opcode/mips.h | 37 ++++++++++++++++++-------------------
1 file changed, 18 insertions(+), 19 deletions(-)
binutils-mips-opcodes-exclude-isa.diff
Index: binutils-gdb/include/opcode/mips.h
===================================================================
--- binutils-gdb.orig/include/opcode/mips.h
+++ binutils-gdb/include/opcode/mips.h
@@ -1459,13 +1459,6 @@ cpu_is_member (int cpu, unsigned int mas
case CPU_INTERAPTIV_MR2:
return (mask & INSN_INTERAPTIV_MR2) != 0;
- case CPU_MIPS32R6:
- return (mask & INSN_ISA_MASK) == INSN_ISA32R6;
-
- case CPU_MIPS64R6:
- return ((mask & INSN_ISA_MASK) == INSN_ISA32R6)
- || ((mask & INSN_ISA_MASK) == INSN_ISA64R6);
-
default:
return false;
}
@@ -1500,20 +1493,26 @@ isa_is_member (int isa, unsigned int mas
static inline bool
opcode_is_member (const struct mips_opcode *insn, int isa, int ase, int cpu)
{
- if (!cpu_is_member (cpu, insn->exclusions))
- {
- /* Test for ISA level compatibility. */
- if (isa_is_member (isa, insn->membership))
- return true;
+ /* Test for ISA level exclusion. */
+ if (isa_is_member (isa, insn->exclusions))
+ return false;
- /* Test for ASE compatibility. */
- if ((ase & insn->ase) != 0)
- return true;
+ /* Test for processor-specific exclusion. */
+ if (cpu_is_member (cpu, insn->exclusions))
+ return false;
+
+ /* Test for ISA level compatibility. */
+ if (isa_is_member (isa, insn->membership))
+ return true;
+
+ /* Test for ASE compatibility. */
+ if ((ase & insn->ase) != 0)
+ return true;
+
+ /* Test for processor-specific extensions. */
+ if (cpu_is_member (cpu, insn->membership))
+ return true;
- /* Test for processor-specific extensions. */
- if (cpu_is_member (cpu, insn->membership))
- return true;
- }
return false;
}
^ permalink raw reply [flat|nested] 19+ messages in thread
* [committed 11/18] MIPS/opcodes: Disassemble the RFE instruction
2021-05-29 1:36 [committed 00/18] MIPS coprocessor opcodes handling fixes Maciej W. Rozycki
` (9 preceding siblings ...)
2021-05-29 1:37 ` [committed 10/18] MIPS/opcodes: Properly handle ISA exclusion Maciej W. Rozycki
@ 2021-05-29 1:37 ` Maciej W. Rozycki
2021-05-29 1:37 ` [committed 12/18] MIPS/GAS/testsuite: Add tests for coprocessor branch instructions Maciej W. Rozycki
` (6 subsequent siblings)
17 siblings, 0 replies; 19+ messages in thread
From: Maciej W. Rozycki @ 2021-05-29 1:37 UTC (permalink / raw)
To: binutils
Fix a commit b015e599c772 ("[MIPS] Add new virtualization instructions"),
<https://sourceware.org/ml/binutils/2013-05/msg00118.html>, regression
and bring the disassembly of the RFE instruction back for the relevant
ISA levels.
It is because the "rfe" opcode table entry was incorrectly moved behind
the catch-all generic "c0" entry for CP0 instructions, causing output
like:
00: 42000010 c0 0x10
to be produced rather than:
00: 42000010 rfe
even for ISA levels that do include the RFE instruction.
Move the "rfe" entry ahead of "c0" then, correcting the problem. Add a
suitable test case.
opcodes/
* mips-opc.c (mips_builtin_opcodes): Move the "rfe" entry ahead
of "c0".
gas/
* testsuite/gas/mips/rfe.d: New test.
* testsuite/gas/mips/rfe.s: New test source.
* testsuite/gas/mips/mips.exp: Run the new test.
---
gas/testsuite/gas/mips/mips.exp | 3 +++
gas/testsuite/gas/mips/rfe.d | 9 +++++++++
gas/testsuite/gas/mips/rfe.s | 8 ++++++++
opcodes/mips-opc.c | 5 +++--
4 files changed, 23 insertions(+), 2 deletions(-)
binutils-mips-opcodes-rfe.diff
Index: binutils-gdb/gas/testsuite/gas/mips/mips.exp
===================================================================
--- binutils-gdb.orig/gas/testsuite/gas/mips/mips.exp
+++ binutils-gdb/gas/testsuite/gas/mips/mips.exp
@@ -1338,6 +1338,9 @@ if { [istarget mips*-*-vxworks*] } {
run_dump_test_arches "cp0m" [mips_arch_list_matching mips1 \
!mips2 !micromips]
+ run_dump_test_arches "rfe" [mips_arch_list_matching mips1 \
+ !mips3 !mips32 !micromips]
+
run_dump_test "cp1-names-numeric"
run_dump_test "cp1-names-r3000"
run_dump_test "cp1-names-r3900"
Index: binutils-gdb/gas/testsuite/gas/mips/rfe.d
===================================================================
--- /dev/null
+++ binutils-gdb/gas/testsuite/gas/mips/rfe.d
@@ -0,0 +1,9 @@
+#objdump: -d --prefix-addresses --show-raw-insn
+#name: MIPS RFE instruction
+#as: -32
+
+.*: +file format .*mips.*
+
+Disassembly of section \.text:
+[0-9a-f]+ <[^>]*> 42000010 rfe
+ \.\.\.
Index: binutils-gdb/gas/testsuite/gas/mips/rfe.s
===================================================================
--- /dev/null
+++ binutils-gdb/gas/testsuite/gas/mips/rfe.s
@@ -0,0 +1,8 @@
+ .text
+ .set noreorder
+foo:
+ rfe
+
+# Force some (non-delay-slot) zero bytes, to make 'objdump' print ...
+ .align 4, 0
+ .space 16
Index: binutils-gdb/opcodes/mips-opc.c
===================================================================
--- binutils-gdb.orig/opcodes/mips-opc.c
+++ binutils-gdb/opcodes/mips-opc.c
@@ -3399,6 +3399,9 @@ const struct mips_opcode mips_builtin_op
{"ginvi", "s", 0x7c00003d, 0xfc1fffff, RD_1, 0, 0, GINV, 0 },
{"ginvt", "s,+\\", 0x7c0000bd, 0xfc1ffcff, RD_1, 0, 0, GINV, 0 },
+/* RFE conflicts with the new Virt spec instruction tlbgp. */
+{"rfe", "", 0x42000010, 0xffffffff, 0, 0, I1|T3, 0, 0 },
+
/* No hazard protection on coprocessor instructions--they shouldn't
change the state of the processor and if they do it's up to the
user to put in nops as necessary. These are at the end so that the
@@ -3411,8 +3414,6 @@ const struct mips_opcode mips_builtin_op
{"cop1", "C", 0, (int) M_COP1, INSN_MACRO, INSN2_M_FP_S, I1, 0, 0 },
{"cop2", "C", 0, (int) M_COP2, INSN_MACRO, 0, I1, 0, IOCT|IOCTP|IOCT2 },
{"cop3", "C", 0, (int) M_COP3, INSN_MACRO, 0, I1, 0, IOCT|IOCTP|IOCT2 },
-/* RFE conflicts with the new Virt spec instruction tlbgp. */
-{"rfe", "", 0x42000010, 0xffffffff, 0, 0, I1|T3, 0, 0 },
};
#define MIPS_NUM_OPCODES \
^ permalink raw reply [flat|nested] 19+ messages in thread
* [committed 12/18] MIPS/GAS/testsuite: Add tests for coprocessor branch instructions
2021-05-29 1:36 [committed 00/18] MIPS coprocessor opcodes handling fixes Maciej W. Rozycki
` (10 preceding siblings ...)
2021-05-29 1:37 ` [committed 11/18] MIPS/opcodes: Disassemble the RFE instruction Maciej W. Rozycki
@ 2021-05-29 1:37 ` Maciej W. Rozycki
2021-05-29 1:37 ` [committed 13/18] MIPS/opcodes: Remove DMFC3 and DMTC3 instructions Maciej W. Rozycki
` (5 subsequent siblings)
17 siblings, 0 replies; 19+ messages in thread
From: Maciej W. Rozycki @ 2021-05-29 1:37 UTC (permalink / raw)
To: binutils
Cover basic CP0, CP2, CP3 branch and branch-likely instructions across
the relevant ISA levels. Omit CP1 branches, covered elsewhere.
gas/
* testsuite/gas/mips/cp0b.d: New test.
* testsuite/gas/mips/cp0bl.d: New test.
* testsuite/gas/mips/cp2b.d: New test.
* testsuite/gas/mips/micromips@cp2b.d: New test.
* testsuite/gas/mips/cp2bl.d: New test.
* testsuite/gas/mips/micromips@cp2bl.d: New test.
* testsuite/gas/mips/cp3b.d: New test.
* testsuite/gas/mips/cp3bl.d: New test.
* testsuite/gas/mips/cp0b.s: New test source.
* testsuite/gas/mips/cp0bl.s: New test source.
* testsuite/gas/mips/cp2b.s: New test source.
* testsuite/gas/mips/cp2bl.s: New test source.
* testsuite/gas/mips/cp3b.s: New test source.
* testsuite/gas/mips/cp3bl.s: New test source.
* testsuite/gas/mips/mips.exp: Run the new tests.
---
gas/testsuite/gas/mips/cp0b.d | 12 ++++++++++++
gas/testsuite/gas/mips/cp0b.s | 13 +++++++++++++
gas/testsuite/gas/mips/cp0bl.d | 12 ++++++++++++
gas/testsuite/gas/mips/cp0bl.s | 14 ++++++++++++++
gas/testsuite/gas/mips/cp2b.d | 12 ++++++++++++
gas/testsuite/gas/mips/cp2b.s | 13 +++++++++++++
gas/testsuite/gas/mips/cp2bl.d | 12 ++++++++++++
gas/testsuite/gas/mips/cp2bl.s | 14 ++++++++++++++
gas/testsuite/gas/mips/cp3b.d | 12 ++++++++++++
gas/testsuite/gas/mips/cp3b.s | 13 +++++++++++++
gas/testsuite/gas/mips/cp3bl.d | 12 ++++++++++++
gas/testsuite/gas/mips/cp3bl.s | 14 ++++++++++++++
gas/testsuite/gas/mips/micromips@cp2b.d | 14 ++++++++++++++
gas/testsuite/gas/mips/micromips@cp2bl.d | 18 ++++++++++++++++++
gas/testsuite/gas/mips/mips.exp | 12 ++++++++++++
15 files changed, 197 insertions(+)
binutils-mips-cp-branch-test.diff
Index: binutils-gdb/gas/testsuite/gas/mips/cp0b.d
===================================================================
--- /dev/null
+++ binutils-gdb/gas/testsuite/gas/mips/cp0b.d
@@ -0,0 +1,12 @@
+#objdump: -d --prefix-addresses --show-raw-insn
+#name: MIPS CP0 branch instructions
+#as: -32
+
+.*: +file format .*mips.*
+
+Disassembly of section \.text:
+[0-9a-f]+ <[^>]*> 41000001 bc0f [0-9a-f]+ <[^>]*>
+[0-9a-f]+ <[^>]*> 02108026 xor s0,s0,s0
+[0-9a-f]+ <[^>]*> 41010001 bc0t [0-9a-f]+ <[^>]*>
+[0-9a-f]+ <[^>]*> 02108026 xor s0,s0,s0
+ \.\.\.
Index: binutils-gdb/gas/testsuite/gas/mips/cp0b.s
===================================================================
--- /dev/null
+++ binutils-gdb/gas/testsuite/gas/mips/cp0b.s
@@ -0,0 +1,13 @@
+ .text
+foo:
+ xor $16, $16
+ bc0f 0f
+0:
+ xor $16, $16
+ bc0t 0f
+0:
+ .insn
+
+# Force some (non-delay-slot) zero bytes, to make 'objdump' print ...
+ .align 4, 0
+ .space 16
Index: binutils-gdb/gas/testsuite/gas/mips/cp0bl.d
===================================================================
--- /dev/null
+++ binutils-gdb/gas/testsuite/gas/mips/cp0bl.d
@@ -0,0 +1,12 @@
+#objdump: -d --prefix-addresses --show-raw-insn
+#name: MIPS CP0 branch likely instructions
+#as: -32
+
+.*: +file format .*mips.*
+
+Disassembly of section \.text:
+[0-9a-f]+ <[^>]*> 41020001 bc0fl [0-9a-f]+ <[^>]*>
+[0-9a-f]+ <[^>]*> 02108026 xor s0,s0,s0
+[0-9a-f]+ <[^>]*> 41030001 bc0tl [0-9a-f]+ <[^>]*>
+[0-9a-f]+ <[^>]*> 02108026 xor s0,s0,s0
+ \.\.\.
Index: binutils-gdb/gas/testsuite/gas/mips/cp0bl.s
===================================================================
--- /dev/null
+++ binutils-gdb/gas/testsuite/gas/mips/cp0bl.s
@@ -0,0 +1,14 @@
+ .text
+ .set noreorder
+foo:
+ bc0fl 0f
+ xor $16, $16
+0:
+ bc0tl 0f
+ xor $16, $16
+0:
+ .insn
+
+# Force some (non-delay-slot) zero bytes, to make 'objdump' print ...
+ .align 4, 0
+ .space 16
Index: binutils-gdb/gas/testsuite/gas/mips/cp2b.d
===================================================================
--- /dev/null
+++ binutils-gdb/gas/testsuite/gas/mips/cp2b.d
@@ -0,0 +1,12 @@
+#objdump: -d --prefix-addresses --show-raw-insn
+#name: MIPS CP2 branch instructions
+#as: -32
+
+.*: +file format .*mips.*
+
+Disassembly of section \.text:
+[0-9a-f]+ <[^>]*> 49000001 bc2f [0-9a-f]+ <[^>]*>
+[0-9a-f]+ <[^>]*> 02108026 xor s0,s0,s0
+[0-9a-f]+ <[^>]*> 49010001 bc2t [0-9a-f]+ <[^>]*>
+[0-9a-f]+ <[^>]*> 02108026 xor s0,s0,s0
+ \.\.\.
Index: binutils-gdb/gas/testsuite/gas/mips/cp2b.s
===================================================================
--- /dev/null
+++ binutils-gdb/gas/testsuite/gas/mips/cp2b.s
@@ -0,0 +1,13 @@
+ .text
+foo:
+ xor $16, $16
+ bc2f 0f
+0:
+ xor $16, $16
+ bc2t 0f
+0:
+ .insn
+
+# Force some (non-delay-slot) zero bytes, to make 'objdump' print ...
+ .align 4, 0
+ .space 16
Index: binutils-gdb/gas/testsuite/gas/mips/cp2bl.d
===================================================================
--- /dev/null
+++ binutils-gdb/gas/testsuite/gas/mips/cp2bl.d
@@ -0,0 +1,12 @@
+#objdump: -d --prefix-addresses --show-raw-insn
+#name: MIPS CP2 branch likely instructions
+#as: -32
+
+.*: +file format .*mips.*
+
+Disassembly of section \.text:
+[0-9a-f]+ <[^>]*> 49020001 bc2fl [0-9a-f]+ <[^>]*>
+[0-9a-f]+ <[^>]*> 02108026 xor s0,s0,s0
+[0-9a-f]+ <[^>]*> 49030001 bc2tl [0-9a-f]+ <[^>]*>
+[0-9a-f]+ <[^>]*> 02108026 xor s0,s0,s0
+ \.\.\.
Index: binutils-gdb/gas/testsuite/gas/mips/cp2bl.s
===================================================================
--- /dev/null
+++ binutils-gdb/gas/testsuite/gas/mips/cp2bl.s
@@ -0,0 +1,14 @@
+ .text
+ .set noreorder
+foo:
+ bc2fl 0f
+ xor $16, $16
+0:
+ bc2tl 0f
+ xor $16, $16
+0:
+ .insn
+
+# Force some (non-delay-slot) zero bytes, to make 'objdump' print ...
+ .align 4, 0
+ .space 16
Index: binutils-gdb/gas/testsuite/gas/mips/cp3b.d
===================================================================
--- /dev/null
+++ binutils-gdb/gas/testsuite/gas/mips/cp3b.d
@@ -0,0 +1,12 @@
+#objdump: -d --prefix-addresses --show-raw-insn
+#name: MIPS CP3 branch instructions
+#as: -32
+
+.*: +file format .*mips.*
+
+Disassembly of section \.text:
+[0-9a-f]+ <[^>]*> 4d000001 bc3f [0-9a-f]+ <[^>]*>
+[0-9a-f]+ <[^>]*> 02108026 xor s0,s0,s0
+[0-9a-f]+ <[^>]*> 4d010001 bc3t [0-9a-f]+ <[^>]*>
+[0-9a-f]+ <[^>]*> 02108026 xor s0,s0,s0
+ \.\.\.
Index: binutils-gdb/gas/testsuite/gas/mips/cp3b.s
===================================================================
--- /dev/null
+++ binutils-gdb/gas/testsuite/gas/mips/cp3b.s
@@ -0,0 +1,13 @@
+ .text
+foo:
+ xor $16, $16
+ bc3f 0f
+0:
+ xor $16, $16
+ bc3t 0f
+0:
+ .insn
+
+# Force some (non-delay-slot) zero bytes, to make 'objdump' print ...
+ .align 4, 0
+ .space 16
Index: binutils-gdb/gas/testsuite/gas/mips/cp3bl.d
===================================================================
--- /dev/null
+++ binutils-gdb/gas/testsuite/gas/mips/cp3bl.d
@@ -0,0 +1,12 @@
+#objdump: -d --prefix-addresses --show-raw-insn
+#name: MIPS CP3 branch likely instructions
+#as: -32
+
+.*: +file format .*mips.*
+
+Disassembly of section \.text:
+[0-9a-f]+ <[^>]*> 4d020001 bc3fl [0-9a-f]+ <[^>]*>
+[0-9a-f]+ <[^>]*> 02108026 xor s0,s0,s0
+[0-9a-f]+ <[^>]*> 4d030001 bc3tl [0-9a-f]+ <[^>]*>
+[0-9a-f]+ <[^>]*> 02108026 xor s0,s0,s0
+ \.\.\.
Index: binutils-gdb/gas/testsuite/gas/mips/cp3bl.s
===================================================================
--- /dev/null
+++ binutils-gdb/gas/testsuite/gas/mips/cp3bl.s
@@ -0,0 +1,14 @@
+ .text
+ .set noreorder
+foo:
+ bc3fl 0f
+ xor $16, $16
+0:
+ bc3tl 0f
+ xor $16, $16
+0:
+ .insn
+
+# Force some (non-delay-slot) zero bytes, to make 'objdump' print ...
+ .align 4, 0
+ .space 16
Index: binutils-gdb/gas/testsuite/gas/mips/micromips@cp2b.d
===================================================================
--- /dev/null
+++ binutils-gdb/gas/testsuite/gas/mips/micromips@cp2b.d
@@ -0,0 +1,14 @@
+#objdump: -d --prefix-addresses --show-raw-insn
+#name: MIPS CP2 branch instructions
+#as: -32
+#source: cp2b.s
+
+.*: +file format .*mips.*
+
+Disassembly of section \.text:
+[0-9a-f]+ <[^>]*> 4280 fffe bc2f [0-9a-f]+ <[^>]*>
+[0-9a-f]+ <[^>]*> 4440 xor s0,s0,s0
+[0-9a-f]+ <[^>]*> 42a0 fffe bc2t [0-9a-f]+ <[^>]*>
+[0-9a-f]+ <[^>]*> 4440 xor s0,s0,s0
+[0-9a-f]+ <[^>]*> 0000 0000 nop
+ \.\.\.
Index: binutils-gdb/gas/testsuite/gas/mips/micromips@cp2bl.d
===================================================================
--- /dev/null
+++ binutils-gdb/gas/testsuite/gas/mips/micromips@cp2bl.d
@@ -0,0 +1,18 @@
+#objdump: -d --prefix-addresses --show-raw-insn
+#name: MIPS CP2 branch likely instructions
+#as: -32
+#source: cp2bl.s
+
+.*: +file format .*mips.*
+
+Disassembly of section \.text:
+[0-9a-f]+ <[^>]*> 42a0 fffe bc2t [0-9a-f]+ <[^>]*>
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> 9400 fffe b [0-9a-f]+ <[^>]*>
+[0-9a-f]+ <[^>]*> 4440 xor s0,s0,s0
+[0-9a-f]+ <[^>]*> 4280 fffe bc2f [0-9a-f]+ <[^>]*>
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> 9400 fffe b [0-9a-f]+ <[^>]*>
+[0-9a-f]+ <[^>]*> 4440 xor s0,s0,s0
+ \.\.\.
+ \.\.\.
Index: binutils-gdb/gas/testsuite/gas/mips/mips.exp
===================================================================
--- binutils-gdb.orig/gas/testsuite/gas/mips/mips.exp
+++ binutils-gdb/gas/testsuite/gas/mips/mips.exp
@@ -1335,6 +1335,10 @@ if { [istarget mips*-*-vxworks*] } {
run_dump_test_arches "cp0c" [mips_arch_list_matching mips1 \
!mips32 !micromips]
+ run_dump_test_arches "cp0b" [mips_arch_list_matching mips1 \
+ !mips4 !mips32 !micromips]
+ run_dump_test_arches "cp0bl" [mips_arch_list_matching mips2 \
+ !mips4 !mips32 !micromips]
run_dump_test_arches "cp0m" [mips_arch_list_matching mips1 \
!mips2 !micromips]
@@ -1358,6 +1362,10 @@ if { [istarget mips*-*-vxworks*] } {
!vr5400 !r5900 !octeon]
run_dump_test_arches "cp2-64" [mips_arch_list_matching mips3 \
!vr5400 !r5900 !octeon]
+ run_dump_test_arches "cp2b" [mips_arch_list_matching mips1 \
+ !mips32r6 !vr5400 !r5900 !octeon]
+ run_dump_test_arches "cp2bl" [mips_arch_list_matching mips2 \
+ !mips32r6 !vr5400 !r5900 !octeon]
run_dump_test_arches "cp2m" [mips_arch_list_matching mips1 \
!vr5400 !r5900 !octeon]
run_dump_test_arches "cp2d" [mips_arch_list_matching mips2 \
@@ -1365,6 +1373,10 @@ if { [istarget mips*-*-vxworks*] } {
run_dump_test_arches "cp3" [mips_arch_list_matching mips1 \
!mips3 !mips32r2 !micromips]
+ run_dump_test_arches "cp3b" [mips_arch_list_matching mips1 \
+ !mips3 !mips32r2 !micromips]
+ run_dump_test_arches "cp3bl" [mips_arch_list_matching mips2 \
+ !mips3 !mips32r2 !micromips]
run_dump_test_arches "cp3m" [mips_arch_list_matching mips1 \
!mips3 !mips32 !micromips]
run_dump_test_arches "cp3d" [mips_arch_list_matching mips2 \
^ permalink raw reply [flat|nested] 19+ messages in thread
* [committed 13/18] MIPS/opcodes: Remove DMFC3 and DMTC3 instructions
2021-05-29 1:36 [committed 00/18] MIPS coprocessor opcodes handling fixes Maciej W. Rozycki
` (11 preceding siblings ...)
2021-05-29 1:37 ` [committed 12/18] MIPS/GAS/testsuite: Add tests for coprocessor branch instructions Maciej W. Rozycki
@ 2021-05-29 1:37 ` Maciej W. Rozycki
2021-05-29 1:37 ` [committed 14/18] MIPS/opcodes: Accurately record coprocessor opcode CPU/ISA membership Maciej W. Rozycki
` (4 subsequent siblings)
17 siblings, 0 replies; 19+ messages in thread
From: Maciej W. Rozycki @ 2021-05-29 1:37 UTC (permalink / raw)
To: binutils
Coprocessor 3 has been removed from the MIPS ISA as from MIPS III[1][2]
with the LDC3 and SDC3 instructions having been replaced with LD and SD
instructions respectively and therefore the doubleword move instructions
from and to that coprocessor have never materialized (for 32-bit ISAs
coprocessor 3 has likewise been removed as from MIPS32r2[3]). Remove
the DMFC3 and DMTC3 instructions from the opcode table then to avoid
confusion.
References:
[1] Charles Price, "MIPS IV Instruction Set", MIPS Technologies, Inc.,
Revision 3.2, September, 1995, Section A 8.3.4 "Coprocessor 3 - COP3
and CP3 load/store", p. A-176
[2] same, Table A-39 "CPU Instruction Encoding - MIPS III Architecture",
p. A-179
[3] "MIPS32 Architecture For Programmers, Volume II: The MIPS32
Instruction Set", MIPS Technologies, Inc., Document Number: MD00086,
Revision 2.00, June 9, 2003, Table A-2 "MIPS32 Encoding of the
Opcode Field", p. 317
opcodes/
* mips-opc.c (mips_builtin_opcodes): Remove "dmfc3" and "dmtc3"
entries and associated comments.
---
opcodes/mips-opc.c | 4 ----
1 file changed, 4 deletions(-)
binutils-mips-opcodes-dmxc3-remove.diff
Index: binutils-gdb/opcodes/mips-opc.c
===================================================================
--- binutils-gdb.orig/opcodes/mips-opc.c
+++ binutils-gdb/opcodes/mips-opc.c
@@ -1112,8 +1112,6 @@ const struct mips_opcode mips_builtin_op
{"dmtc1", "t,G", 0x44a00000, 0xffe007ff, RD_1|WR_2|CM|FP_D, 0, I3, 0, SF },
/* dmfc2 is at the bottom of the table. */
/* dmtc2 is at the bottom of the table. */
-/* dmfc3 is at the bottom of the table. */
-/* dmtc3 is at the bottom of the table. */
{"dmuh", "d,s,t", 0x000000dc, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I69, 0, 0 },
{"dmul", "d,s,t", 0x0000009c, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I69, 0, 0 },
{"dmul", "d,v,t", 0x70000003, 0xfc0007ff, WR_1|RD_2|RD_3|WR_HILO, 0, IOCT, 0, 0 },
@@ -2161,8 +2159,6 @@ const struct mips_opcode mips_builtin_op
{"bc3tl", "p", 0x4d030000, 0xffff0000, RD_CC|CBL, 0, I2|T3, 0, IOCT|IOCTP|IOCT2|EE|I37 },
{"cfc3", "t,g", 0x4c400000, 0xffe007ff, WR_1|RD_C3|LC, 0, I1, 0, IOCT|IOCTP|IOCT2|EE|I37 },
{"ctc3", "t,g", 0x4cc00000, 0xffe007ff, RD_1|WR_CC|CM, 0, I1, 0, IOCT|IOCTP|IOCT2|EE|I37 },
-{"dmfc3", "t,G", 0x4c200000, 0xffe007ff, WR_1|RD_C3|LC, 0, I3, 0, IOCT|IOCTP|IOCT2|EE|I37 },
-{"dmtc3", "t,G", 0x4ca00000, 0xffe007ff, RD_1|WR_C3|WR_CC|CM, 0, I3, 0, IOCT|IOCTP|IOCT2|EE|I37 },
{"mfc3", "t,G", 0x4c000000, 0xffe007ff, WR_1|RD_C3|LC, 0, I1, 0, IOCT|IOCTP|IOCT2|EE|I37 },
{"mfc3", "t,G,H", 0x4c000000, 0xffe007f8, WR_1|RD_C3|LC, 0, I32, 0, IOCT|IOCTP|IOCT2|EE|I37 },
{"mtc3", "t,G", 0x4c800000, 0xffe007ff, RD_1|WR_C3|WR_CC|CM, 0, I1, 0, IOCT|IOCTP|IOCT2|EE|I37 },
^ permalink raw reply [flat|nested] 19+ messages in thread
* [committed 14/18] MIPS/opcodes: Accurately record coprocessor opcode CPU/ISA membership
2021-05-29 1:36 [committed 00/18] MIPS coprocessor opcodes handling fixes Maciej W. Rozycki
` (12 preceding siblings ...)
2021-05-29 1:37 ` [committed 13/18] MIPS/opcodes: Remove DMFC3 and DMTC3 instructions Maciej W. Rozycki
@ 2021-05-29 1:37 ` Maciej W. Rozycki
2021-05-29 1:37 ` [committed 15/18] MIPS/GAS/testsuite: Run coprocessor tests across all ISAs Maciej W. Rozycki
` (3 subsequent siblings)
17 siblings, 0 replies; 19+ messages in thread
From: Maciej W. Rozycki @ 2021-05-29 1:37 UTC (permalink / raw)
To: binutils
Adjust opcode table entries for coprocessor instructions that have been
removed from certain ISA levels or CPU implementations as follows:
- remove CP0 memory access instructions from MIPS II up as the LWC0 and
SWC0 opcodes have been reused for the LL and SC instructions
respectively[1]; strictly speaking LWC0 and SWC0 have never really
been defined in the first place[2], but let's keep them for now in
case an odd implementation did,
- remove CP0 branch instructions from MIPS IV[3] and MIPS32[4] up, as
they have been removed as from those ISAs,
- remove CP0 control register move instructions from MIPS32 up, as they
have been removed as from that ISA[5],
- remove the RFE instruction from MIPS III[6] and MIPS32[7] up, as it
has been removed as from those ISAs in favour to ERET,
- remove CP2 instructions from Vr5400 CPUs as their encodings have been
reused for the multimedia instruction set extensions[8] and no CP2
registers exist[9],
- remove CP3 memory access instructions from MIPS III up as coprocessor
3 has been removed as from that ISA[10][11] and from MIPS32 up as the
LWC3 opcode has been reused for the PREF instruction and consequently
all the four memory access instructions removed from the ISA (though
the COP3 opcode has been retained)[12].
Update the testsuite accordingly.
References:
[1] Charles Price, "MIPS IV Instruction Set", MIPS Technologies, Inc.,
Revision 3.2, September, 1995, Table A-38 "CPU Instruction Encoding
- MIPS II Architecture", p. A-178
[2] same, Section A.2.5.1 "Coprocessor Load and Store", p. A-12
[3] "MIPS R10000 Microprocessor User's Manual", Version 2.0, MIPS
Technologies, Inc., January 29, 1997, Section 14.25 "CP0
Instructions", Subsection "Branch on Coprocessor 0", p. 285
[4] "MIPS32 Architecture For Programmers, Volume II: The MIPS32
Instruction Set", MIPS Technologies, Inc., Document Number:
MD00086, Revision 1.00, June 9, 2003, Table A-9 "MIPS32 COP0
Encoding of rs Field", p. 242
[5] same
[6] Joe Heinrich, "MIPS R4000 Microprocessor User's Manual", Second
Edition, MIPS Technologies, Inc., April 1, 1994, Figure A-2 "R4000
Opcode Bit Encoding", p. A-182
[8] "Vr5432 64-bit MIPS RISC Microprocessor User's Manual, Volume 1",
NEC Electronics Inc., Document No. U13751EU5V0UM00, May 2000,
Section 1.2.3 "CPU Instruction Set Overview", p. 9
[9] "Vr5432 64-bit MIPS RISC Microprocessor User's Manual, Volume 2",
NEC Electronics Inc., Document No. U13751EU5V0UM00, May 2000,
Section 19.2 "Multimedia Instruction Format", p. 681
[10] Charles Price, "MIPS IV Instruction Set", MIPS Technologies, Inc.,
Revision 3.2, September, 1995, Section A 8.3.4 "Coprocessor 3 -
COP3 and CP3 load/store", p. A-176
[11] same, Table A-39 "CPU Instruction Encoding - MIPS III
Architecture", p. A-179
[12] "MIPS32 Architecture For Programmers, Volume II: The MIPS32
Instruction Set", MIPS Technologies, Inc., Document Number:
MD00086, Revision 1.00, August 29, 2002, Table A-2 "MIPS32 Encoding
of the Opcode Field", p. 241
opcodes/
* mips-opc.c (mips_builtin_opcodes): Update exclusion list for
"ldc2", "ldc3", "lwc0", "lwc2", "lwc3", "sdc2", "sdc3", "swc0",
"swc2", "swc3", "cfc0", "ctc0", "bc2f", "bc2fl", "bc2t",
"bc2tl", "cfc2", "ctc2", "dmfc2", "dmtc2", "mfc2", "mtc2",
"bc3f", "bc3fl", "bc3t", "bc3tl", "cfc3", "ctc3", "mfc3",
"mtc3", "bc0f", "bc0fl", "bc0t", "bc0tl", "rfe", "c2", "c3",
"cop2", and "cop3" entries.
gas/
* testsuite/gas/mips/mips32@isa-override-1.d: Update for LDC3
instruction removal.
* testsuite/gas/mips/mips32r2@isa-override-1.d: Likewise.
---
gas/testsuite/gas/mips/mips32@isa-override-1.d | 47 ++++++++++
gas/testsuite/gas/mips/mips32r2@isa-override-1.d | 2
opcodes/mips-opc.c | 102 +++++++++++------------
3 files changed, 98 insertions(+), 53 deletions(-)
Index: binutils-gdb/gas/testsuite/gas/mips/mips32@isa-override-1.d
===================================================================
--- binutils-gdb.orig/gas/testsuite/gas/mips/mips32@isa-override-1.d
+++ binutils-gdb/gas/testsuite/gas/mips/mips32@isa-override-1.d
@@ -2,4 +2,49 @@
#name: MIPS ISA override code generation
#as: -32
#source: isa-override-1.s
-#dump: mips2@isa-override-1.d
+
+.*: +file format .*mips.*
+
+Disassembly of section \.text:
+[0-9a-f]+ <[^>]*> 8c820000 lw v0,0\(a0\)
+[0-9a-f]+ <[^>]*> 8c830004 lw v1,4\(a0\)
+[0-9a-f]+ <[^>]*> 3c0189ab lui at,0x89ab
+[0-9a-f]+ <[^>]*> 00411025 or v0,v0,at
+[0-9a-f]+ <[^>]*> d4820000 ldc1 \$f2,0\(a0\)
+[0-9a-f]+ <[^>]*> 3c013ff0 lui at,0x3ff0
+[0-9a-f]+ <[^>]*> 44811800 mtc1 at,\$f3
+[0-9a-f]+ <[^>]*> 3c0189ab lui at,0x89ab
+[0-9a-f]+ <[^>]*> 44811000 mtc1 at,\$f2
+[0-9a-f]+ <[^>]*> dc820000 0xdc820000
+[0-9a-f]+ <[^>]*> 340189ab li at,0x89ab
+[0-9a-f]+ <[^>]*> 00010c38 0x10c38
+[0-9a-f]+ <[^>]*> 00411025 or v0,v0,at
+[0-9a-f]+ <[^>]*> 3c029000 lui v0,0x9000
+[0-9a-f]+ <[^>]*> 00021438 0x21438
+[0-9a-f]+ <[^>]*> 34428000 ori v0,v0,0x8000
+[0-9a-f]+ <[^>]*> 00021438 0x21438
+[0-9a-f]+ <[^>]*> d4820000 ldc1 \$f2,0\(a0\)
+[0-9a-f]+ <[^>]*> 3c013ff0 lui at,0x3ff0
+[0-9a-f]+ <[^>]*> 00010c38 0x10c38
+[0-9a-f]+ <[^>]*> 342189ab ori at,at,0x89ab
+[0-9a-f]+ <[^>]*> 00010c38 0x10c38
+[0-9a-f]+ <[^>]*> 44a11000 0x44a11000
+[0-9a-f]+ <[^>]*> 8c820000 lw v0,0\(a0\)
+[0-9a-f]+ <[^>]*> 8c830004 lw v1,4\(a0\)
+[0-9a-f]+ <[^>]*> 3c0189ab lui at,0x89ab
+[0-9a-f]+ <[^>]*> 00411025 or v0,v0,at
+[0-9a-f]+ <[^>]*> d4820000 ldc1 \$f2,0\(a0\)
+[0-9a-f]+ <[^>]*> 3c013ff0 lui at,0x3ff0
+[0-9a-f]+ <[^>]*> 44811800 mtc1 at,\$f3
+[0-9a-f]+ <[^>]*> 3c0189ab lui at,0x89ab
+[0-9a-f]+ <[^>]*> 44811000 mtc1 at,\$f2
+[0-9a-f]+ <[^>]*> 8c820000 lw v0,0\(a0\)
+[0-9a-f]+ <[^>]*> 8c830004 lw v1,4\(a0\)
+[0-9a-f]+ <[^>]*> 3c0189ab lui at,0x89ab
+[0-9a-f]+ <[^>]*> 00411025 or v0,v0,at
+[0-9a-f]+ <[^>]*> d4820000 ldc1 \$f2,0\(a0\)
+[0-9a-f]+ <[^>]*> 3c013ff0 lui at,0x3ff0
+[0-9a-f]+ <[^>]*> 44811800 mtc1 at,\$f3
+[0-9a-f]+ <[^>]*> 3c0189ab lui at,0x89ab
+[0-9a-f]+ <[^>]*> 44811000 mtc1 at,\$f2
+ \.\.\.
Index: binutils-gdb/gas/testsuite/gas/mips/mips32r2@isa-override-1.d
===================================================================
--- binutils-gdb.orig/gas/testsuite/gas/mips/mips32r2@isa-override-1.d
+++ binutils-gdb/gas/testsuite/gas/mips/mips32r2@isa-override-1.d
@@ -15,7 +15,7 @@
[0-9a-f]+ <[^>]*> 44811000 mtc1 at,\$f2
[0-9a-f]+ <[^>]*> 3c013ff0 lui at,0x3ff0
[0-9a-f]+ <[^>]*> 44e11000 mthc1 at,\$f2
-[0-9a-f]+ <[^>]*> dc820000 ldc3 \$2,0\(a0\)
+[0-9a-f]+ <[^>]*> dc820000 0xdc820000
[0-9a-f]+ <[^>]*> 340189ab li at,0x89ab
[0-9a-f]+ <[^>]*> 00010c38 0x10c38
[0-9a-f]+ <[^>]*> 00411025 or v0,v0,at
Index: binutils-gdb/opcodes/mips-opc.c
===================================================================
--- binutils-gdb.orig/opcodes/mips-opc.c
+++ binutils-gdb/opcodes/mips-opc.c
@@ -1276,10 +1276,10 @@ const struct mips_opcode mips_builtin_op
{"l.d", "T,o(b)", 0xd4000000, 0xfc000000, WR_1|RD_3|CLD|FP_D, 0, I2, 0, SF }, /* ldc1 */
{"l.d", "T,A(b)", 0, (int) M_L_DAB, INSN_MACRO, INSN2_M_FP_D, I1, 0, 0 },
{"ldc2", "E,+:(d)", 0x49c00000, 0xffe00000, RD_3|WR_C2|CLD, 0, I37, 0, 0 },
-{"ldc2", "E,o(b)", 0xd8000000, 0xfc000000, RD_3|WR_CC|CLD, 0, I2, 0, IOCT|IOCTP|IOCT2|EE|I37 },
-{"ldc2", "E,A(b)", 0, (int) M_LDC2_AB, INSN_MACRO, 0, I2, 0, IOCT|IOCTP|IOCT2|EE },
-{"ldc3", "E,o(b)", 0xdc000000, 0xfc000000, RD_3|WR_CC|CLD, 0, I2, 0, IOCT|IOCTP|IOCT2|EE },
-{"ldc3", "E,A(b)", 0, (int) M_LDC3_AB, INSN_MACRO, 0, I2, 0, IOCT|IOCTP|IOCT2|EE },
+{"ldc2", "E,o(b)", 0xd8000000, 0xfc000000, RD_3|WR_CC|CLD, 0, I2, 0, N54|IOCT|IOCTP|IOCT2|EE|I37 },
+{"ldc2", "E,A(b)", 0, (int) M_LDC2_AB, INSN_MACRO, 0, I2, 0, N54|IOCT|IOCTP|IOCT2|EE },
+{"ldc3", "E,o(b)", 0xdc000000, 0xfc000000, RD_3|WR_CC|CLD, 0, I2, 0, I3_32|EE },
+{"ldc3", "E,A(b)", 0, (int) M_LDC3_AB, INSN_MACRO, 0, I2, 0, I3_32|EE },
{"ldl", "t,o(b)", 0x68000000, 0xfc000000, WR_1|RD_3|LM, 0, I3, 0, I69 },
{"ldl", "t,A(b)", 0, (int) M_LDL_AB, INSN_MACRO, 0, I3, 0, I69 },
{"ldr", "t,o(b)", 0x6c000000, 0xfc000000, WR_1|RD_3|LM, 0, I3, 0, I69 },
@@ -1314,8 +1314,8 @@ const struct mips_opcode mips_builtin_op
{"lw", "t,o(b)", 0x8c000000, 0xfc000000, WR_1|RD_3|LM, 0, I1, 0, 0 },
{"lw", "s,-a(+R)", 0xec080000, 0xfc180000, WR_1|LM, RD_pc, I37, 0, 0 },
{"lw", "t,A(b)", 0, (int) M_LW_AB, INSN_MACRO, 0, I1, 0, 0 },
-{"lwc0", "E,o(b)", 0xc0000000, 0xfc000000, RD_3|WR_CC|CLD, 0, I1, 0, IOCT|IOCTP|IOCT2|I37 },
-{"lwc0", "E,A(b)", 0, (int) M_LWC0_AB, INSN_MACRO, 0, I1, 0, IOCT|IOCTP|IOCT2|I37 },
+{"lwc0", "E,o(b)", 0xc0000000, 0xfc000000, RD_3|WR_CC|CLD, 0, I1, 0, I2 },
+{"lwc0", "E,A(b)", 0, (int) M_LWC0_AB, INSN_MACRO, 0, I1, 0, I2 },
{"lwc1", "T,o(b)", 0xc4000000, 0xfc000000, WR_1|RD_3|CLD|FP_S, 0, I1, 0, 0 },
{"lwc1", "E,o(b)", 0xc4000000, 0xfc000000, WR_1|RD_3|CLD|FP_S, 0, I1, 0, 0 },
{"lwc1", "T,A(b)", 0, (int) M_LWC1_AB, INSN_MACRO, INSN2_M_FP_S, I1, 0, 0 },
@@ -1323,10 +1323,10 @@ const struct mips_opcode mips_builtin_op
{"l.s", "T,o(b)", 0xc4000000, 0xfc000000, WR_1|RD_3|CLD|FP_S, 0, I1, 0, 0 }, /* lwc1 */
{"l.s", "T,A(b)", 0, (int) M_LWC1_AB, INSN_MACRO, INSN2_M_FP_S, I1, 0, 0 },
{"lwc2", "E,+:(d)", 0x49400000, 0xffe00000, RD_3|WR_C2|CLD, 0, I37, 0, 0 },
-{"lwc2", "E,o(b)", 0xc8000000, 0xfc000000, RD_3|WR_CC|CLD, 0, I1, 0, IOCT|IOCTP|IOCT2|EE|I37 },
-{"lwc2", "E,A(b)", 0, (int) M_LWC2_AB, INSN_MACRO, 0, I1, 0, IOCT|IOCTP|IOCT2|EE },
-{"lwc3", "E,o(b)", 0xcc000000, 0xfc000000, RD_3|WR_CC|CLD, 0, I1, 0, IOCT|IOCTP|IOCT2|EE|I37 },
-{"lwc3", "E,A(b)", 0, (int) M_LWC3_AB, INSN_MACRO, 0, I1, 0, IOCT|IOCTP|IOCT2|EE|I37 },
+{"lwc2", "E,o(b)", 0xc8000000, 0xfc000000, RD_3|WR_CC|CLD, 0, I1, 0, N54|IOCT|IOCTP|IOCT2|EE|I37 },
+{"lwc2", "E,A(b)", 0, (int) M_LWC2_AB, INSN_MACRO, 0, I1, 0, N54|IOCT|IOCTP|IOCT2|EE },
+{"lwc3", "E,o(b)", 0xcc000000, 0xfc000000, RD_3|WR_CC|CLD, 0, I1, 0, I3_32|EE },
+{"lwc3", "E,A(b)", 0, (int) M_LWC3_AB, INSN_MACRO, 0, I1, 0, I3_32|EE },
{"lwl", "t,o(b)", 0x88000000, 0xfc000000, WR_1|RD_3|LM, 0, I1, 0, I37 },
{"lwl", "t,A(b)", 0, (int) M_LWL_AB, INSN_MACRO, 0, I1, 0, I37 },
{"lcache", "t,o(b)", 0x88000000, 0xfc000000, WR_1|RD_3|LM, 0, I2, 0, I37 }, /* same */
@@ -1854,10 +1854,10 @@ const struct mips_opcode mips_builtin_op
{"sdc1", "T,A(b)", 0, (int) M_SDC1_AB, INSN_MACRO, INSN2_M_FP_D, I2, 0, SF },
{"sdc1", "E,A(b)", 0, (int) M_SDC1_AB, INSN_MACRO, INSN2_M_FP_D, I2, 0, SF },
{"sdc2", "E,+:(d)", 0x49e00000, 0xffe00000, RD_3|RD_C2|SM, 0, I37, 0, 0 },
-{"sdc2", "E,o(b)", 0xf8000000, 0xfc000000, RD_3|RD_C2|SM, 0, I2, 0, IOCT|IOCTP|IOCT2|EE|I37 },
-{"sdc2", "E,A(b)", 0, (int) M_SDC2_AB, INSN_MACRO, 0, I2, 0, IOCT|IOCTP|IOCT2|EE },
-{"sdc3", "E,o(b)", 0xfc000000, 0xfc000000, RD_3|RD_C3|SM, 0, I2, 0, IOCT|IOCTP|IOCT2|EE },
-{"sdc3", "E,A(b)", 0, (int) M_SDC3_AB, INSN_MACRO, 0, I2, 0, IOCT|IOCTP|IOCT2|EE },
+{"sdc2", "E,o(b)", 0xf8000000, 0xfc000000, RD_3|RD_C2|SM, 0, I2, 0, N54|IOCT|IOCTP|IOCT2|EE|I37 },
+{"sdc2", "E,A(b)", 0, (int) M_SDC2_AB, INSN_MACRO, 0, I2, 0, N54|IOCT|IOCTP|IOCT2|EE },
+{"sdc3", "E,o(b)", 0xfc000000, 0xfc000000, RD_3|RD_C3|SM, 0, I2, 0, I3_32|EE },
+{"sdc3", "E,A(b)", 0, (int) M_SDC3_AB, INSN_MACRO, 0, I2, 0, I3_32|EE },
{"s.d", "T,o(b)", 0xf4000000, 0xfc000000, RD_1|RD_3|SM|FP_D, 0, I2, 0, SF },
{"s.d", "T,A(b)", 0, (int) M_S_DAB, INSN_MACRO, INSN2_M_FP_D, I1, 0, 0 },
{"sdl", "t,o(b)", 0xb0000000, 0xfc000000, RD_1|RD_3|SM, 0, I3, 0, I69 },
@@ -1980,8 +1980,8 @@ const struct mips_opcode mips_builtin_op
{"swapw", "t,b", 0x70000014, 0xfc00ffff, MOD_1|RD_2|LM|SM, 0, XLR, 0, 0 },
{"swapwu", "t,b", 0x70000015, 0xfc00ffff, MOD_1|RD_2|LM|SM, 0, XLR, 0, 0 },
{"swapd", "t,b", 0x70000016, 0xfc00ffff, MOD_1|RD_2|LM|SM, 0, XLR, 0, 0 },
-{"swc0", "E,o(b)", 0xe0000000, 0xfc000000, RD_3|RD_C0|SM, 0, I1, 0, IOCT|IOCTP|IOCT2|I37 },
-{"swc0", "E,A(b)", 0, (int) M_SWC0_AB, INSN_MACRO, 0, I1, 0, IOCT|IOCTP|IOCT2|I37 },
+{"swc0", "E,o(b)", 0xe0000000, 0xfc000000, RD_3|RD_C0|SM, 0, I1, 0, I2 },
+{"swc0", "E,A(b)", 0, (int) M_SWC0_AB, INSN_MACRO, 0, I1, 0, I2 },
{"swc1", "T,o(b)", 0xe4000000, 0xfc000000, RD_1|RD_3|SM|FP_S, 0, I1, 0, 0 },
{"swc1", "E,o(b)", 0xe4000000, 0xfc000000, RD_1|RD_3|SM|FP_S, 0, I1, 0, 0 },
{"swc1", "T,A(b)", 0, (int) M_SWC1_AB, INSN_MACRO, INSN2_M_FP_S, I1, 0, 0 },
@@ -1989,10 +1989,10 @@ const struct mips_opcode mips_builtin_op
{"s.s", "T,o(b)", 0xe4000000, 0xfc000000, RD_1|RD_3|SM|FP_S, 0, I1, 0, 0 }, /* swc1 */
{"s.s", "T,A(b)", 0, (int) M_SWC1_AB, INSN_MACRO, INSN2_M_FP_S, I1, 0, 0 },
{"swc2", "E,+:(d)", 0x49600000, 0xffe00000, RD_3|RD_C2|SM, 0, I37, 0, 0 },
-{"swc2", "E,o(b)", 0xe8000000, 0xfc000000, RD_3|RD_C2|SM, 0, I1, 0, IOCT|IOCTP|IOCT2|EE|I37 },
-{"swc2", "E,A(b)", 0, (int) M_SWC2_AB, INSN_MACRO, 0, I1, 0, IOCT|IOCTP|IOCT2|EE },
-{"swc3", "E,o(b)", 0xec000000, 0xfc000000, RD_3|RD_C3|SM, 0, I1, 0, IOCT|IOCTP|IOCT2|EE|I37 },
-{"swc3", "E,A(b)", 0, (int) M_SWC3_AB, INSN_MACRO, 0, I1, 0, IOCT|IOCTP|IOCT2|EE|I37 },
+{"swc2", "E,o(b)", 0xe8000000, 0xfc000000, RD_3|RD_C2|SM, 0, I1, 0, N54|IOCT|IOCTP|IOCT2|EE|I37 },
+{"swc2", "E,A(b)", 0, (int) M_SWC2_AB, INSN_MACRO, 0, I1, 0, N54|IOCT|IOCTP|IOCT2|EE },
+{"swc3", "E,o(b)", 0xec000000, 0xfc000000, RD_3|RD_C3|SM, 0, I1, 0, I3_32|EE },
+{"swc3", "E,A(b)", 0, (int) M_SWC3_AB, INSN_MACRO, 0, I1, 0, I3_32|EE },
{"swl", "t,o(b)", 0xa8000000, 0xfc000000, RD_1|RD_3|SM, 0, I1, 0, I37 },
{"swl", "t,A(b)", 0, (int) M_SWL_AB, INSN_MACRO, 0, I1, 0, I37 },
{"scache", "t,o(b)", 0xa8000000, 0xfc000000, RD_1|RD_3, 0, I2, 0, I37 }, /* same */
@@ -2106,41 +2106,41 @@ const struct mips_opcode mips_builtin_op
/* Coprocessor 0 move instructions cfc0 and ctc0 conflict with the
mfhc0 and mthc0 XPA instructions, so they have been placed here
to allow the XPA instructions to take precedence. */
-{"cfc0", "t,g", 0x40400000, 0xffe007ff, WR_1|RD_C0|LC, 0, I1, 0, IOCT|IOCTP|IOCT2 },
-{"ctc0", "t,g", 0x40c00000, 0xffe007ff, RD_1|WR_CC|CM, 0, I1, 0, IOCT|IOCTP|IOCT2 },
+{"cfc0", "t,g", 0x40400000, 0xffe007ff, WR_1|RD_C0|LC, 0, I1, 0, I32 },
+{"ctc0", "t,g", 0x40c00000, 0xffe007ff, RD_1|WR_CC|CM, 0, I1, 0, I32 },
/* Coprocessor 2 move/branch operations overlap with VR5400 .ob format
instructions so they are here for the latters to take precedence. */
{"bc2eqz", "E,p", 0x49200000, 0xffe00000, RD_C2|CBD, 0, I37, 0, 0 },
-{"bc2f", "p", 0x49000000, 0xffff0000, RD_CC|CBD, 0, I1, 0, IOCT|IOCTP|IOCT2|I37 },
+{"bc2f", "p", 0x49000000, 0xffff0000, RD_CC|CBD, 0, I1, 0, N54|IOCT|IOCTP|IOCT2|I37 },
{"bc2f", "N,p", 0x49000000, 0xffe30000, RD_CC|CBD, 0, I32, 0, IOCT|IOCTP|IOCT2|I37 },
-{"bc2fl", "p", 0x49020000, 0xffff0000, RD_CC|CBL, 0, I2|T3, 0, IOCT|IOCTP|IOCT2|I37 },
+{"bc2fl", "p", 0x49020000, 0xffff0000, RD_CC|CBL, 0, I2|T3, 0, N54|IOCT|IOCTP|IOCT2|I37 },
{"bc2fl", "N,p", 0x49020000, 0xffe30000, RD_CC|CBL, 0, I32, 0, IOCT|IOCTP|IOCT2|I37 },
{"bc2nez", "E,p", 0x49a00000, 0xffe00000, RD_C2|CBD, 0, I37, 0, 0 },
-{"bc2t", "p", 0x49010000, 0xffff0000, RD_CC|CBD, 0, I1, 0, IOCT|IOCTP|IOCT2|I37 },
+{"bc2t", "p", 0x49010000, 0xffff0000, RD_CC|CBD, 0, I1, 0, N54|IOCT|IOCTP|IOCT2|I37 },
{"bc2t", "N,p", 0x49010000, 0xffe30000, RD_CC|CBD, 0, I32, 0, IOCT|IOCTP|IOCT2|I37 },
-{"bc2tl", "p", 0x49030000, 0xffff0000, RD_CC|CBL, 0, I2|T3, 0, IOCT|IOCTP|IOCT2|I37 },
+{"bc2tl", "p", 0x49030000, 0xffff0000, RD_CC|CBL, 0, I2|T3, 0, N54|IOCT|IOCTP|IOCT2|I37 },
{"bc2tl", "N,p", 0x49030000, 0xffe30000, RD_CC|CBL, 0, I32, 0, IOCT|IOCTP|IOCT2|I37 },
-{"cfc2", "t,g", 0x48400000, 0xffe007ff, WR_1|RD_C2|LC, 0, I1, 0, IOCT|IOCTP|IOCT2|EE },
+{"cfc2", "t,g", 0x48400000, 0xffe007ff, WR_1|RD_C2|LC, 0, I1, 0, N54|IOCT|IOCTP|IOCT2|EE },
{"cfc2", "t,+9", 0x48400000, 0xffe007ff, WR_1|RD_C2|LC, 0, EE, 0, 0 },
{"cfc2.i", "t,+9", 0x48400001, 0xffe007ff, WR_1|RD_C2|LC, 0, EE, 0, 0 },
{"cfc2.ni", "t,+9", 0x48400000, 0xffe007ff, WR_1|RD_C2|LC, 0, EE, 0, 0 },
-{"ctc2", "t,g", 0x48c00000, 0xffe007ff, RD_1|WR_CC|CM, 0, I1, 0, IOCT|IOCTP|IOCT2|EE },
+{"ctc2", "t,g", 0x48c00000, 0xffe007ff, RD_1|WR_CC|CM, 0, I1, 0, N54|IOCT|IOCTP|IOCT2|EE },
{"ctc2", "t,+9", 0x48c00000, 0xffe007ff, RD_1|WR_CC|CM, 0, EE, 0, 0 },
{"ctc2.i", "t,+9", 0x48c00001, 0xffe007ff, RD_1|WR_CC|CM, 0, EE, 0, 0 },
{"ctc2.ni", "t,+9", 0x48c00000, 0xffe007ff, RD_1|WR_CC|CM, 0, EE, 0, 0 },
{"dmfc2", "t,i", 0x48200000, 0xffe00000, WR_1|RD_C2|LC, 0, IOCT, 0, 0 },
-{"dmfc2", "t,G", 0x48200000, 0xffe007ff, WR_1|RD_C2|LC, 0, I3, 0, IOCT|IOCTP|IOCT2|EE },
+{"dmfc2", "t,G", 0x48200000, 0xffe007ff, WR_1|RD_C2|LC, 0, I3, 0, N54|IOCT|IOCTP|IOCT2|EE },
{"dmfc2", "t,G,H", 0x48200000, 0xffe007f8, WR_1|RD_C2|LC, 0, I64, 0, IOCT|IOCTP|IOCT2 },
{"dmtc2", "t,i", 0x48a00000, 0xffe00000, RD_1|WR_C2|WR_CC|CM, 0, IOCT, 0, 0 },
-{"dmtc2", "t,G", 0x48a00000, 0xffe007ff, RD_1|WR_C2|WR_CC|CM, 0, I3, 0, IOCT|IOCTP|IOCT2|EE },
+{"dmtc2", "t,G", 0x48a00000, 0xffe007ff, RD_1|WR_C2|WR_CC|CM, 0, I3, 0, N54|IOCT|IOCTP|IOCT2|EE },
{"dmtc2", "t,G,H", 0x48a00000, 0xffe007f8, RD_1|WR_C2|WR_CC|CM, 0, I64, 0, IOCT|IOCTP|IOCT2 },
-{"mfc2", "t,G", 0x48000000, 0xffe007ff, WR_1|RD_C2|LC, 0, I1, 0, IOCT|IOCTP|IOCT2|EE },
+{"mfc2", "t,G", 0x48000000, 0xffe007ff, WR_1|RD_C2|LC, 0, I1, 0, N54|IOCT|IOCTP|IOCT2|EE },
{"mfc2", "t,G,H", 0x48000000, 0xffe007f8, WR_1|RD_C2|LC, 0, I32, 0, IOCT|IOCTP|IOCT2 },
{"mfhc2", "t,G", 0x48600000, 0xffe007ff, WR_1|RD_C2|LC, 0, I33, 0, IOCT|IOCTP|IOCT2 },
{"mfhc2", "t,G,H", 0x48600000, 0xffe007f8, WR_1|RD_C2|LC, 0, I33, 0, IOCT|IOCTP|IOCT2 },
{"mfhc2", "t,i", 0x48600000, 0xffe00000, WR_1|RD_C2|LC, 0, I33, 0, IOCT|IOCTP|IOCT2 },
-{"mtc2", "t,G", 0x48800000, 0xffe007ff, RD_1|WR_C2|WR_CC|CM, 0, I1, 0, IOCT|IOCTP|IOCT2|EE },
+{"mtc2", "t,G", 0x48800000, 0xffe007ff, RD_1|WR_C2|WR_CC|CM, 0, I1, 0, N54|IOCT|IOCTP|IOCT2|EE },
{"mtc2", "t,G,H", 0x48800000, 0xffe007f8, RD_1|WR_C2|WR_CC|CM, 0, I32, 0, IOCT|IOCTP|IOCT2 },
{"mthc2", "t,G", 0x48e00000, 0xffe007ff, RD_1|WR_C2|WR_CC|CM, 0, I33, 0, IOCT|IOCTP|IOCT2 },
{"mthc2", "t,G,H", 0x48e00000, 0xffe007f8, RD_1|WR_C2|WR_CC|CM, 0, I33, 0, IOCT|IOCTP|IOCT2 },
@@ -2153,16 +2153,16 @@ const struct mips_opcode mips_builtin_op
{"qmtc2.ni", "t,+6", 0x48a00000, 0xffe007ff, RD_1|WR_C2, 0, EE, 0, 0 },
/* Coprocessor 3 move/branch operations overlap with MIPS IV COP1X
instructions, so they are here for the latters to take precedence. */
-{"bc3f", "p", 0x4d000000, 0xffff0000, RD_CC|CBD, 0, I1, 0, IOCT|IOCTP|IOCT2|EE|I37 },
-{"bc3fl", "p", 0x4d020000, 0xffff0000, RD_CC|CBL, 0, I2|T3, 0, IOCT|IOCTP|IOCT2|EE|I37 },
-{"bc3t", "p", 0x4d010000, 0xffff0000, RD_CC|CBD, 0, I1, 0, IOCT|IOCTP|IOCT2|EE|I37 },
-{"bc3tl", "p", 0x4d030000, 0xffff0000, RD_CC|CBL, 0, I2|T3, 0, IOCT|IOCTP|IOCT2|EE|I37 },
-{"cfc3", "t,g", 0x4c400000, 0xffe007ff, WR_1|RD_C3|LC, 0, I1, 0, IOCT|IOCTP|IOCT2|EE|I37 },
-{"ctc3", "t,g", 0x4cc00000, 0xffe007ff, RD_1|WR_CC|CM, 0, I1, 0, IOCT|IOCTP|IOCT2|EE|I37 },
-{"mfc3", "t,G", 0x4c000000, 0xffe007ff, WR_1|RD_C3|LC, 0, I1, 0, IOCT|IOCTP|IOCT2|EE|I37 },
-{"mfc3", "t,G,H", 0x4c000000, 0xffe007f8, WR_1|RD_C3|LC, 0, I32, 0, IOCT|IOCTP|IOCT2|EE|I37 },
-{"mtc3", "t,G", 0x4c800000, 0xffe007ff, RD_1|WR_C3|WR_CC|CM, 0, I1, 0, IOCT|IOCTP|IOCT2|EE|I37 },
-{"mtc3", "t,G,H", 0x4c800000, 0xffe007f8, RD_1|WR_C3|WR_CC|CM, 0, I32, 0, IOCT|IOCTP|IOCT2|EE|I37 },
+{"bc3f", "p", 0x4d000000, 0xffff0000, RD_CC|CBD, 0, I1, 0, I3_33|EE },
+{"bc3fl", "p", 0x4d020000, 0xffff0000, RD_CC|CBL, 0, I2|T3, 0, I3_33|EE },
+{"bc3t", "p", 0x4d010000, 0xffff0000, RD_CC|CBD, 0, I1, 0, I3_33|EE },
+{"bc3tl", "p", 0x4d030000, 0xffff0000, RD_CC|CBL, 0, I2|T3, 0, I3_33|EE },
+{"cfc3", "t,g", 0x4c400000, 0xffe007ff, WR_1|RD_C3|LC, 0, I1, 0, I3_33|EE },
+{"ctc3", "t,g", 0x4cc00000, 0xffe007ff, RD_1|WR_CC|CM, 0, I1, 0, I3_33|EE },
+{"mfc3", "t,G", 0x4c000000, 0xffe007ff, WR_1|RD_C3|LC, 0, I1, 0, I3_33|EE },
+{"mfc3", "t,G,H", 0x4c000000, 0xffe007f8, WR_1|RD_C3|LC, 0, I32, 0, I3_33|EE },
+{"mtc3", "t,G", 0x4c800000, 0xffe007ff, RD_1|WR_C3|WR_CC|CM, 0, I1, 0, I3_33|EE },
+{"mtc3", "t,G,H", 0x4c800000, 0xffe007f8, RD_1|WR_C3|WR_CC|CM, 0, I32, 0, I3_33|EE },
/* Conflicts with the 4650's "mul" instruction. Nobody's using the
4010 any more, so move this insn out of the way. If the object
@@ -2450,10 +2450,10 @@ const struct mips_opcode mips_builtin_op
{"dpsqx_s.w.ph", "7,s,t", 0x7c000670, 0xfc00e7ff, RD_2|RD_3|MOD_a, 0, 0, D33, 0 },
{"dpsqx_sa.w.ph", "7,s,t", 0x7c0006f0, 0xfc00e7ff, RD_2|RD_3|MOD_a, 0, 0, D33, 0 },
/* Move bc0* after mftr and mttr to avoid opcode collision. */
-{"bc0f", "p", 0x41000000, 0xffff0000, RD_CC|CBD, 0, I1, 0, IOCT|IOCTP|IOCT2|I37 },
-{"bc0fl", "p", 0x41020000, 0xffff0000, RD_CC|CBL, 0, I2|T3, 0, IOCT|IOCTP|IOCT2|I37 },
-{"bc0t", "p", 0x41010000, 0xffff0000, RD_CC|CBD, 0, I1, 0, IOCT|IOCTP|IOCT2|I37 },
-{"bc0tl", "p", 0x41030000, 0xffff0000, RD_CC|CBL, 0, I2|T3, 0, IOCT|IOCTP|IOCT2|I37 },
+{"bc0f", "p", 0x41000000, 0xffff0000, RD_CC|CBD, 0, I1, 0, I4_32 },
+{"bc0fl", "p", 0x41020000, 0xffff0000, RD_CC|CBL, 0, I2|T3, 0, I4_32 },
+{"bc0t", "p", 0x41010000, 0xffff0000, RD_CC|CBD, 0, I1, 0, I4_32 },
+{"bc0tl", "p", 0x41030000, 0xffff0000, RD_CC|CBL, 0, I2|T3, 0, I4_32 },
/* ST Microelectronics Loongson-2E and -2F. */
{"mult.g", "d,s,t", 0x7c000018, 0xfc0007ff, WR_1|RD_2|RD_3, 0, IL2E, 0, 0 },
{"mult.g", "d,s,t", 0x70000010, 0xfc0007ff, WR_1|RD_2|RD_3, 0, IL2F, 0, 0 },
@@ -3396,7 +3396,7 @@ const struct mips_opcode mips_builtin_op
{"ginvt", "s,+\\", 0x7c0000bd, 0xfc1ffcff, RD_1, 0, 0, GINV, 0 },
/* RFE conflicts with the new Virt spec instruction tlbgp. */
-{"rfe", "", 0x42000010, 0xffffffff, 0, 0, I1|T3, 0, 0 },
+{"rfe", "", 0x42000010, 0xffffffff, 0, 0, I1|T3, 0, I3_32 },
/* No hazard protection on coprocessor instructions--they shouldn't
change the state of the processor and if they do it's up to the
@@ -3404,12 +3404,12 @@ const struct mips_opcode mips_builtin_op
disassembler recognizes more specific versions first. */
{"c0", "C", 0x42000000, 0xfe000000, CP, 0, I1, 0, IOCT|IOCTP|IOCT2 },
{"c1", "C", 0x46000000, 0xfe000000, FP_S, 0, I1, 0, 0 },
-{"c2", "C", 0x4a000000, 0xfe000000, CP, 0, I1, 0, IOCT|IOCTP|IOCT2 },
-{"c3", "C", 0x4e000000, 0xfe000000, CP, 0, I1, 0, IOCT|IOCTP|IOCT2 },
+{"c2", "C", 0x4a000000, 0xfe000000, CP, 0, I1, 0, N54|IOCT|IOCTP|IOCT2 },
+{"c3", "C", 0x4e000000, 0xfe000000, CP, 0, I1, 0, I3_33 },
{"cop0", "C", 0, (int) M_COP0, INSN_MACRO, 0, I1, 0, IOCT|IOCTP|IOCT2 },
{"cop1", "C", 0, (int) M_COP1, INSN_MACRO, INSN2_M_FP_S, I1, 0, 0 },
-{"cop2", "C", 0, (int) M_COP2, INSN_MACRO, 0, I1, 0, IOCT|IOCTP|IOCT2 },
-{"cop3", "C", 0, (int) M_COP3, INSN_MACRO, 0, I1, 0, IOCT|IOCTP|IOCT2 },
+{"cop2", "C", 0, (int) M_COP2, INSN_MACRO, 0, I1, 0, N54|IOCT|IOCTP|IOCT2 },
+{"cop3", "C", 0, (int) M_COP3, INSN_MACRO, 0, I1, 0, I3_33 },
};
#define MIPS_NUM_OPCODES \
^ permalink raw reply [flat|nested] 19+ messages in thread
* [committed 15/18] MIPS/GAS/testsuite: Run coprocessor tests across all ISAs
2021-05-29 1:36 [committed 00/18] MIPS coprocessor opcodes handling fixes Maciej W. Rozycki
` (13 preceding siblings ...)
2021-05-29 1:37 ` [committed 14/18] MIPS/opcodes: Accurately record coprocessor opcode CPU/ISA membership Maciej W. Rozycki
@ 2021-05-29 1:37 ` Maciej W. Rozycki
2021-05-29 1:38 ` [committed 16/18] MIPS/GAS/testsuite: Run RFE test " Maciej W. Rozycki
` (2 subsequent siblings)
17 siblings, 0 replies; 19+ messages in thread
From: Maciej W. Rozycki @ 2021-05-29 1:37 UTC (permalink / raw)
To: binutils
[-- Attachment #1: Type: text/plain, Size: 10582 bytes --]
Verify that individual coprocessor instructions are not only accepted
where supported, but rejected where they are not as well.
gas/
* testsuite/gas/mips/mips.exp: Run coprocessor tests across all
ISAs.
* testsuite/gas/mips/cp0b.d: Update for ISA exclusions.
* testsuite/gas/mips/cp0bl.d: Update for ISA exclusions.
* testsuite/gas/mips/cp0c.d: Update for ISA exclusions.
* testsuite/gas/mips/cp0m.d: Update for ISA exclusions.
* testsuite/gas/mips/cp3.d: Update for ISA exclusions.
* testsuite/gas/mips/cp3b.d: Update for ISA exclusions.
* testsuite/gas/mips/cp3bl.d: Update for ISA exclusions.
* testsuite/gas/mips/cp3m.d: Update for ISA exclusions.
* testsuite/gas/mips/cp3d.d: Update for ISA exclusions.
* testsuite/gas/mips/mips1@cp0b.d: New test.
* testsuite/gas/mips/mips2@cp0b.d: New test.
* testsuite/gas/mips/mips3@cp0b.d: New test.
* testsuite/gas/mips/r3000@cp0b.d: New test.
* testsuite/gas/mips/r3900@cp0b.d: New test.
* testsuite/gas/mips/r4000@cp0b.d: New test.
* testsuite/gas/mips/r5900@cp0b.d: New test.
* testsuite/gas/mips/mips2@cp0bl.d: New test.
* testsuite/gas/mips/mips3@cp0bl.d: New test.
* testsuite/gas/mips/r3900@cp0bl.d: New test.
* testsuite/gas/mips/r4000@cp0bl.d: New test.
* testsuite/gas/mips/r5900@cp0bl.d: New test.
* testsuite/gas/mips/mips1@cp0c.d: New test.
* testsuite/gas/mips/mips2@cp0c.d: New test.
* testsuite/gas/mips/mips3@cp0c.d: New test.
* testsuite/gas/mips/mips4@cp0c.d: New test.
* testsuite/gas/mips/mips5@cp0c.d: New test.
* testsuite/gas/mips/r3000@cp0c.d: New test.
* testsuite/gas/mips/r3900@cp0c.d: New test.
* testsuite/gas/mips/r4000@cp0c.d: New test.
* testsuite/gas/mips/vr5400@cp0c.d: New test.
* testsuite/gas/mips/r5900@cp0c.d: New test.
* testsuite/gas/mips/mips1@cp0m.d: New test.
* testsuite/gas/mips/r3000@cp0m.d: New test.
* testsuite/gas/mips/octeon@cp2.d: New test.
* testsuite/gas/mips/mipsr6@cp2b.d: New test.
* testsuite/gas/mips/vr5400@cp2b.d: New test.
* testsuite/gas/mips/octeon@cp2b.d: New test.
* testsuite/gas/mips/mips1@cp2bl.d: New test.
* testsuite/gas/mips/mipsr6@cp2bl.d: New test.
* testsuite/gas/mips/r3000@cp2bl.d: New test.
* testsuite/gas/mips/vr5400@cp2bl.d: New test.
* testsuite/gas/mips/octeon@cp2bl.d: New test.
* testsuite/gas/mips/vr5400@cp2m.d: New test.
* testsuite/gas/mips/r5900@cp2m.d: New test.
* testsuite/gas/mips/octeon@cp2m.d: New test.
* testsuite/gas/mips/mips1@cp2d.d: New test.
* testsuite/gas/mips/r3000@cp2d.d: New test.
* testsuite/gas/mips/r3900@cp2d.d: New test.
* testsuite/gas/mips/vr5400@cp2d.d: New test.
* testsuite/gas/mips/r5900@cp2d.d: New test.
* testsuite/gas/mips/octeon@cp2d.d: New test.
* testsuite/gas/mips/mips1@cp2-64.d: New test.
* testsuite/gas/mips/mips2@cp2-64.d: New test.
* testsuite/gas/mips/mips32@cp2-64.d: New test.
* testsuite/gas/mips/mips32r2@cp2-64.d: New test.
* testsuite/gas/mips/mips32r3@cp2-64.d: New test.
* testsuite/gas/mips/mips32r5@cp2-64.d: New test.
* testsuite/gas/mips/mips32r6@cp2-64.d: New test.
* testsuite/gas/mips/r3000@cp2-64.d: New test.
* testsuite/gas/mips/r3900@cp2-64.d: New test.
* testsuite/gas/mips/interaptiv-mr2@cp2-64.d: New test.
* testsuite/gas/mips/mips1@cp3.d: New test.
* testsuite/gas/mips/mips2@cp3.d: New test.
* testsuite/gas/mips/mips32@cp3.d: New test.
* testsuite/gas/mips/r3000@cp3.d: New test.
* testsuite/gas/mips/r3900@cp3.d: New test.
* testsuite/gas/mips/mips1@cp3b.d: New test.
* testsuite/gas/mips/mips2@cp3b.d: New test.
* testsuite/gas/mips/mips32@cp3b.d: New test.
* testsuite/gas/mips/r3000@cp3b.d: New test.
* testsuite/gas/mips/r3900@cp3b.d: New test.
* testsuite/gas/mips/mips2@cp3bl.d: New test.
* testsuite/gas/mips/mips32@cp3bl.d: New test.
* testsuite/gas/mips/r3900@cp3bl.d: New test.
* testsuite/gas/mips/mips1@cp3m.d: New test.
* testsuite/gas/mips/mips2@cp3m.d: New test.
* testsuite/gas/mips/r3000@cp3m.d: New test.
* testsuite/gas/mips/r3900@cp3m.d: New test.
* testsuite/gas/mips/mips2@cp3d.d: New test.
* testsuite/gas/mips/cp0b.l: New test stderr output.
* testsuite/gas/mips/cp0bl.l: New test stderr output.
* testsuite/gas/mips/cp0c.l: New test stderr output.
* testsuite/gas/mips/cp0m.l: New test stderr output.
* testsuite/gas/mips/cp2.l: New test stderr output.
* testsuite/gas/mips/cp2-64.l: New test stderr output.
* testsuite/gas/mips/cp2b.l: New test stderr output.
* testsuite/gas/mips/cp2bl.l: New test stderr output.
* testsuite/gas/mips/cp2m.l: New test stderr output.
* testsuite/gas/mips/cp2d.l: New test stderr output.
* testsuite/gas/mips/cp3.l: New test stderr output.
* testsuite/gas/mips/cp3b.l: New test stderr output.
* testsuite/gas/mips/cp3bl.l: New test stderr output.
* testsuite/gas/mips/cp3m.l: New test stderr output.
* testsuite/gas/mips/cp3d.l: New test stderr output.
---
gas/testsuite/gas/mips/cp0b.d | 11 --
gas/testsuite/gas/mips/cp0b.l | 3
gas/testsuite/gas/mips/cp0bl.d | 10 -
gas/testsuite/gas/mips/cp0bl.l | 3
gas/testsuite/gas/mips/cp0c.d | 70 ------------
gas/testsuite/gas/mips/cp0c.l | 65 +++++++++++
gas/testsuite/gas/mips/cp0m.d | 70 ------------
gas/testsuite/gas/mips/cp0m.l | 65 +++++++++++
gas/testsuite/gas/mips/cp2-64.l | 65 +++++++++++
gas/testsuite/gas/mips/cp2.l | 129 +++++++++++++++++++++++
gas/testsuite/gas/mips/cp2b.l | 3
gas/testsuite/gas/mips/cp2bl.l | 3
gas/testsuite/gas/mips/cp2d.l | 65 +++++++++++
gas/testsuite/gas/mips/cp2m.l | 65 +++++++++++
gas/testsuite/gas/mips/cp3.d | 134 ------------------------
gas/testsuite/gas/mips/cp3.l | 129 +++++++++++++++++++++++
gas/testsuite/gas/mips/cp3b.d | 10 -
gas/testsuite/gas/mips/cp3b.l | 3
gas/testsuite/gas/mips/cp3bl.d | 10 -
gas/testsuite/gas/mips/cp3bl.l | 3
gas/testsuite/gas/mips/cp3d.d | 70 ------------
gas/testsuite/gas/mips/cp3d.l | 65 +++++++++++
gas/testsuite/gas/mips/cp3m.d | 70 ------------
gas/testsuite/gas/mips/cp3m.l | 65 +++++++++++
gas/testsuite/gas/mips/interaptiv-mr2@cp2-64.d | 5
gas/testsuite/gas/mips/mips.exp | 42 +++----
gas/testsuite/gas/mips/mips1@cp0b.d | 13 ++
gas/testsuite/gas/mips/mips1@cp0c.d | 73 +++++++++++++
gas/testsuite/gas/mips/mips1@cp0m.d | 73 +++++++++++++
gas/testsuite/gas/mips/mips1@cp2-64.d | 5
gas/testsuite/gas/mips/mips1@cp2bl.d | 5
gas/testsuite/gas/mips/mips1@cp2d.d | 5
gas/testsuite/gas/mips/mips1@cp3.d | 137 +++++++++++++++++++++++++
gas/testsuite/gas/mips/mips1@cp3b.d | 13 ++
gas/testsuite/gas/mips/mips1@cp3m.d | 73 +++++++++++++
gas/testsuite/gas/mips/mips2@cp0b.d | 5
gas/testsuite/gas/mips/mips2@cp0bl.d | 13 ++
gas/testsuite/gas/mips/mips2@cp0c.d | 5
gas/testsuite/gas/mips/mips2@cp2-64.d | 5
gas/testsuite/gas/mips/mips2@cp3.d | 5
gas/testsuite/gas/mips/mips2@cp3b.d | 5
gas/testsuite/gas/mips/mips2@cp3bl.d | 13 ++
gas/testsuite/gas/mips/mips2@cp3d.d | 73 +++++++++++++
gas/testsuite/gas/mips/mips2@cp3m.d | 5
gas/testsuite/gas/mips/mips32@cp2-64.d | 5
gas/testsuite/gas/mips/mips32@cp3.d | 5
gas/testsuite/gas/mips/mips32@cp3b.d | 5
gas/testsuite/gas/mips/mips32@cp3bl.d | 5
gas/testsuite/gas/mips/mips32r2@cp2-64.d | 5
gas/testsuite/gas/mips/mips32r3@cp2-64.d | 5
gas/testsuite/gas/mips/mips32r5@cp2-64.d | 5
gas/testsuite/gas/mips/mips32r6@cp2-64.d | 5
gas/testsuite/gas/mips/mips3@cp0b.d | 5
gas/testsuite/gas/mips/mips3@cp0bl.d | 5
gas/testsuite/gas/mips/mips3@cp0c.d | 5
gas/testsuite/gas/mips/mips4@cp0c.d | 5
gas/testsuite/gas/mips/mips5@cp0c.d | 5
gas/testsuite/gas/mips/mipsr6@cp2b.d | 5
gas/testsuite/gas/mips/mipsr6@cp2bl.d | 5
gas/testsuite/gas/mips/octeon@cp2.d | 5
gas/testsuite/gas/mips/octeon@cp2b.d | 5
gas/testsuite/gas/mips/octeon@cp2bl.d | 5
gas/testsuite/gas/mips/octeon@cp2d.d | 5
gas/testsuite/gas/mips/octeon@cp2m.d | 5
gas/testsuite/gas/mips/r3000@cp0b.d | 5
gas/testsuite/gas/mips/r3000@cp0c.d | 5
gas/testsuite/gas/mips/r3000@cp0m.d | 5
gas/testsuite/gas/mips/r3000@cp2-64.d | 5
gas/testsuite/gas/mips/r3000@cp2bl.d | 5
gas/testsuite/gas/mips/r3000@cp2d.d | 5
gas/testsuite/gas/mips/r3000@cp3.d | 5
gas/testsuite/gas/mips/r3000@cp3b.d | 5
gas/testsuite/gas/mips/r3000@cp3m.d | 5
gas/testsuite/gas/mips/r3900@cp0b.d | 5
gas/testsuite/gas/mips/r3900@cp0bl.d | 5
gas/testsuite/gas/mips/r3900@cp0c.d | 5
gas/testsuite/gas/mips/r3900@cp2-64.d | 5
gas/testsuite/gas/mips/r3900@cp2d.d | 5
gas/testsuite/gas/mips/r3900@cp3.d | 5
gas/testsuite/gas/mips/r3900@cp3b.d | 5
gas/testsuite/gas/mips/r3900@cp3bl.d | 5
gas/testsuite/gas/mips/r3900@cp3m.d | 5
gas/testsuite/gas/mips/r4000@cp0b.d | 5
gas/testsuite/gas/mips/r4000@cp0bl.d | 5
gas/testsuite/gas/mips/r4000@cp0c.d | 5
gas/testsuite/gas/mips/r5900@cp0b.d | 5
gas/testsuite/gas/mips/r5900@cp0bl.d | 5
gas/testsuite/gas/mips/r5900@cp0c.d | 5
gas/testsuite/gas/mips/r5900@cp2d.d | 5
gas/testsuite/gas/mips/r5900@cp2m.d | 5
gas/testsuite/gas/mips/vr5400@cp0c.d | 5
gas/testsuite/gas/mips/vr5400@cp2b.d | 5
gas/testsuite/gas/mips/vr5400@cp2bl.d | 5
gas/testsuite/gas/mips/vr5400@cp2d.d | 5
gas/testsuite/gas/mips/vr5400@cp2m.d | 5
95 files changed, 1547 insertions(+), 467 deletions(-)
binutils-mips-opcodes-copx-test-update.diff
[Patch attached compressed due to its size.]
[-- Attachment #2: Type: application/octet-stream, Size: 6744 bytes --]
^ permalink raw reply [flat|nested] 19+ messages in thread
* [committed 16/18] MIPS/GAS/testsuite: Run RFE test across all ISAs
2021-05-29 1:36 [committed 00/18] MIPS coprocessor opcodes handling fixes Maciej W. Rozycki
` (14 preceding siblings ...)
2021-05-29 1:37 ` [committed 15/18] MIPS/GAS/testsuite: Run coprocessor tests across all ISAs Maciej W. Rozycki
@ 2021-05-29 1:38 ` Maciej W. Rozycki
2021-05-29 1:38 ` [committed 17/18] MIPS/GAS/testsuite: Add C0, C1, C2, C3 opcode tests Maciej W. Rozycki
2021-05-29 1:38 ` [committed 18/18] MIPS/opcodes: Reorder legacy COP0, COP2, COP3 opcode instructions Maciej W. Rozycki
17 siblings, 0 replies; 19+ messages in thread
From: Maciej W. Rozycki @ 2021-05-29 1:38 UTC (permalink / raw)
To: binutils
Verify that the RFE instruction is not only accepted where supported,
but rejected where it is not as well.
gas/
* testsuite/gas/mips/mips.exp: Run RFE test across all ISAs.
* testsuite/gas/mips/rfe.d: Update for ISA exclusions.
* testsuite/gas/mips/mips1@rfe.d: New test.
* testsuite/gas/mips/mips2@rfe.d: New test.
* testsuite/gas/mips/r3000@rfe.d: New test.
* testsuite/gas/mips/r3900@rfe.d: New test.
* testsuite/gas/mips/rfe.l: New test stderr output.
---
gas/testsuite/gas/mips/mips.exp | 2 +-
gas/testsuite/gas/mips/mips1@rfe.d | 10 ++++++++++
gas/testsuite/gas/mips/mips2@rfe.d | 5 +++++
gas/testsuite/gas/mips/r3000@rfe.d | 5 +++++
gas/testsuite/gas/mips/r3900@rfe.d | 5 +++++
gas/testsuite/gas/mips/rfe.d | 7 +------
gas/testsuite/gas/mips/rfe.l | 2 ++
7 files changed, 29 insertions(+), 7 deletions(-)
binutils-mips-opcodes-rfe-test-update.diff
Index: binutils-gdb/gas/testsuite/gas/mips/mips.exp
===================================================================
--- binutils-gdb.orig/gas/testsuite/gas/mips/mips.exp
+++ binutils-gdb/gas/testsuite/gas/mips/mips.exp
@@ -1343,7 +1343,7 @@ if { [istarget mips*-*-vxworks*] } {
!micromips]
run_dump_test_arches "rfe" [mips_arch_list_matching mips1 \
- !mips3 !mips32 !micromips]
+ !micromips]
run_dump_test "cp1-names-numeric"
run_dump_test "cp1-names-r3000"
Index: binutils-gdb/gas/testsuite/gas/mips/mips1@rfe.d
===================================================================
--- /dev/null
+++ binutils-gdb/gas/testsuite/gas/mips/mips1@rfe.d
@@ -0,0 +1,10 @@
+#objdump: -d --prefix-addresses --show-raw-insn
+#name: MIPS RFE instruction
+#as: -32
+#source: rfe.s
+
+.*: +file format .*mips.*
+
+Disassembly of section \.text:
+[0-9a-f]+ <[^>]*> 42000010 rfe
+ \.\.\.
Index: binutils-gdb/gas/testsuite/gas/mips/mips2@rfe.d
===================================================================
--- /dev/null
+++ binutils-gdb/gas/testsuite/gas/mips/mips2@rfe.d
@@ -0,0 +1,5 @@
+#objdump: -d --prefix-addresses --show-raw-insn
+#name: MIPS RFE instruction
+#as: -32
+#source: rfe.s
+#dump: mips1@rfe.d
Index: binutils-gdb/gas/testsuite/gas/mips/r3000@rfe.d
===================================================================
--- /dev/null
+++ binutils-gdb/gas/testsuite/gas/mips/r3000@rfe.d
@@ -0,0 +1,5 @@
+#objdump: -d --prefix-addresses --show-raw-insn
+#name: MIPS RFE instruction
+#as: -32
+#source: rfe.s
+#dump: mips1@rfe.d
Index: binutils-gdb/gas/testsuite/gas/mips/r3900@rfe.d
===================================================================
--- /dev/null
+++ binutils-gdb/gas/testsuite/gas/mips/r3900@rfe.d
@@ -0,0 +1,5 @@
+#objdump: -d --prefix-addresses --show-raw-insn
+#name: MIPS RFE instruction
+#as: -32
+#source: rfe.s
+#dump: mips1@rfe.d
Index: binutils-gdb/gas/testsuite/gas/mips/rfe.d
===================================================================
--- binutils-gdb.orig/gas/testsuite/gas/mips/rfe.d
+++ binutils-gdb/gas/testsuite/gas/mips/rfe.d
@@ -1,9 +1,4 @@
#objdump: -d --prefix-addresses --show-raw-insn
#name: MIPS RFE instruction
#as: -32
-
-.*: +file format .*mips.*
-
-Disassembly of section \.text:
-[0-9a-f]+ <[^>]*> 42000010 rfe
- \.\.\.
+#error_output: rfe.l
Index: binutils-gdb/gas/testsuite/gas/mips/rfe.l
===================================================================
--- /dev/null
+++ binutils-gdb/gas/testsuite/gas/mips/rfe.l
@@ -0,0 +1,2 @@
+.*: Assembler messages:
+.*:4: Error: opcode not supported on this processor: .* \(.*\) `rfe'
^ permalink raw reply [flat|nested] 19+ messages in thread
* [committed 17/18] MIPS/GAS/testsuite: Add C0, C1, C2, C3 opcode tests
2021-05-29 1:36 [committed 00/18] MIPS coprocessor opcodes handling fixes Maciej W. Rozycki
` (15 preceding siblings ...)
2021-05-29 1:38 ` [committed 16/18] MIPS/GAS/testsuite: Run RFE test " Maciej W. Rozycki
@ 2021-05-29 1:38 ` Maciej W. Rozycki
2021-05-29 1:38 ` [committed 18/18] MIPS/opcodes: Reorder legacy COP0, COP2, COP3 opcode instructions Maciej W. Rozycki
17 siblings, 0 replies; 19+ messages in thread
From: Maciej W. Rozycki @ 2021-05-29 1:38 UTC (permalink / raw)
To: binutils
[-- Attachment #1: Type: text/plain, Size: 6095 bytes --]
Add tests for the generic C0, C1, C2, C3 coprocessor instructions.
gas/
* testsuite/gas/mips/c0.d: New test.
* testsuite/gas/mips/mips1@c0.d: New test.
* testsuite/gas/mips/mips2@c0.d: New test.
* testsuite/gas/mips/mips3@c0.d: New test.
* testsuite/gas/mips/mips4@c0.d: New test.
* testsuite/gas/mips/mips5@c0.d: New test.
* testsuite/gas/mips/mips32@c0.d: New test.
* testsuite/gas/mips/mips64@c0.d: New test.
* testsuite/gas/mips/r3000@c0.d: New test.
* testsuite/gas/mips/r3900@c0.d: New test.
* testsuite/gas/mips/r4000@c0.d: New test.
* testsuite/gas/mips/vr5400@c0.d: New test.
* testsuite/gas/mips/r5900@c0.d: New test.
* testsuite/gas/mips/sb1@c0.d: New test.
* testsuite/gas/mips/interaptiv-mr2@c0.d: New test.
* testsuite/gas/mips/octeon@c0.d: New test.
* testsuite/gas/mips/xlr@c0.d: New test.
* testsuite/gas/mips/c1.d: New test.
* testsuite/gas/mips/mips1@c1.d: New test.
* testsuite/gas/mips/mips2@c1.d: New test.
* testsuite/gas/mips/mips3@c1.d: New test.
* testsuite/gas/mips/mips4@c1.d: New test.
* testsuite/gas/mips/mips5@c1.d: New test.
* testsuite/gas/mips/mips32@c1.d: New test.
* testsuite/gas/mips/mips64@c1.d: New test.
* testsuite/gas/mips/mipsr6@c1.d: New test.
* testsuite/gas/mips/r3000@c1.d: New test.
* testsuite/gas/mips/r3900@c1.d: New test.
* testsuite/gas/mips/r4000@c1.d: New test.
* testsuite/gas/mips/vr5400@c1.d: New test.
* testsuite/gas/mips/r5900@c1.d: New test.
* testsuite/gas/mips/sb1@c1.d: New test.
* testsuite/gas/mips/interaptiv-mr2@c1.d: New test.
* testsuite/gas/mips/octeon@c1.d: New test.
* testsuite/gas/mips/xlr@c1.d: New test.
* testsuite/gas/mips/c2.d: New test.
* testsuite/gas/mips/vr5400@c2.d: New test.
* testsuite/gas/mips/r5900@c2.d: New test.
* testsuite/gas/mips/octeon@c2.d: New test.
* testsuite/gas/mips/c3.d: New test.
* testsuite/gas/mips/mips1@c3.d: New test.
* testsuite/gas/mips/mips2@c3.d: New test.
* testsuite/gas/mips/mips32@c3.d: New test.
* testsuite/gas/mips/r3000@c3.d: New test.
* testsuite/gas/mips/r3900@c3.d: New test.
* testsuite/gas/mips/c0.l: New test stderr output.
* testsuite/gas/mips/c2.l: New test stderr output.
* testsuite/gas/mips/c3.l: New test stderr output.
* testsuite/gas/mips/c0.s: New test source.
* testsuite/gas/mips/c1.s: New test source.
* testsuite/gas/mips/c2.s: New test source.
* testsuite/gas/mips/c3.s: New test source.
* testsuite/gas/mips/mips.exp: Run the new tests.
---
gas/testsuite/gas/mips/c0.d | 264 ++++++++++++++++++++++++++++
gas/testsuite/gas/mips/c0.l | 257 ++++++++++++++++++++++++++++
gas/testsuite/gas/mips/c0.s | 265 ++++++++++++++++++++++++++++
gas/testsuite/gas/mips/c1.d | 266 +++++++++++++++++++++++++++++
gas/testsuite/gas/mips/c1.s | 265 ++++++++++++++++++++++++++++
gas/testsuite/gas/mips/c2.d | 264 ++++++++++++++++++++++++++++
gas/testsuite/gas/mips/c2.l | 257 ++++++++++++++++++++++++++++
gas/testsuite/gas/mips/c2.s | 265 ++++++++++++++++++++++++++++
gas/testsuite/gas/mips/c3.d | 4
gas/testsuite/gas/mips/c3.l | 257 ++++++++++++++++++++++++++++
gas/testsuite/gas/mips/c3.s | 265 ++++++++++++++++++++++++++++
gas/testsuite/gas/mips/interaptiv-mr2@c0.d | 265 ++++++++++++++++++++++++++++
gas/testsuite/gas/mips/interaptiv-mr2@c1.d | 5
gas/testsuite/gas/mips/mips.exp | 9
gas/testsuite/gas/mips/mips1@c0.d | 265 ++++++++++++++++++++++++++++
gas/testsuite/gas/mips/mips1@c1.d | 265 ++++++++++++++++++++++++++++
gas/testsuite/gas/mips/mips1@c3.d | 265 ++++++++++++++++++++++++++++
gas/testsuite/gas/mips/mips2@c0.d | 5
gas/testsuite/gas/mips/mips2@c1.d | 265 ++++++++++++++++++++++++++++
gas/testsuite/gas/mips/mips2@c3.d | 5
gas/testsuite/gas/mips/mips32@c0.d | 265 ++++++++++++++++++++++++++++
gas/testsuite/gas/mips/mips32@c1.d | 265 ++++++++++++++++++++++++++++
gas/testsuite/gas/mips/mips32@c3.d | 5
gas/testsuite/gas/mips/mips3@c0.d | 265 ++++++++++++++++++++++++++++
gas/testsuite/gas/mips/mips3@c1.d | 265 ++++++++++++++++++++++++++++
gas/testsuite/gas/mips/mips4@c0.d | 5
gas/testsuite/gas/mips/mips4@c1.d | 265 ++++++++++++++++++++++++++++
gas/testsuite/gas/mips/mips5@c0.d | 5
gas/testsuite/gas/mips/mips5@c1.d | 265 ++++++++++++++++++++++++++++
gas/testsuite/gas/mips/mips64@c0.d | 5
gas/testsuite/gas/mips/mips64@c1.d | 265 ++++++++++++++++++++++++++++
gas/testsuite/gas/mips/mipsr6@c1.d | 266 +++++++++++++++++++++++++++++
gas/testsuite/gas/mips/octeon@c0.d | 5
gas/testsuite/gas/mips/octeon@c1.d | 265 ++++++++++++++++++++++++++++
gas/testsuite/gas/mips/octeon@c2.d | 5
gas/testsuite/gas/mips/r3000@c0.d | 5
gas/testsuite/gas/mips/r3000@c1.d | 5
gas/testsuite/gas/mips/r3000@c3.d | 5
gas/testsuite/gas/mips/r3900@c0.d | 265 ++++++++++++++++++++++++++++
gas/testsuite/gas/mips/r3900@c1.d | 5
gas/testsuite/gas/mips/r3900@c3.d | 5
gas/testsuite/gas/mips/r4000@c0.d | 5
gas/testsuite/gas/mips/r4000@c1.d | 5
gas/testsuite/gas/mips/r5900@c0.d | 265 ++++++++++++++++++++++++++++
gas/testsuite/gas/mips/r5900@c1.d | 265 ++++++++++++++++++++++++++++
gas/testsuite/gas/mips/r5900@c2.d | 265 ++++++++++++++++++++++++++++
gas/testsuite/gas/mips/sb1@c0.d | 5
gas/testsuite/gas/mips/sb1@c1.d | 5
gas/testsuite/gas/mips/vr5400@c0.d | 5
gas/testsuite/gas/mips/vr5400@c1.d | 5
gas/testsuite/gas/mips/vr5400@c2.d | 5
gas/testsuite/gas/mips/xlr@c0.d | 5
gas/testsuite/gas/mips/xlr@c1.d | 5
53 files changed, 7524 insertions(+)
binutils-mips-cp-test.diff
[Patch attached compressed due to its size.]
[-- Attachment #2: Type: application/octet-stream, Size: 11044 bytes --]
^ permalink raw reply [flat|nested] 19+ messages in thread
* [committed 18/18] MIPS/opcodes: Reorder legacy COP0, COP2, COP3 opcode instructions
2021-05-29 1:36 [committed 00/18] MIPS coprocessor opcodes handling fixes Maciej W. Rozycki
` (16 preceding siblings ...)
2021-05-29 1:38 ` [committed 17/18] MIPS/GAS/testsuite: Add C0, C1, C2, C3 opcode tests Maciej W. Rozycki
@ 2021-05-29 1:38 ` Maciej W. Rozycki
17 siblings, 0 replies; 19+ messages in thread
From: Maciej W. Rozycki @ 2021-05-29 1:38 UTC (permalink / raw)
To: binutils
Group legacy instructions using the COP0, COP2, COP3 opcodes together
and by their coprocessor number, and move them towards the end of the
opcode table. No functional change.
With the addition of explicit ISA exclusions this is maybe not strictly
necessary anymore as the individual legacy instructions are not supposed
to match ISA levels or CPU implementations that have discarded them or
replaced with a new instruction each, but let's not have them scattered
randomly across blocks of unrelated instruction sets where someone chose
to put them previously. Perhaps they could be put back in alphabetical
order in the main instruction block, but let's leave it for another
occasion.
opcodes/
* mips-opc.c (mips_builtin_opcodes): Reorder legacy COP0, COP2,
COP3 opcode instructions.
---
opcodes/mips-opc.c | 134 ++++++++++++++++++++++++++---------------------------
1 file changed, 68 insertions(+), 66 deletions(-)
binutils-mips-opcodes-copx-legacy.diff
Index: binutils-gdb/opcodes/mips-opc.c
===================================================================
--- binutils-gdb.orig/opcodes/mips-opc.c
+++ binutils-gdb/opcodes/mips-opc.c
@@ -2103,67 +2103,6 @@ const struct mips_opcode mips_builtin_op
{"zcb", "(b)", 0x7000071f, 0xfc1fffff, RD_1|SM, 0, IOCT2, 0, 0 },
{"zcbt", "(b)", 0x7000075f, 0xfc1fffff, RD_1|SM, 0, IOCT2, 0, 0 },
-/* Coprocessor 0 move instructions cfc0 and ctc0 conflict with the
- mfhc0 and mthc0 XPA instructions, so they have been placed here
- to allow the XPA instructions to take precedence. */
-{"cfc0", "t,g", 0x40400000, 0xffe007ff, WR_1|RD_C0|LC, 0, I1, 0, I32 },
-{"ctc0", "t,g", 0x40c00000, 0xffe007ff, RD_1|WR_CC|CM, 0, I1, 0, I32 },
-
-/* Coprocessor 2 move/branch operations overlap with VR5400 .ob format
- instructions so they are here for the latters to take precedence. */
-{"bc2eqz", "E,p", 0x49200000, 0xffe00000, RD_C2|CBD, 0, I37, 0, 0 },
-{"bc2f", "p", 0x49000000, 0xffff0000, RD_CC|CBD, 0, I1, 0, N54|IOCT|IOCTP|IOCT2|I37 },
-{"bc2f", "N,p", 0x49000000, 0xffe30000, RD_CC|CBD, 0, I32, 0, IOCT|IOCTP|IOCT2|I37 },
-{"bc2fl", "p", 0x49020000, 0xffff0000, RD_CC|CBL, 0, I2|T3, 0, N54|IOCT|IOCTP|IOCT2|I37 },
-{"bc2fl", "N,p", 0x49020000, 0xffe30000, RD_CC|CBL, 0, I32, 0, IOCT|IOCTP|IOCT2|I37 },
-{"bc2nez", "E,p", 0x49a00000, 0xffe00000, RD_C2|CBD, 0, I37, 0, 0 },
-{"bc2t", "p", 0x49010000, 0xffff0000, RD_CC|CBD, 0, I1, 0, N54|IOCT|IOCTP|IOCT2|I37 },
-{"bc2t", "N,p", 0x49010000, 0xffe30000, RD_CC|CBD, 0, I32, 0, IOCT|IOCTP|IOCT2|I37 },
-{"bc2tl", "p", 0x49030000, 0xffff0000, RD_CC|CBL, 0, I2|T3, 0, N54|IOCT|IOCTP|IOCT2|I37 },
-{"bc2tl", "N,p", 0x49030000, 0xffe30000, RD_CC|CBL, 0, I32, 0, IOCT|IOCTP|IOCT2|I37 },
-{"cfc2", "t,g", 0x48400000, 0xffe007ff, WR_1|RD_C2|LC, 0, I1, 0, N54|IOCT|IOCTP|IOCT2|EE },
-{"cfc2", "t,+9", 0x48400000, 0xffe007ff, WR_1|RD_C2|LC, 0, EE, 0, 0 },
-{"cfc2.i", "t,+9", 0x48400001, 0xffe007ff, WR_1|RD_C2|LC, 0, EE, 0, 0 },
-{"cfc2.ni", "t,+9", 0x48400000, 0xffe007ff, WR_1|RD_C2|LC, 0, EE, 0, 0 },
-{"ctc2", "t,g", 0x48c00000, 0xffe007ff, RD_1|WR_CC|CM, 0, I1, 0, N54|IOCT|IOCTP|IOCT2|EE },
-{"ctc2", "t,+9", 0x48c00000, 0xffe007ff, RD_1|WR_CC|CM, 0, EE, 0, 0 },
-{"ctc2.i", "t,+9", 0x48c00001, 0xffe007ff, RD_1|WR_CC|CM, 0, EE, 0, 0 },
-{"ctc2.ni", "t,+9", 0x48c00000, 0xffe007ff, RD_1|WR_CC|CM, 0, EE, 0, 0 },
-{"dmfc2", "t,i", 0x48200000, 0xffe00000, WR_1|RD_C2|LC, 0, IOCT, 0, 0 },
-{"dmfc2", "t,G", 0x48200000, 0xffe007ff, WR_1|RD_C2|LC, 0, I3, 0, N54|IOCT|IOCTP|IOCT2|EE },
-{"dmfc2", "t,G,H", 0x48200000, 0xffe007f8, WR_1|RD_C2|LC, 0, I64, 0, IOCT|IOCTP|IOCT2 },
-{"dmtc2", "t,i", 0x48a00000, 0xffe00000, RD_1|WR_C2|WR_CC|CM, 0, IOCT, 0, 0 },
-{"dmtc2", "t,G", 0x48a00000, 0xffe007ff, RD_1|WR_C2|WR_CC|CM, 0, I3, 0, N54|IOCT|IOCTP|IOCT2|EE },
-{"dmtc2", "t,G,H", 0x48a00000, 0xffe007f8, RD_1|WR_C2|WR_CC|CM, 0, I64, 0, IOCT|IOCTP|IOCT2 },
-{"mfc2", "t,G", 0x48000000, 0xffe007ff, WR_1|RD_C2|LC, 0, I1, 0, N54|IOCT|IOCTP|IOCT2|EE },
-{"mfc2", "t,G,H", 0x48000000, 0xffe007f8, WR_1|RD_C2|LC, 0, I32, 0, IOCT|IOCTP|IOCT2 },
-{"mfhc2", "t,G", 0x48600000, 0xffe007ff, WR_1|RD_C2|LC, 0, I33, 0, IOCT|IOCTP|IOCT2 },
-{"mfhc2", "t,G,H", 0x48600000, 0xffe007f8, WR_1|RD_C2|LC, 0, I33, 0, IOCT|IOCTP|IOCT2 },
-{"mfhc2", "t,i", 0x48600000, 0xffe00000, WR_1|RD_C2|LC, 0, I33, 0, IOCT|IOCTP|IOCT2 },
-{"mtc2", "t,G", 0x48800000, 0xffe007ff, RD_1|WR_C2|WR_CC|CM, 0, I1, 0, N54|IOCT|IOCTP|IOCT2|EE },
-{"mtc2", "t,G,H", 0x48800000, 0xffe007f8, RD_1|WR_C2|WR_CC|CM, 0, I32, 0, IOCT|IOCTP|IOCT2 },
-{"mthc2", "t,G", 0x48e00000, 0xffe007ff, RD_1|WR_C2|WR_CC|CM, 0, I33, 0, IOCT|IOCTP|IOCT2 },
-{"mthc2", "t,G,H", 0x48e00000, 0xffe007f8, RD_1|WR_C2|WR_CC|CM, 0, I33, 0, IOCT|IOCTP|IOCT2 },
-{"mthc2", "t,i", 0x48e00000, 0xffe00000, RD_1|WR_C2|WR_CC|CM, 0, I33, 0, IOCT|IOCTP|IOCT2 },
-{"qmfc2", "t,+6", 0x48200000, 0xffe007ff, WR_1|RD_C2, 0, EE, 0, 0 },
-{"qmfc2.i", "t,+6", 0x48200001, 0xffe007ff, WR_1|RD_C2, 0, EE, 0, 0 },
-{"qmfc2.ni", "t,+6", 0x48200000, 0xffe007ff, WR_1|RD_C2, 0, EE, 0, 0 },
-{"qmtc2", "t,+6", 0x48a00000, 0xffe007ff, RD_1|WR_C2, 0, EE, 0, 0 },
-{"qmtc2.i", "t,+6", 0x48a00001, 0xffe007ff, RD_1|WR_C2, 0, EE, 0, 0 },
-{"qmtc2.ni", "t,+6", 0x48a00000, 0xffe007ff, RD_1|WR_C2, 0, EE, 0, 0 },
-/* Coprocessor 3 move/branch operations overlap with MIPS IV COP1X
- instructions, so they are here for the latters to take precedence. */
-{"bc3f", "p", 0x4d000000, 0xffff0000, RD_CC|CBD, 0, I1, 0, I3_33|EE },
-{"bc3fl", "p", 0x4d020000, 0xffff0000, RD_CC|CBL, 0, I2|T3, 0, I3_33|EE },
-{"bc3t", "p", 0x4d010000, 0xffff0000, RD_CC|CBD, 0, I1, 0, I3_33|EE },
-{"bc3tl", "p", 0x4d030000, 0xffff0000, RD_CC|CBL, 0, I2|T3, 0, I3_33|EE },
-{"cfc3", "t,g", 0x4c400000, 0xffe007ff, WR_1|RD_C3|LC, 0, I1, 0, I3_33|EE },
-{"ctc3", "t,g", 0x4cc00000, 0xffe007ff, RD_1|WR_CC|CM, 0, I1, 0, I3_33|EE },
-{"mfc3", "t,G", 0x4c000000, 0xffe007ff, WR_1|RD_C3|LC, 0, I1, 0, I3_33|EE },
-{"mfc3", "t,G,H", 0x4c000000, 0xffe007f8, WR_1|RD_C3|LC, 0, I32, 0, I3_33|EE },
-{"mtc3", "t,G", 0x4c800000, 0xffe007ff, RD_1|WR_C3|WR_CC|CM, 0, I1, 0, I3_33|EE },
-{"mtc3", "t,G,H", 0x4c800000, 0xffe007f8, RD_1|WR_C3|WR_CC|CM, 0, I32, 0, I3_33|EE },
-
/* Conflicts with the 4650's "mul" instruction. Nobody's using the
4010 any more, so move this insn out of the way. If the object
format gave us more info, we could do this right. */
@@ -2449,11 +2388,6 @@ const struct mips_opcode mips_builtin_op
{"dpaqx_sa.w.ph", "7,s,t", 0x7c0006b0, 0xfc00e7ff, RD_2|RD_3|MOD_a, 0, 0, D33, 0 },
{"dpsqx_s.w.ph", "7,s,t", 0x7c000670, 0xfc00e7ff, RD_2|RD_3|MOD_a, 0, 0, D33, 0 },
{"dpsqx_sa.w.ph", "7,s,t", 0x7c0006f0, 0xfc00e7ff, RD_2|RD_3|MOD_a, 0, 0, D33, 0 },
-/* Move bc0* after mftr and mttr to avoid opcode collision. */
-{"bc0f", "p", 0x41000000, 0xffff0000, RD_CC|CBD, 0, I1, 0, I4_32 },
-{"bc0fl", "p", 0x41020000, 0xffff0000, RD_CC|CBL, 0, I2|T3, 0, I4_32 },
-{"bc0t", "p", 0x41010000, 0xffff0000, RD_CC|CBD, 0, I1, 0, I4_32 },
-{"bc0tl", "p", 0x41030000, 0xffff0000, RD_CC|CBL, 0, I2|T3, 0, I4_32 },
/* ST Microelectronics Loongson-2E and -2F. */
{"mult.g", "d,s,t", 0x7c000018, 0xfc0007ff, WR_1|RD_2|RD_3, 0, IL2E, 0, 0 },
{"mult.g", "d,s,t", 0x70000010, 0xfc0007ff, WR_1|RD_2|RD_3, 0, IL2F, 0, 0 },
@@ -3395,9 +3329,77 @@ const struct mips_opcode mips_builtin_op
{"ginvi", "s", 0x7c00003d, 0xfc1fffff, RD_1, 0, 0, GINV, 0 },
{"ginvt", "s,+\\", 0x7c0000bd, 0xfc1ffcff, RD_1, 0, 0, GINV, 0 },
+/* Move bc0* after mftr and mttr to avoid opcode collision. */
+{"bc0f", "p", 0x41000000, 0xffff0000, RD_CC|CBD, 0, I1, 0, I4_32 },
+{"bc0fl", "p", 0x41020000, 0xffff0000, RD_CC|CBL, 0, I2|T3, 0, I4_32 },
+{"bc0t", "p", 0x41010000, 0xffff0000, RD_CC|CBD, 0, I1, 0, I4_32 },
+{"bc0tl", "p", 0x41030000, 0xffff0000, RD_CC|CBL, 0, I2|T3, 0, I4_32 },
+
+/* Coprocessor 0 move instructions cfc0 and ctc0 conflict with the
+ mfhc0 and mthc0 XPA instructions, so they have been placed here
+ to allow the XPA instructions to take precedence. */
+{"cfc0", "t,g", 0x40400000, 0xffe007ff, WR_1|RD_C0|LC, 0, I1, 0, I32 },
+{"ctc0", "t,g", 0x40c00000, 0xffe007ff, RD_1|WR_CC|CM, 0, I1, 0, I32 },
+
/* RFE conflicts with the new Virt spec instruction tlbgp. */
{"rfe", "", 0x42000010, 0xffffffff, 0, 0, I1|T3, 0, I3_32 },
+/* Coprocessor 2 move/branch operations overlap with VR5400 .ob format
+ instructions so they are here for the latters to take precedence. */
+{"bc2eqz", "E,p", 0x49200000, 0xffe00000, RD_C2|CBD, 0, I37, 0, 0 },
+{"bc2f", "p", 0x49000000, 0xffff0000, RD_CC|CBD, 0, I1, 0, N54|IOCT|IOCTP|IOCT2|I37 },
+{"bc2f", "N,p", 0x49000000, 0xffe30000, RD_CC|CBD, 0, I32, 0, IOCT|IOCTP|IOCT2|I37 },
+{"bc2fl", "p", 0x49020000, 0xffff0000, RD_CC|CBL, 0, I2|T3, 0, N54|IOCT|IOCTP|IOCT2|I37 },
+{"bc2fl", "N,p", 0x49020000, 0xffe30000, RD_CC|CBL, 0, I32, 0, IOCT|IOCTP|IOCT2|I37 },
+{"bc2nez", "E,p", 0x49a00000, 0xffe00000, RD_C2|CBD, 0, I37, 0, 0 },
+{"bc2t", "p", 0x49010000, 0xffff0000, RD_CC|CBD, 0, I1, 0, N54|IOCT|IOCTP|IOCT2|I37 },
+{"bc2t", "N,p", 0x49010000, 0xffe30000, RD_CC|CBD, 0, I32, 0, IOCT|IOCTP|IOCT2|I37 },
+{"bc2tl", "p", 0x49030000, 0xffff0000, RD_CC|CBL, 0, I2|T3, 0, N54|IOCT|IOCTP|IOCT2|I37 },
+{"bc2tl", "N,p", 0x49030000, 0xffe30000, RD_CC|CBL, 0, I32, 0, IOCT|IOCTP|IOCT2|I37 },
+{"cfc2", "t,g", 0x48400000, 0xffe007ff, WR_1|RD_C2|LC, 0, I1, 0, N54|IOCT|IOCTP|IOCT2|EE },
+{"cfc2", "t,+9", 0x48400000, 0xffe007ff, WR_1|RD_C2|LC, 0, EE, 0, 0 },
+{"cfc2.i", "t,+9", 0x48400001, 0xffe007ff, WR_1|RD_C2|LC, 0, EE, 0, 0 },
+{"cfc2.ni", "t,+9", 0x48400000, 0xffe007ff, WR_1|RD_C2|LC, 0, EE, 0, 0 },
+{"ctc2", "t,g", 0x48c00000, 0xffe007ff, RD_1|WR_CC|CM, 0, I1, 0, N54|IOCT|IOCTP|IOCT2|EE },
+{"ctc2", "t,+9", 0x48c00000, 0xffe007ff, RD_1|WR_CC|CM, 0, EE, 0, 0 },
+{"ctc2.i", "t,+9", 0x48c00001, 0xffe007ff, RD_1|WR_CC|CM, 0, EE, 0, 0 },
+{"ctc2.ni", "t,+9", 0x48c00000, 0xffe007ff, RD_1|WR_CC|CM, 0, EE, 0, 0 },
+{"dmfc2", "t,i", 0x48200000, 0xffe00000, WR_1|RD_C2|LC, 0, IOCT, 0, 0 },
+{"dmfc2", "t,G", 0x48200000, 0xffe007ff, WR_1|RD_C2|LC, 0, I3, 0, N54|IOCT|IOCTP|IOCT2|EE },
+{"dmfc2", "t,G,H", 0x48200000, 0xffe007f8, WR_1|RD_C2|LC, 0, I64, 0, IOCT|IOCTP|IOCT2 },
+{"dmtc2", "t,i", 0x48a00000, 0xffe00000, RD_1|WR_C2|WR_CC|CM, 0, IOCT, 0, 0 },
+{"dmtc2", "t,G", 0x48a00000, 0xffe007ff, RD_1|WR_C2|WR_CC|CM, 0, I3, 0, N54|IOCT|IOCTP|IOCT2|EE },
+{"dmtc2", "t,G,H", 0x48a00000, 0xffe007f8, RD_1|WR_C2|WR_CC|CM, 0, I64, 0, IOCT|IOCTP|IOCT2 },
+{"mfc2", "t,G", 0x48000000, 0xffe007ff, WR_1|RD_C2|LC, 0, I1, 0, N54|IOCT|IOCTP|IOCT2|EE },
+{"mfc2", "t,G,H", 0x48000000, 0xffe007f8, WR_1|RD_C2|LC, 0, I32, 0, IOCT|IOCTP|IOCT2 },
+{"mfhc2", "t,G", 0x48600000, 0xffe007ff, WR_1|RD_C2|LC, 0, I33, 0, IOCT|IOCTP|IOCT2 },
+{"mfhc2", "t,G,H", 0x48600000, 0xffe007f8, WR_1|RD_C2|LC, 0, I33, 0, IOCT|IOCTP|IOCT2 },
+{"mfhc2", "t,i", 0x48600000, 0xffe00000, WR_1|RD_C2|LC, 0, I33, 0, IOCT|IOCTP|IOCT2 },
+{"mtc2", "t,G", 0x48800000, 0xffe007ff, RD_1|WR_C2|WR_CC|CM, 0, I1, 0, N54|IOCT|IOCTP|IOCT2|EE },
+{"mtc2", "t,G,H", 0x48800000, 0xffe007f8, RD_1|WR_C2|WR_CC|CM, 0, I32, 0, IOCT|IOCTP|IOCT2 },
+{"mthc2", "t,G", 0x48e00000, 0xffe007ff, RD_1|WR_C2|WR_CC|CM, 0, I33, 0, IOCT|IOCTP|IOCT2 },
+{"mthc2", "t,G,H", 0x48e00000, 0xffe007f8, RD_1|WR_C2|WR_CC|CM, 0, I33, 0, IOCT|IOCTP|IOCT2 },
+{"mthc2", "t,i", 0x48e00000, 0xffe00000, RD_1|WR_C2|WR_CC|CM, 0, I33, 0, IOCT|IOCTP|IOCT2 },
+{"qmfc2", "t,+6", 0x48200000, 0xffe007ff, WR_1|RD_C2, 0, EE, 0, 0 },
+{"qmfc2.i", "t,+6", 0x48200001, 0xffe007ff, WR_1|RD_C2, 0, EE, 0, 0 },
+{"qmfc2.ni", "t,+6", 0x48200000, 0xffe007ff, WR_1|RD_C2, 0, EE, 0, 0 },
+{"qmtc2", "t,+6", 0x48a00000, 0xffe007ff, RD_1|WR_C2, 0, EE, 0, 0 },
+{"qmtc2.i", "t,+6", 0x48a00001, 0xffe007ff, RD_1|WR_C2, 0, EE, 0, 0 },
+{"qmtc2.ni", "t,+6", 0x48a00000, 0xffe007ff, RD_1|WR_C2, 0, EE, 0, 0 },
+
+/* Coprocessor 3 move/branch operations overlap with MIPS IV COP1X
+ instructions, so they are here for the latters to take precedence. */
+{"bc3f", "p", 0x4d000000, 0xffff0000, RD_CC|CBD, 0, I1, 0, I3_33|EE },
+{"bc3fl", "p", 0x4d020000, 0xffff0000, RD_CC|CBL, 0, I2|T3, 0, I3_33|EE },
+{"bc3t", "p", 0x4d010000, 0xffff0000, RD_CC|CBD, 0, I1, 0, I3_33|EE },
+{"bc3tl", "p", 0x4d030000, 0xffff0000, RD_CC|CBL, 0, I2|T3, 0, I3_33|EE },
+{"cfc3", "t,g", 0x4c400000, 0xffe007ff, WR_1|RD_C3|LC, 0, I1, 0, I3_33|EE },
+{"ctc3", "t,g", 0x4cc00000, 0xffe007ff, RD_1|WR_CC|CM, 0, I1, 0, I3_33|EE },
+{"mfc3", "t,G", 0x4c000000, 0xffe007ff, WR_1|RD_C3|LC, 0, I1, 0, I3_33|EE },
+{"mfc3", "t,G,H", 0x4c000000, 0xffe007f8, WR_1|RD_C3|LC, 0, I32, 0, I3_33|EE },
+{"mtc3", "t,G", 0x4c800000, 0xffe007ff, RD_1|WR_C3|WR_CC|CM, 0, I1, 0, I3_33|EE },
+{"mtc3", "t,G,H", 0x4c800000, 0xffe007f8, RD_1|WR_C3|WR_CC|CM, 0, I32, 0, I3_33|EE },
+
/* No hazard protection on coprocessor instructions--they shouldn't
change the state of the processor and if they do it's up to the
user to put in nops as necessary. These are at the end so that the
^ permalink raw reply [flat|nested] 19+ messages in thread
end of thread, other threads:[~2021-05-29 1:38 UTC | newest]
Thread overview: 19+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2021-05-29 1:36 [committed 00/18] MIPS coprocessor opcodes handling fixes Maciej W. Rozycki
2021-05-29 1:36 ` [committed 01/18] MIPS/GAS: Use FCSR rather than RA with CFC1/CTC1 Maciej W. Rozycki
2021-05-29 1:36 ` [committed 02/18] microMIPS/opcodes: Refer FPRs rather than FCRs with DMTC1 Maciej W. Rozycki
2021-05-29 1:36 ` [committed 03/18] MIPS/opcodes: Free up redundant `g' operand code Maciej W. Rozycki
2021-05-29 1:37 ` [committed 04/18] MIPS/binutils/testsuite: Fix XPA and Virtualization ASE cases Maciej W. Rozycki
2021-05-29 1:37 ` [committed 05/18] MIPS/opcodes: Add TX39 CP0 register names Maciej W. Rozycki
2021-05-29 1:37 ` [committed 06/18] MIPS/opcodes: Do not use CP0 register names for control registers Maciej W. Rozycki
2021-05-29 1:37 ` [committed 07/18] MIPS/GAS/testsuite: Add tests for coprocessor access instructions Maciej W. Rozycki
2021-05-29 1:37 ` [committed 08/18] MIPS/opcodes: Add legacy CP1 control register names Maciej W. Rozycki
2021-05-29 1:37 ` [committed 09/18] MIPS/opcodes: Factor out ISA matching against flags Maciej W. Rozycki
2021-05-29 1:37 ` [committed 10/18] MIPS/opcodes: Properly handle ISA exclusion Maciej W. Rozycki
2021-05-29 1:37 ` [committed 11/18] MIPS/opcodes: Disassemble the RFE instruction Maciej W. Rozycki
2021-05-29 1:37 ` [committed 12/18] MIPS/GAS/testsuite: Add tests for coprocessor branch instructions Maciej W. Rozycki
2021-05-29 1:37 ` [committed 13/18] MIPS/opcodes: Remove DMFC3 and DMTC3 instructions Maciej W. Rozycki
2021-05-29 1:37 ` [committed 14/18] MIPS/opcodes: Accurately record coprocessor opcode CPU/ISA membership Maciej W. Rozycki
2021-05-29 1:37 ` [committed 15/18] MIPS/GAS/testsuite: Run coprocessor tests across all ISAs Maciej W. Rozycki
2021-05-29 1:38 ` [committed 16/18] MIPS/GAS/testsuite: Run RFE test " Maciej W. Rozycki
2021-05-29 1:38 ` [committed 17/18] MIPS/GAS/testsuite: Add C0, C1, C2, C3 opcode tests Maciej W. Rozycki
2021-05-29 1:38 ` [committed 18/18] MIPS/opcodes: Reorder legacy COP0, COP2, COP3 opcode instructions Maciej W. Rozycki
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