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Date: Mon, 9 Jan 2023 21:59:34 +0000 (GMT)
From: "Maciej W. Rozycki" <macro@orcam.me.uk>
To: Palmer Dabbelt <palmer@dabbelt.com>
cc: jbeulich@suse.com, Andrew Waterman <andrew@sifive.com>, 
    Jim Wilson <jim.wilson.gcc@gmail.com>, nelson@rivosinc.com, 
    Nick Clifton <nickc@redhat.com>, binutils@sourceware.org
Subject: Re: [PATCH] gas/RISC-V: adjust assembler for opcode table
 re-ordering
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References: <mhng-da78c63b-1a53-4a49-8adc-e0e97b9c9259@palmer-ri-x1c9a>
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On Mon, 9 Jan 2023, Palmer Dabbelt wrote:

> > > > The similar workaround in my_getSmallExpression() actually looks
> > > > suspicious to me: I expect that it would get in the way of using equates
> > > > "shadowing" names of GPRs.
> > > > 
> > > > --- a/gas/config/tc-riscv.c
> > > > +++ b/gas/config/tc-riscv.c
> > > > @@ -3266,6 +3266,17 @@ riscv_ip (char *str, struct riscv_cl_ins
> > > >  	      continue;
> > > > 
> > > >  	    case 'a': /* 20-bit PC-relative offset.  */
> > > > +	      /* Like in my_getSmallExpression() we need to avoid emitting
> > > > +		 a stray undefined symbol if the 1st JAL entry doesn't match,
> > > > +		 but the 2nd (with 2 operands) might.  */
> > > > +	      if (oparg == insn->args)
> > > > +		{
> > > > +		  asargStart = asarg;
> > > > +		  if (reg_lookup (&asarg, RCLASS_GPR, NULL)
> > > > +		      && (*asarg == ',' || (ISSPACE (*asarg) && asarg[1] ==
> > > > ',')))
> > > > +		    break;
> > > > +		  asarg = asargStart;
> > > > +		}
> > > >  	    jump:
> > > >  	      my_getExpression (imm_expr, asarg);
> > > >  	      asarg = expr_end;
> > > 
> > > Thanks for the patch. I have tested it and confirmed it fix the problem
> > > I reported.
> > 
> > With 2.40 scheduled to be cut in less than a week, may I ask for an arch
> > maintainer's view here?
> 
> Thanks for fixing this.  I don't have any issues with what's there, but looks
> like I'm also getting some failures (glibc/multilib errno related stuff).  I'm
> trying to bisect those so I can't really get a proper test up now, I'll try to
> do so ASAP as it's really late to have stuff broken.

 I wonder why the RISC-V port needs such a hack while the MIPS one 
doesn't.

  Maciej