From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from angie.orcam.me.uk (angie.orcam.me.uk [78.133.224.34]) by sourceware.org (Postfix) with ESMTP id 5ED01384644B for ; Thu, 15 Jun 2023 03:51:36 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 5ED01384644B Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=orcam.me.uk Authentication-Results: sourceware.org; spf=none smtp.mailfrom=orcam.me.uk Received: by angie.orcam.me.uk (Postfix, from userid 500) id D7F2292009D; Thu, 15 Jun 2023 05:51:35 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by angie.orcam.me.uk (Postfix) with ESMTP id D0BD392009B; Thu, 15 Jun 2023 04:51:35 +0100 (BST) Date: Thu, 15 Jun 2023 04:51:35 +0100 (BST) From: "Maciej W. Rozycki" To: david@davidgf.es cc: binutils@sourceware.org, David Guillen Fandos Subject: Re: [PATCH v2 2/3] Add rotation instructions to MIPS Allegrex CPU In-Reply-To: <20230614000148.10989-3-david@davidgf.es> Message-ID: References: <20230614000148.10989-1-david@davidgf.es> <20230614000148.10989-3-david@davidgf.es> User-Agent: Alpine 2.21 (DEB 202 2017-01-01) MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII X-Spam-Status: No, score=-1169.4 required=5.0 tests=BAYES_00,GIT_PATCH_0,KAM_DMARC_STATUS,KAM_INFOUSMEBIZ,KAM_LAZY_DOMAIN_SECURITY,SPF_HELO_NONE,SPF_NONE,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: On Wed, 14 Jun 2023, david@davidgf.es wrote: > The Allegrex CPU supports bit rotation instructions as described in the > MIPS32 release 2 CPU (even though it is a MIPS-2 based CPU). Just a minor nit about this version. > diff --git a/gas/testsuite/gas/mips/mips.exp b/gas/testsuite/gas/mips/mips.exp > index 6dbf2e3746..f4137c5640 100644 > --- a/gas/testsuite/gas/mips/mips.exp > +++ b/gas/testsuite/gas/mips/mips.exp > @@ -517,7 +517,7 @@ mips_arch_create r3000 32 mips1 {} \ > mips_arch_create r3900 32 mips1 { gpr_ilocks } \ > { -march=r3900 -mtune=r3900 } { -mmips:3900 } \ > { mipstx39-*-* mipstx39el-*-* } > -mips_arch_create allegrex 32 mips2 { oddspreg singlefloat } \ > +mips_arch_create allegrex 32 mips2 { oddspreg ror singlefloat } \ You haven't reordered `ror' here as requested with v1. I have done this for you (and fixed the order for `singlefloat' in 1/3 too, which I missed previously), but please be more careful in the future. It helps when the reviewer doesn't have to double-check everything. I have now committed this change with said modification applied. Thank you for your contribution. Maciej