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[37.24.206.209]) by smtp.gmail.com with ESMTPSA id bp14-20020a056638440e00b0046b1e958fb0sm104671jab.174.2023.12.14.23.51.20 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 14 Dec 2023 23:51:21 -0800 (PST) Message-ID: Date: Fri, 15 Dec 2023 08:51:18 +0100 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH] x86: Remove the restriction for size of the mask register in AVX10 Content-Language: en-US To: Haochen Jiang Cc: hjl.tools@gmail.com, binutils@sourceware.org References: <20231215022359.2702206-1-haochen.jiang@intel.com> From: Jan Beulich Autocrypt: addr=jbeulich@suse.com; keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: <20231215022359.2702206-1-haochen.jiang@intel.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Spam-Status: No, score=-3026.1 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,KAM_NUMSUBJECT,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: On 15.12.2023 03:23, Haochen Jiang wrote: > Sorry for the late change near the 2.42 branch freeze but there is a revision > in AVX10 documentation, which allows 64 bit mask register instructions in > AVX10/256, the documentation comes following: > > Intel Advanced Vector Extensions 10 (Intel AVX10) Architecture Specification > https://cdrdv2.intel.com/v1/dl/getContent/784267 > The Converged Vector ISA: Intel Advanced Vector Extensions 10 Technical Paper > https://cdrdv2.intel.com/v1/dl/getContent/784343 > > This patch aims to remove the mask register size restriction on all vector size > in AVX10. > > Since mask registers size is not an issue, I also removed the testcases for them. > But I have no objection to keep them. This aspect is certainly fine. > --- a/opcodes/i386-opc.tbl > +++ b/opcodes/i386-opc.tbl > @@ -135,9 +135,6 @@ > > #define Disp8ShiftVL Disp8MemShift=DISP8_SHIFT_VL > > -#define Vsz256 Vsz=VSZ256 > -#define Vsz512 Vsz=VSZ512 Isn't it that with this and ... > @@ -996,9 +993,9 @@ pause, 0xf390, i186, NoSuf, {} > b:0:VexW0:Byte:AVX512DQ:66:AVX512VBMI, + > w:1:VexW1:Word:AVX512F::AVX512BW> > > - - d:0:VexW0::Dword::Reg32:66:Vsz256, + > - q:1:VexW1:VexW1:Qword:x64:Reg64::Vsz512> > + + d:0:VexW0::Dword::Reg32:66, + > + q:1:VexW1:VexW1:Qword:x64:Reg64:> ... this, the Vsz attribute is no longer used? If so, it wants removing altogether at the same time. Jan