From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-sender-0.a4lg.com (mail-sender.a4lg.com [153.120.152.154]) by sourceware.org (Postfix) with ESMTPS id 8A6603858285 for ; Sat, 1 Oct 2022 04:46:11 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 8A6603858285 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=irq.a4lg.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=irq.a4lg.com Received: from [127.0.0.1] (localhost [127.0.0.1]) by mail-sender-0.a4lg.com (Postfix) with ESMTPSA id 8385F300089; Sat, 1 Oct 2022 04:46:08 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=irq.a4lg.com; s=2017s01; t=1664599568; bh=iE/lDV7kOdF8xWpV/JZACiiiOV/cbEcADWN3Qb/yPeA=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: Mime-Version:Content-Transfer-Encoding; b=rKy13oT94Dytuye9551Oa8iZ+5D6IJxSOlVnb/30TdI348IbIzITO3lRKTuLqK7Jt e3Fk9IjQgDcttvjydekdgssSEGuKsbtQClY9g4pTrkvwLnqR3q03+Hk9gnLbZXCLtd XeoNf8NSMI6iJB52EcoBsu9JTWpc4pVTXvzrmWZk= From: Tsukasa OI To: Tsukasa OI , Nelson Chu , Kito Cheng , Palmer Dabbelt Cc: binutils@sourceware.org Subject: [RFC PATCH 1/1] RISC-V: Implement common register pair framework Date: Sat, 1 Oct 2022 04:45:52 +0000 Message-Id: In-Reply-To: References: Mime-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-12.1 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,GIT_PATCH_0,SPF_HELO_NONE,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: This commit implements common framework for aligned register pairs (using GPRs). This is particularly useful on following extensions: - 'Zdinx' - 'Zqinx' (once proposed but not ratified yet) - 'Zpsfoperand' (a part of 'P'-extension proposal) New operand type format is shown below: 1. 'l' (stands for "length") 2. One of the following: '1' for 32-bit data (or less), (RV32: 1 register, RV64: 1 register) '2' for 64-bit data (RV32: 2 registers, RV64: 1 register) '4' for 128-bit data (RV32: 4 registers, RV64: 2 registers) 3. One of the following: 'd' for RD 's' for RS1 't' for RS2 'r' for RS3 'u' for RS1 and RS2 (where RS1 == RS2) gas/ChangeLog: * config/tc-riscv.c (riscv_ip): Add handling for "l[124][dstru]". (validate_riscv_insn): Likewise. opcodes/ChangeLog: * riscv-dis.c (print_insn_args): Add handling for "l[124][dstru]". --- gas/config/tc-riscv.c | 72 +++++++++++++++++++++++++++++++++++++++++++ opcodes/riscv-dis.c | 31 +++++++++++++++++++ 2 files changed, 103 insertions(+) diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c index bd8f65d94fd..5e6fca3de9f 100644 --- a/gas/config/tc-riscv.c +++ b/gas/config/tc-riscv.c @@ -1251,6 +1251,30 @@ validate_riscv_insn (const struct riscv_opcode *opc, int length) case 'z': break; /* Zero immediate. */ case '[': break; /* Unused operand. */ case ']': break; /* Unused operand. */ + case 'l': /* Register pairs. */ + switch (*++oparg) + { + case '1': + case '2': + case '4': + break; + default: + goto unknown_validate_operand; + } + switch (*++oparg) + { + case 'd': USE_BITS (OP_MASK_RD, OP_SH_RD); break; + case 's': USE_BITS (OP_MASK_RS1, OP_SH_RS1); break; + case 't': USE_BITS (OP_MASK_RS2, OP_SH_RS2); break; + case 'r': USE_BITS (OP_MASK_RS3, OP_SH_RS3); break; + case 'u': /* RS1 == RS2. */ + USE_BITS (OP_MASK_RS1, OP_SH_RS1); + USE_BITS (OP_MASK_RS2, OP_SH_RS2); + break; + default: + goto unknown_validate_operand; + } + break; case '0': break; /* AMO displacement, must to zero. */ case '1': break; /* Relaxation operand. */ case 'F': /* Funct for .insn directive. */ @@ -3021,6 +3045,54 @@ riscv_ip (char *str, struct riscv_cl_insn *ip, expressionS *imm_expr, } break; + case 'l': /* Register pairs. */ + if (reg_lookup (&asarg, RCLASS_GPR, ®no)) + { + if (*asarg == ' ') + ++asarg; + + unsigned dlen; + switch (*++oparg) + { + case '1': dlen = 32; break; + case '2': dlen = 64; break; + case '4': dlen = 128; break; + default: + goto unknown_riscv_ip_operand; + } + char c = *++oparg; + + /* Check whether the register number is aligned properly. */ + if (!(xlen >= dlen || (regno % (dlen / xlen)) == 0)) + break; + + /* Now the register number is valid. Insert the number to + the corresponding field(s). */ + switch (c) + { + case 'd': + INSERT_OPERAND (RD, *ip, regno); + break; + case 's': + INSERT_OPERAND (RS1, *ip, regno); + break; + case 't': + INSERT_OPERAND (RS2, *ip, regno); + break; + case 'r': + INSERT_OPERAND (RS3, *ip, regno); + break; + case 'u': + INSERT_OPERAND (RS1, *ip, regno); + INSERT_OPERAND (RS2, *ip, regno); + break; + default: + goto unknown_riscv_ip_operand; + } + continue; + } + break; + case 'D': /* Floating point RD. */ case 'S': /* Floating point RS1. */ case 'T': /* Floating point RS2. */ diff --git a/opcodes/riscv-dis.c b/opcodes/riscv-dis.c index 6ac69490b78..85b79db606c 100644 --- a/opcodes/riscv-dis.c +++ b/opcodes/riscv-dis.c @@ -488,6 +488,37 @@ print_insn_args (const char *oparg, insn_t l, bfd_vma pc, disassemble_info *info print (info->stream, dis_style_register, "%s", riscv_gpr_names[0]); break; + case 'l': + { + unsigned dlen; + int regno; + switch (*++oparg) + { + case '1': dlen = 32; break; + case '2': dlen = 64; break; + case '4': dlen = 128; break; + default: + goto undefined_modifier; + } + switch (*++oparg) + { + case 'd': regno = rd; break; + case 's': regno = rs1; break; + case 't': regno = EXTRACT_OPERAND (RS2, l); break; + case 'r': regno = EXTRACT_OPERAND (RS3, l); break; + case 'u': regno = rs1; break; /* RS1 == RS2. */ + default: + goto undefined_modifier; + } + /* Check whether the register number is aligned properly. */ + if (xlen >= dlen || (regno % (dlen / xlen)) == 0) + print (info->stream, dis_style_register, "%s", + riscv_gpr_names[regno]); + else + print (info->stream, dis_style_text, "invalid%d", regno); + break; + } + case '>': print (info->stream, dis_style_immediate, "0x%x", (int)EXTRACT_OPERAND (SHAMT, l)); -- 2.34.1