From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from xry111.site (xry111.site [89.208.246.23]) by sourceware.org (Postfix) with ESMTPS id 6DE363857C69 for ; Thu, 30 Nov 2023 16:10:30 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 6DE363857C69 Authentication-Results: sourceware.org; dmarc=pass (p=reject dis=none) header.from=xry111.site Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=xry111.site ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 6DE363857C69 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=89.208.246.23 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1701360633; cv=none; b=k/elyAzbn2TxuteZpgZbvVLHrORVAXrVU7dGO0vRtp4QhUybkfLLaZY+QCjdkTedkbiBVgNdXi5tE1doZu6BmWYVwLQwGEB/KqCngWe7q8XIoidT03xzInrhw5KWrrfmEjxngeZLQCkusL7qxSKIONa3NFMt4/chbr52FXg+3AU= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1701360633; c=relaxed/simple; bh=+WHr7vFhZMYhh0sp50WgPSHm3kLpaLTCQd0zqA+iSjg=; h=DKIM-Signature:Message-ID:Subject:From:To:Date:MIME-Version; b=lfFZ4mFuHv8LgdcPnbTfPBE97oZMMuHLujmUgM7xaAW3WE6u5IiC2WhjCJ2xACwRjncOWLe2TeEYeKxnoggy+e9J8wsjCQ5L7vftni/mXY8FtwTW6YP6UNl7Tn7TxVgArFox+p0Cab3yAnrrJ83eV8pmZDrZV37so6x6kT2N2CA= ARC-Authentication-Results: i=1; server2.sourceware.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=xry111.site; s=default; t=1701360629; bh=+WHr7vFhZMYhh0sp50WgPSHm3kLpaLTCQd0zqA+iSjg=; h=Subject:From:To:Cc:Date:In-Reply-To:References:From; b=FiZveiUGPoMF9CIm+sAYbU+AenfgwhiQiODxRIuvH1TJKSmNXEVjsIuX75rTOAvJZ w5TUA/6SRjIfq76BdoMsJBvGZT+Na6YnJs/CaPu+/jCq5ORV1IhoQkOfWt3asQCZHk 0gcMANb6FkZZCBa4eqq7DSbh/xIp+ht3swPCGX+g= Received: from [IPv6:240e:358:11b5:1100:dc73:854d:832e:3] (unknown [IPv6:240e:358:11b5:1100:dc73:854d:832e:3]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (P-256) server-signature ECDSA (P-384) server-digest SHA384) (Client did not present a certificate) (Authenticated sender: xry111@xry111.site) by xry111.site (Postfix) with ESMTPSA id 4658D66A83; Thu, 30 Nov 2023 11:10:23 -0500 (EST) Message-ID: Subject: Re: [PATCH v1 2/2] LoongArch: Add call and tail pseudo instructions From: Xi Ruoyao To: mengqinggang , binutils@sourceware.org Cc: xuchenghua@loongson.cn, chenglulu@loongson.cn, liuzhensong@loongson.cn, i.swmail@xen0n.name, maskray@google.com, cailulu@loongson.cn, luweining@loongson.cn, wanglei@loongson.cn, hejinyang@loongson.cn Date: Fri, 01 Dec 2023 00:10:19 +0800 In-Reply-To: <20231130111328.3236602-3-mengqinggang@loongson.cn> References: <20231130111328.3236602-1-mengqinggang@loongson.cn> <20231130111328.3236602-3-mengqinggang@loongson.cn> Autocrypt: addr=xry111@xry111.site; prefer-encrypt=mutual; keydata=mDMEYnkdPhYJKwYBBAHaRw8BAQdAsY+HvJs3EVKpwIu2gN89cQT/pnrbQtlvd6Yfq7egugi0HlhpIFJ1b3lhbyA8eHJ5MTExQHhyeTExMS5zaXRlPoiTBBMWCgA7FiEEkdD1djAfkk197dzorKrSDhnnEOMFAmJ5HT4CGwMFCwkIBwICIgIGFQoJCAsCBBYCAwECHgcCF4AACgkQrKrSDhnnEOPHFgD8D9vUToTd1MF5bng9uPJq5y3DfpcxDp+LD3joA3U2TmwA/jZtN9xLH7CGDHeClKZK/ZYELotWfJsqRcthOIGjsdAPuDgEYnkdPhIKKwYBBAGXVQEFAQEHQG+HnNiPZseiBkzYBHwq/nN638o0NPwgYwH70wlKMZhRAwEIB4h4BBgWCgAgFiEEkdD1djAfkk197dzorKrSDhnnEOMFAmJ5HT4CGwwACgkQrKrSDhnnEOPjXgD/euD64cxwqDIqckUaisT3VCst11RcnO5iRHm6meNIwj0BALLmWplyi7beKrOlqKfuZtCLbiAPywGfCNg8LOTt4iMD Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable User-Agent: Evolution 3.50.1 MIME-Version: 1.0 X-Spam-Status: No, score=-7.6 required=5.0 tests=BAYES_00,BODY_8BITS,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,GIT_PATCH_0,LIKELY_SPAM_FROM,SPF_HELO_PASS,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: I'd not use a plain "call" or "tail" as the pseudo name. The problem is people not very familiar with LoongArch may use them instead of "bl" or "b" everywhere and regress the code. Esp. the programmers know some RISC-V: in Aug 28 we've noticed several RISC-V developers were attending Loongson user conference and they may contribute some LoongArch code too in the future. In RISC-V assembly call/tail are aliases of jal with rd =3D ra/r0. Maybe "call_medium"? "call_36"? "call_far"? Or if we can relax call/tail into b/bl it would be even better. On Thu, 2023-11-30 at 19:13 +0800, mengqinggang wrote: > --- > =C2=A0gas/testsuite/gas/loongarch/medium-call.d=C2=A0=C2=A0 | 10 ++++++++= -- > =C2=A0gas/testsuite/gas/loongarch/medium-call.s=C2=A0=C2=A0 |=C2=A0 2 ++ > =C2=A0ld/testsuite/ld-loongarch-elf/medium-call.s |=C2=A0 2 ++ > =C2=A0opcodes/loongarch-opc.c=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0 | 11 +++++++++++ > =C2=A04 files changed, 23 insertions(+), 2 deletions(-) >=20 > diff --git a/gas/testsuite/gas/loongarch/medium-call.d b/gas/testsuite/ga= s/loongarch/medium-call.d > index 4183818cb4f..3491760b96a 100644 > --- a/gas/testsuite/gas/loongarch/medium-call.d > +++ b/gas/testsuite/gas/loongarch/medium-call.d > @@ -10,6 +10,12 @@ Disassembly of section .text: > =C2=A0[=C2=A0 ]+0:[=C2=A0 ]+1e000001[=C2=A0 ]+pcaddu18i[=C2=A0 ]+\$ra, 0 > =C2=A0[=C2=A0 ]+0: R_LARCH_CALL36[=C2=A0 ]+a > =C2=A0[=C2=A0 ]+4:[=C2=A0 ]+4c000021[=C2=A0 ]+jirl[=C2=A0 ]+\$ra, \$ra, 0 > -[=C2=A0 ]+8:[=C2=A0 ]+1e00000c[=C2=A0 ]+pcaddu18i[=C2=A0 ]+\$t0, 0 > +[=C2=A0 ]+8:[=C2=A0 ]+1e000001[=C2=A0 ]+pcaddu18i[=C2=A0 ]+\$ra, 0 > =C2=A0[=C2=A0 ]+8: R_LARCH_CALL36[=C2=A0 ]+a > -[=C2=A0 ]+c:[=C2=A0 ]+4c000180[=C2=A0 ]+jr[=C2=A0 ]+\$t0 > +[=C2=A0 ]+c:[=C2=A0 ]+4c000021[=C2=A0 ]+jirl[=C2=A0 ]+\$ra, \$ra, 0 > +[=C2=A0 ]+10:[=C2=A0 ]+1e00000c[=C2=A0 ]+pcaddu18i[=C2=A0 ]+\$t0, 0 > +[=C2=A0 ]+10: R_LARCH_CALL36[=C2=A0 ]+a > +[=C2=A0 ]+14:[=C2=A0 ]+4c000180[=C2=A0 ]+jr[=C2=A0 ]+\$t0 > +[=C2=A0 ]+18:[=C2=A0 ]+1e00000c[=C2=A0 ]+pcaddu18i[=C2=A0 ]+\$t0, 0 > +[=C2=A0 ]+18: R_LARCH_CALL36[=C2=A0 ]+a > +[=C2=A0 ]+1c:[=C2=A0 ]+4c000180[=C2=A0 ]+jr[=C2=A0 ]+\$t0 > diff --git a/gas/testsuite/gas/loongarch/medium-call.s b/gas/testsuite/ga= s/loongarch/medium-call.s > index f2977d1c6d7..55a2fc6ffff 100644 > --- a/gas/testsuite/gas/loongarch/medium-call.s > +++ b/gas/testsuite/gas/loongarch/medium-call.s > @@ -1,6 +1,8 @@ > =C2=A0=C2=A0 # call .L1, r1(ra) temp register, r1(ra) return register. > +=C2=A0 call a > =C2=A0=C2=A0 pcaddu18i $r1, %call36(a) > =C2=A0=C2=A0 jirl =C2=A0=C2=A0=C2=A0 $r1, $r1, 0 > =C2=A0=C2=A0 # tail .L1, r12(t0) temp register, r0(zero) return register. > +=C2=A0 tail a > =C2=A0=C2=A0 pcaddu18i $r12, %call36(a) > =C2=A0=C2=A0 jirl =C2=A0=C2=A0=C2=A0 $r0, $r12, 0 > diff --git a/ld/testsuite/ld-loongarch-elf/medium-call.s b/ld/testsuite/l= d-loongarch-elf/medium-call.s > index 4d1888b76a0..31d4c2c1c75 100644 > --- a/ld/testsuite/ld-loongarch-elf/medium-call.s > +++ b/ld/testsuite/ld-loongarch-elf/medium-call.s > @@ -1,7 +1,9 @@ > =C2=A0.L1: > =C2=A0=C2=A0 # call .L1, r1(ra) temp register, r1(ra) return register. > +=C2=A0 call .L1 > =C2=A0=C2=A0 pcaddu18i $r1, %call36(.L1) > =C2=A0=C2=A0 jirl =C2=A0=C2=A0=C2=A0 $r1, $r1, 0 > =C2=A0=C2=A0 # tail .L1, r12(t0) temp register, r0(zero) return register. > +=C2=A0 tail .L1 > =C2=A0=C2=A0 pcaddu18i $r12, %call36(.L1) > =C2=A0=C2=A0 jirl =C2=A0=C2=A0=C2=A0 $r0, $r12, 0 > diff --git a/opcodes/loongarch-opc.c b/opcodes/loongarch-opc.c > index 15c7da6340c..1d02f020686 100644 > --- a/opcodes/loongarch-opc.c > +++ b/opcodes/loongarch-opc.c > @@ -293,6 +293,15 @@ const char *const loongarch_x_normal_name[32] =3D > =C2=A0=C2=A0 &LARCH_opts.ase_lp64, =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 \ > =C2=A0=C2=A0 &LARCH_opts.ase_gpcr > =C2=A0 > +#define INSN_LA_CALL =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 \ > +=C2=A0 "pcaddu18i $ra,%%call36(%1);"=C2=A0=C2=A0=C2=A0 \ > +=C2=A0 "jirl $ra,$ra,0;",=C2=A0=C2=A0=C2=A0 \ > +=C2=A0 &LARCH_opts.ase_lp64, 0 > + > +#define INSN_LA_TAIL =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 \ > +=C2=A0 "pcaddu18i $t0,%%call36(%1);"=C2=A0=C2=A0 \ > +=C2=A0 "jirl $zero,$t0,0;",=C2=A0=C2=A0 \ > +=C2=A0 &LARCH_opts.ase_lp64, 0 > =C2=A0 > =C2=A0static struct loongarch_opcode loongarch_macro_opcodes[] =3D > =C2=A0{ > @@ -340,6 +349,8 @@ static struct loongarch_opcode loongarch_macro_opcode= s[] =3D > =C2=A0=C2=A0 { 0, 0, "la.tls.gd", "r,l", =C2=A0 INSN_LA_TLS_GD64, 0 }, > =C2=A0=C2=A0 { 0, 0, "la.tls.gd", "r,l", =C2=A0 INSN_LA_TLS_GD64_LARGE_AB= S, 0 }, > =C2=A0=C2=A0 { 0, 0, "la.tls.gd", "r,r,l",=C2=A0 INSN_LA_TLS_GD64_LARGE_P= CREL, 0 }, > +=C2=A0 { 0, 0, "call", "la", =C2=A0 INSN_LA_CALL, 0 }, > +=C2=A0 { 0, 0, "tail", "la", =C2=A0 INSN_LA_TAIL, 0 }, > =C2=A0=C2=A0 { 0, 0, "pcaddi", "r,la", =C2=A0 "pcaddi %1, %%pcrel_20(%2)"= , &LARCH_opts.ase_ilp32, 0, 0 }, > =C2=A0=C2=A0 { 0, 0, 0, 0, 0, 0, 0, 0 } /* Terminate the list.=C2=A0 */ > =C2=A0}; --=20 Xi Ruoyao School of Aerospace Science and Technology, Xidian University