From: "Andre Vieira (lists)" <andre.simoesdiasvieira@arm.com>
To: binutils@sourceware.org
Subject: [PATCH, binutils, ARM, 6/16] New BF instruction for Armv8.1-M Mainline
Date: Thu, 04 Apr 2019 13:37:00 -0000 [thread overview]
Message-ID: <b7b8b136-a3c2-0287-268e-7dcd4ab1aed7@arm.com> (raw)
In-Reply-To: <cfedf9a3-8a0e-d9cd-3b65-683d00e83621@arm.com>
[-- Attachment #1: Type: text/plain, Size: 1049 bytes --]
Hi
This patch is part of a series of patches to add support for Armv8.1-M
Mainline instructions to binutils.
This patch adds the BF instruction.
Testing: Added new tests for the valid instructions operands. Testsuite
shows no regression when run for arm-none-eabi targets.
Thanks
Sudi
ChangeLog entries are as follows :
*** gas/ChangeLog ***
2019-04-04 Sudakshina Das <sudi.das@arm.com>
* config/tc-arm.c (T16_32_TAB): New entries for bf.
(do_t_branch_future): New.
(insns): New instruction for bf.
* testsuite/gas/arm/armv8_1-m-bf.d: New.
* testsuite/gas/arm/armv8_1-m-bf.s: New.
* testsuite/gas/arm/armv8_1-m-bf-bad.s: New
* testsuite/gas/arm/armv8_1-m-bf-bad.l: New
* testsuite/gas/arm/armv8_1-m-bf-bad.d: New
*** ld/ChangeLog ***
2019-04-04 Sudakshina Das <sudi.das@arm.com>
* testsuite/ld-arm/bf.s: New.
* testsuite/ld-arm/bf.d: New.
* testsuite/ld-arm/arm-elf.exp: Add above test.
*** opcodes/ChangeLog ***
2019-04-04 Sudakshina Das <sudi.das@arm.com>
* arm-dis.c (thumb32_opcodes): New instructions for bf.
[-- Attachment #2: 6.patch --]
[-- Type: text/x-patch, Size: 8532 bytes --]
diff --git a/gas/config/tc-arm.c b/gas/config/tc-arm.c
index d3a21d63575c194051606bb723a224d3c10334e9..04bd9b0e612b2e88db275effeec2749a4ba3605f 100644
--- a/gas/config/tc-arm.c
+++ b/gas/config/tc-arm.c
@@ -10505,6 +10505,7 @@ encode_thumb32_addr_mode (int i, bfd_boolean is_t, bfd_boolean is_d)
X(_asrs, 1000, fa50f000), \
X(_b, e000, f000b000), \
X(_bcond, d000, f0008000), \
+ X(_bf, 0000, f040e001), \
X(_bic, 4380, ea200000), \
X(_bics, 4380, ea300000), \
X(_cmn, 42c0, eb100f00), \
@@ -13320,6 +13321,51 @@ v8_1_branch_value_check (int val, int nbits, int is_signed)
return SUCCESS;
}
+/* For branches in Armv8.1-M Mainline. */
+static void
+do_t_branch_future (void)
+{
+ unsigned long insn = inst.instruction;
+
+ inst.instruction = THUMB_OP32 (inst.instruction);
+ if (inst.operands[0].hasreloc == 0)
+ {
+ if (v8_1_branch_value_check (inst.operands[0].imm, 5, FALSE) == FAIL)
+ as_bad (BAD_BRANCH_OFF);
+
+ inst.instruction |= ((inst.operands[0].imm & 0x1f) >> 1) << 23;
+ }
+ else
+ {
+ inst.relocs[0].type = BFD_RELOC_THUMB_PCREL_BRANCH5;
+ inst.relocs[0].pc_rel = 1;
+ }
+
+ switch (insn)
+ {
+ case T_MNEM_bf:
+ if (inst.operands[1].hasreloc == 0)
+ {
+ int val = inst.operands[1].imm;
+ if (v8_1_branch_value_check (inst.operands[1].imm, 17, TRUE) == FAIL)
+ as_bad (BAD_BRANCH_OFF);
+
+ int immA = (val & 0x0001f000) >> 12;
+ int immB = (val & 0x00000ffc) >> 2;
+ int immC = (val & 0x00000002) >> 1;
+ inst.instruction |= (immA << 16) | (immB << 1) | (immC << 11);
+ }
+ else
+ {
+ inst.relocs[1].type = BFD_RELOC_ARM_THUMB_BF17;
+ inst.relocs[1].pc_rel = 1;
+ }
+ break;
+
+ default: abort ();
+ }
+}
+
/* Neon instruction encoder helpers. */
/* Encodings for the different types for various Neon opcodes. */
@@ -19538,6 +19584,11 @@ static struct asm_barrier_opt barrier_opt_names[] =
{ mnem, OPS##nops ops, OT_unconditional, 0x0, 0x##top, 0, THUMB_VARIANT, \
NULL, do_##te }
+/* T_MNEM_xyz enumerator variants of ToC. */
+#define toC(mnem, top, nops, ops, te) \
+ { mnem, OPS##nops ops, OT_csuffix, 0x0, T_MNEM##top, 0, THUMB_VARIANT, NULL, \
+ do_##te }
+
/* Legacy mnemonics that always have conditional infix after the third
character. */
#define CL(mnem, op, nops, ops, ae) \
@@ -21623,6 +21674,11 @@ static const struct asm_opcode insns[] =
#define THUMB_VARIANT & arm_ext_v8m_main
ToC("vlldm", ec300a00, 1, (RRnpc), rn),
ToC("vlstm", ec200a00, 1, (RRnpc), rn),
+
+ /* Armv8.1-M Mainline instructions. */
+#undef THUMB_VARIANT
+#define THUMB_VARIANT & arm_ext_v8_1m_main
+ toC("bf", _bf, 2, (EXPs, EXPs), t_branch_future),
};
#undef ARM_VARIANT
#undef THUMB_VARIANT
@@ -21633,8 +21689,10 @@ static const struct asm_opcode insns[] =
#undef cCE
#undef cCL
#undef C3E
+#undef C3
#undef CE
#undef CM
+#undef CL
#undef UE
#undef UF
#undef UT
@@ -21650,6 +21708,10 @@ static const struct asm_opcode insns[] =
#undef OPS5
#undef OPS6
#undef do_0
+#undef ToC
+#undef toC
+#undef ToU
+#undef
\f
/* MD interface: bits in the object file. */
diff --git a/gas/testsuite/gas/arm/armv8_1-m-bf-bad.d b/gas/testsuite/gas/arm/armv8_1-m-bf-bad.d
new file mode 100644
index 0000000000000000000000000000000000000000..d61aad79e9a6faa26a733245b3769b867f5e126d
--- /dev/null
+++ b/gas/testsuite/gas/arm/armv8_1-m-bf-bad.d
@@ -0,0 +1,4 @@
+#name: Invalid Armv8.1-M Mainline BF instructions
+#source: armv8_1-m-bf-bad.s
+#as: -march=armv8.1-m.main
+#error_output: armv8_1-m-bf-bad.l
diff --git a/gas/testsuite/gas/arm/armv8_1-m-bf-bad.l b/gas/testsuite/gas/arm/armv8_1-m-bf-bad.l
new file mode 100644
index 0000000000000000000000000000000000000000..3f7ed80a6d07a4a2c05e8968e95c26d66eae2fab
--- /dev/null
+++ b/gas/testsuite/gas/arm/armv8_1-m-bf-bad.l
@@ -0,0 +1,9 @@
+.*: Assembler messages:
+.*:6: Error: branch out of range or not a multiple of 2
+.*:7: Error: branch out of range or not a multiple of 2
+.*:8: Error: branch out of range or not a multiple of 2
+.*:9: Error: branch out of range or not a multiple of 2
+.*:11: Error: branch out of range or not a multiple of 2
+.*:12: Error: branch out of range or not a multiple of 2
+.*:13: Error: branch out of range or not a multiple of 2
+.*:14: Error: branch out of range or not a multiple of 2
diff --git a/gas/testsuite/gas/arm/armv8_1-m-bf-bad.s b/gas/testsuite/gas/arm/armv8_1-m-bf-bad.s
new file mode 100644
index 0000000000000000000000000000000000000000..43ef4b1bf92fa42956f2fdabd29eeec7bcf168fb
--- /dev/null
+++ b/gas/testsuite/gas/arm/armv8_1-m-bf-bad.s
@@ -0,0 +1,14 @@
+ .syntax unified
+ .text
+ .thumb
+foo:
+ # OP0 : Unsigned, 5-bit, even
+ bf 0, 36
+ bf -2, 36
+ bf 3, 36
+ bf 32, 36
+ # OP1 : signed, 17-bit, even
+ bf 2, -5
+ bf 2, 5
+ bf 2, 65536
+ bf 2, -65538
diff --git a/gas/testsuite/gas/arm/armv8_1-m-bf.d b/gas/testsuite/gas/arm/armv8_1-m-bf.d
new file mode 100644
index 0000000000000000000000000000000000000000..9e721ed290d1291c27c210768ebf0358c038a105
--- /dev/null
+++ b/gas/testsuite/gas/arm/armv8_1-m-bf.d
@@ -0,0 +1,17 @@
+#name: Valid Armv8.1-M Mainline BF instruction
+#source: armv8_1-m-bf.s
+#as: -march=armv8.1-m.main
+#objdump: -dr --prefix-addresses --show-raw-insn
+
+.*: +file format .*arm.*
+
+Disassembly of section .text:
+0[0-9a-f]+ <[^>]+> f0c0 e803 bf 2, 0000000a <foo\+0xa>
+0[0-9a-f]+ <[^>]+> 4608 mov r0, r1
+0[0-9a-f]+ <[^>]+> f0df e7ff bf 2, 00000000 <.target>
+ 6: R_ARM_THM_BF16 .target
+0[0-9a-f]+ <[^>]+> 4609 mov r1, r1
+0[0-9a-f]+ <[^>]+> f140 e801 bf 4, 00000012 <foo\+0x12>
+0[0-9a-f]+ <[^>]+> 460a mov r2, r1
+0[0-9a-f]+ <[^>]+> 4613 mov r3, r2
+0[0-9a-f]+ <[^>]+> 4614 mov r4, r2
diff --git a/gas/testsuite/gas/arm/armv8_1-m-bf.s b/gas/testsuite/gas/arm/armv8_1-m-bf.s
new file mode 100644
index 0000000000000000000000000000000000000000..cafc34bf5de4d54ef3db6139b8c997fa22608a2f
--- /dev/null
+++ b/gas/testsuite/gas/arm/armv8_1-m-bf.s
@@ -0,0 +1,14 @@
+ .syntax unified
+ .text
+ .thumb
+foo:
+ bf 2, 6
+ mov r0, r1
+ bf 2, .target
+ mov r1, r1
+ bf .LBranch, .LB2
+ mov r2, r1
+.LB2:
+ mov r3, r2
+.LBranch:
+ mov r4, r2
diff --git a/ld/testsuite/ld-arm/arm-elf.exp b/ld/testsuite/ld-arm/arm-elf.exp
index 450a76b7082be883d0bbc818420edd2d6a762e6e..ef3a49c23742f4c43c78e73aa692928ba3d56123 100644
--- a/ld/testsuite/ld-arm/arm-elf.exp
+++ b/ld/testsuite/ld-arm/arm-elf.exp
@@ -667,6 +667,10 @@ set armeabitests_nonacl {
{{objdump -d armv4-bx.d}}
"armv4-bx"}
+ {"Armv8.1-M Mainline BF" "-r -Ttext 0x1000 --section-start .foo=0x1001000" "" "-march=armv8.1-m.main" {bf.s}
+ {{objdump -dr bf.d}}
+ "bf"}
+
{"R_ARM_THM_JUMP24 Relocation veneers: Short 1"
"--no-fix-arm1176 --section-start destsect=0x00009000 --section-start .text=0x8000" ""
"-march=armv7-a -mthumb"
diff --git a/ld/testsuite/ld-arm/bf.d b/ld/testsuite/ld-arm/bf.d
new file mode 100644
index 0000000000000000000000000000000000000000..190383f93af81e6c9ba023b07d1bfa3771e29a97
--- /dev/null
+++ b/ld/testsuite/ld-arm/bf.d
@@ -0,0 +1,14 @@
+
+.*: file format elf32-littlearm
+
+
+Disassembly of section .text:
+
+00001000 <_start>:
+ 1000: f0df e7ff bf 2, 1001000 <bar>
+ 1000: R_ARM_THM_BF16 bar
+
+Disassembly of section .foo:
+
+01001000 <bar>:
+ 1001000: 4770 bx lr
diff --git a/ld/testsuite/ld-arm/bf.s b/ld/testsuite/ld-arm/bf.s
new file mode 100644
index 0000000000000000000000000000000000000000..164a90d04b4e995add2c54beee31e63fbdc5c12d
--- /dev/null
+++ b/ld/testsuite/ld-arm/bf.s
@@ -0,0 +1,19 @@
+ .global _start
+ .syntax unified
+
+@ We will place the section .text at 0x1000.
+
+ .text
+ .thumb_func
+
+_start:
+ bf 2, bar
+
+@ We will place the section .foo at 0x1001000.
+
+ .section .foo, "xa"
+ .thumb_func
+
+bar:
+ bx lr
+
diff --git a/opcodes/arm-dis.c b/opcodes/arm-dis.c
index 71443d3ea41966309d4516754eb8f2e38e3e6df0..966a4d4d92fa660b1754c4c703648ec008efcfb0 100644
--- a/opcodes/arm-dis.c
+++ b/opcodes/arm-dis.c
@@ -2747,6 +2747,11 @@ static const struct opcode16 thumb_opcodes[] =
makes heavy use of special-case bit patterns. */
static const struct opcode32 thumb32_opcodes[] =
{
+ /* Armv8.1-M Mainline instructions. */
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
+ 0xf040e001, 0xf860f001, "bf%c\t%G, %W"},
+
+
/* ARMv8-M and ARMv8-M Security Extensions instructions. */
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M), 0xe97fe97f, 0xffffffff, "sg"},
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M),
next prev parent reply other threads:[~2019-04-04 13:37 UTC|newest]
Thread overview: 32+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-04-04 13:24 [PATCH, binutils, ARM, 0/16] Add support " Andre Vieira (lists)
2019-04-04 13:28 ` [PATCH, binutils, ARM, 1/16] Add support for Armv8.1-M Mainline CLI Andre Vieira (lists)
2019-04-04 13:28 ` [PATCH, GAS, ARM, 2/16] Add CLI extension support for Armv8.1-M Mainline Andre Vieira (lists)
2019-04-04 13:34 ` [PATCH, binutils, ARM, 4/16] BF insns infrastructure with array of relocs in struct arm_it Andre Vieira (lists)
2019-04-04 13:34 ` [PATCH, binutils, ARM, 3/16] BF insns infrastructure with new bfd_reloc_code_real for fallback branch Andre Vieira (lists)
2019-04-04 13:36 ` [PATCH, binutils, ARM, 5/16] BF insns infrastructure with new global reloc R_ARM_THM_BF16 Andre Vieira (lists)
2019-04-04 13:37 ` Andre Vieira (lists) [this message]
2019-04-12 10:41 ` [PATCH, binutils, ARM, 6/16] New BF instruction for Armv8.1-M Mainline Andre Vieira (lists)
2019-04-04 13:38 ` [PATCH, binutils, ARM, 7/16] New BFX and BFLX " Andre Vieira (lists)
2019-04-04 13:38 ` [PATCH, binutils, ARM, 8/16] BFL infrastructure with new global reloc R_ARM_THM_BF18 Andre Vieira (lists)
2019-04-04 13:39 ` [PATCH, binutils, ARM, 9/16] New BFL instruction for Armv8.1-M Mainline Andre Vieira (lists)
2019-04-12 10:40 ` Andre Vieira (lists)
2019-04-04 13:40 ` [PATCH, binutils, ARM, 10/16] BFCSEL infrastructure with new global reloc R_ARM_THM_BF12 Andre Vieira (lists)
2019-04-04 13:41 ` [PATCH, binutils, ARM, 11/16] New BFCSEL instruction for Armv8.1-M Mainline Andre Vieira (lists)
2019-04-12 10:39 ` Andre Vieira (lists)
2019-04-04 13:41 ` [PATCH, binutils, ARM, 12/16] Scalar Low Overhead loop instructions " Andre Vieira (lists)
2019-04-12 10:40 ` Andre Vieira (lists)
2019-04-04 13:42 ` [PATCH, binutils, ARM, 13/16] Add support for CLRM Andre Vieira (lists)
2019-04-04 13:43 ` [PATCH, opcodes, ARM, 14/16] Add mode availability to coprocessor table entries Andre Vieira (lists)
2019-04-04 13:44 ` [PATCH, binutils, ARM, 16/16] Add support to VLDR and VSTR of system registers Andre Vieira (lists)
2019-04-04 13:44 ` [PATCH, binutils, ARM, 15/16] Add support for VSCCLRM Andre Vieira (lists)
2019-04-11 10:04 ` [PATCH, binutils, ARM, 0/16] Add support for Armv8.1-M Mainline Nick Clifton
2019-04-12 10:39 ` Andre Vieira (lists)
2019-04-12 13:51 ` Nick Clifton
2019-04-15 9:41 ` Andre Simoes Dias Vieira
2019-04-16 1:58 ` Alan Modra
2019-04-16 11:52 ` Andre Simoes Dias Vieira
2019-04-16 12:36 ` Alan Modra
2019-05-01 9:32 ` Andre Vieira (lists)
2019-05-02 1:21 ` Alan Modra
2019-05-15 15:34 ` Andre Vieira (lists)
2019-05-20 10:31 ` Nick Clifton
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