From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-sender-0.a4lg.com (mail-sender.a4lg.com [153.120.152.154]) by sourceware.org (Postfix) with ESMTPS id AC7E33852756 for ; Wed, 19 Oct 2022 13:13:21 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org AC7E33852756 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=irq.a4lg.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=irq.a4lg.com Received: from [127.0.0.1] (localhost [127.0.0.1]) by mail-sender-0.a4lg.com (Postfix) with ESMTPSA id 1181A300089; Wed, 19 Oct 2022 13:13:20 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=irq.a4lg.com; s=2017s01; t=1666185200; bh=S5Ol1ldLTPK9xM2hbJgqdD2ES4CcXEjpuaVyGhq25G0=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: Mime-Version:Content-Transfer-Encoding; b=fLMR0V97kzhviVlbnpkAf8jJKtCyYpbq0UPA/15VIhj9p92CNV/abtMJngNoL1fw9 RYagGJAYLX0vLAhg6F54n7qDG0r5FbMYvEOaspvcnHE7Wj9wGU2B65GnBpMDExKMSn wsxPsv9NwyfqhUkIokoI8eCwhSAZL19GVOJD27ic= From: Tsukasa OI To: Tsukasa OI , Nelson Chu , Kito Cheng , Palmer Dabbelt Cc: binutils@sourceware.org Subject: [PATCH v2 7/8] RISC-V: Make alias instructions aliases Date: Wed, 19 Oct 2022 13:12:01 +0000 Message-Id: In-Reply-To: References: Mime-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-12.0 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,GIT_PATCH_0,SPF_HELO_NONE,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: This commit makes following alias instruction real aliases. - scall (an alias of "ecall") - fmv.x.s (an alias of "fmv.x.w") - fmv.s.x (an alias of "fmv.w.x") opcodes/ChangeLog: * riscv-opc.c (riscv_opcodes): Make alias instructions aliases. --- opcodes/riscv-opc.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c index 3bf22cff219..b7a3b438209 100644 --- a/opcodes/riscv-opc.c +++ b/opcodes/riscv-opc.c @@ -475,7 +475,7 @@ const struct riscv_opcode riscv_opcodes[] = {"rdinstreth", 32, INSN_CLASS_I, "d", MATCH_RDINSTRETH, MASK_RDINSTRETH, match_opcode, INSN_ALIAS }, {"rdtimeh", 32, INSN_CLASS_I, "d", MATCH_RDTIMEH, MASK_RDTIMEH, match_opcode, INSN_ALIAS }, {"ecall", 0, INSN_CLASS_I, "", MATCH_ECALL, MASK_ECALL, match_opcode, 0 }, -{"scall", 0, INSN_CLASS_I, "", MATCH_ECALL, MASK_ECALL, match_opcode, 0 }, +{"scall", 0, INSN_CLASS_I, "", MATCH_ECALL, MASK_ECALL, match_opcode, INSN_ALIAS }, {"xor", 0, INSN_CLASS_I, "d,s,j", MATCH_XORI, MASK_XORI, match_opcode, INSN_ALIAS }, {"xor", 0, INSN_CLASS_C, "Cs,Cw,Ct", MATCH_C_XOR, MASK_C_XOR, match_opcode, INSN_ALIAS }, {"xor", 0, INSN_CLASS_C, "Cs,Ct,Cw", MATCH_C_XOR, MASK_C_XOR, match_opcode, INSN_ALIAS }, @@ -710,8 +710,8 @@ const struct riscv_opcode riscv_opcodes[] = {"fsw", 0, INSN_CLASS_F, "T,A,s", 0, (int) M_FSW, match_never, INSN_MACRO }, {"fmv.x.w", 0, INSN_CLASS_F, "d,S", MATCH_FMV_X_W, MASK_FMV_X_W, match_opcode, 0 }, {"fmv.w.x", 0, INSN_CLASS_F, "D,s", MATCH_FMV_W_X, MASK_FMV_W_X, match_opcode, 0 }, -{"fmv.x.s", 0, INSN_CLASS_F, "d,S", MATCH_FMV_X_W, MASK_FMV_X_W, match_opcode, 0 }, -{"fmv.s.x", 0, INSN_CLASS_F, "D,s", MATCH_FMV_W_X, MASK_FMV_W_X, match_opcode, 0 }, +{"fmv.x.s", 0, INSN_CLASS_F, "d,S", MATCH_FMV_X_W, MASK_FMV_X_W, match_opcode, INSN_ALIAS }, +{"fmv.s.x", 0, INSN_CLASS_F, "D,s", MATCH_FMV_W_X, MASK_FMV_W_X, match_opcode, INSN_ALIAS }, {"fmv.s", 0, INSN_CLASS_F_INX, "D,U", MATCH_FSGNJ_S, MASK_FSGNJ_S, match_rs1_eq_rs2, INSN_ALIAS }, {"fneg.s", 0, INSN_CLASS_F_INX, "D,U", MATCH_FSGNJN_S, MASK_FSGNJN_S, match_rs1_eq_rs2, INSN_ALIAS }, {"fabs.s", 0, INSN_CLASS_F_INX, "D,U", MATCH_FSGNJX_S, MASK_FSGNJX_S, match_rs1_eq_rs2, INSN_ALIAS }, -- 2.34.1