From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-sender-0.a4lg.com (mail-sender.a4lg.com [153.120.152.154]) by sourceware.org (Postfix) with ESMTPS id 5D2363857C58 for ; Thu, 22 Sep 2022 06:30:53 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 5D2363857C58 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=irq.a4lg.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=irq.a4lg.com Received: from [127.0.0.1] (localhost [127.0.0.1]) by mail-sender-0.a4lg.com (Postfix) with ESMTPSA id A5E14300089; Thu, 22 Sep 2022 06:30:50 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=irq.a4lg.com; s=2017s01; t=1663828250; bh=jm6CZL4QOgOm47tazBkYMzHzywhznhpYPtTcUFe5Up0=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: Mime-Version:Content-Transfer-Encoding; b=JzEApVno4GP83eefLfESvGfhjoPv6Kr0WbukpkkxcDNbCuRxchvBcGkjxjAdBy4cR OBkqt7QLLDQ15LavhbpQ1oJvpPxbvVJWfZ6PZnN8XeEG9+oIQiv0QR8LF8FbG8Fpjf IOuFvWOfz4ETKqiUkwtO8Remz3uwCuqHeRSBynkA= From: Tsukasa OI To: Tsukasa OI , Nelson Chu , Kito Cheng , Palmer Dabbelt Cc: binutils@sourceware.org Subject: [PATCH v2 1/2] RISC-V: Add macro-only operands to validate_riscv_insn Date: Thu, 22 Sep 2022 06:30:37 +0000 Message-Id: In-Reply-To: References: Mime-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-12.1 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,GIT_PATCH_0,SPF_HELO_NONE,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: Although they are not (and should not be) reachable, following macro-only operands are parsed in the `validate_riscv_insn' function and ignored. That function also notes that they are macro-only. - "A" - "B" - "I" Following this convention, this commit adds three remaining macro-only operands to this function. By doing this, we could instead choose to reject those operands from appearing in regular instructions later. - "c" (used by call, tail and jump macros) - "VM" (used by vmsge.vx and vmsgeu.vx macros) - "VT" (likewise) gas/ChangeLog: * config/tc-riscv.c (validate_riscv_insn): Add "c", "VM" and "VT" macro-only operand types. --- gas/config/tc-riscv.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c index 5411d68a401..0a14b2cecc8 100644 --- a/gas/config/tc-riscv.c +++ b/gas/config/tc-riscv.c @@ -1203,6 +1203,8 @@ validate_riscv_insn (const struct riscv_opcode *opc, int length) case 'j': case 'k': USE_BITS (OP_MASK_VIMM, OP_SH_VIMM); break; case 'm': USE_BITS (OP_MASK_VMASK, OP_SH_VMASK); break; + case 'M': break; /* Macro operand, must be a mask register. */ + case 'T': break; /* Macro operand, must be a vector register. */ default: goto unknown_validate_operand; } @@ -1214,6 +1216,7 @@ validate_riscv_insn (const struct riscv_opcode *opc, int length) case '>': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; case 'A': break; /* Macro operand, must be symbol. */ case 'B': break; /* Macro operand, must be symbol or constant. */ + case 'c': break; /* Macro operand, must be symbol or constant. */ case 'I': break; /* Macro operand, must be constant. */ case 'D': /* RD, floating point. */ case 'd': USE_BITS (OP_MASK_RD, OP_SH_RD); break; -- 2.34.1