From: Tsukasa OI <research_trasio@irq.a4lg.com>
To: Tsukasa OI <research_trasio@irq.a4lg.com>,
Kito Cheng <kito.cheng@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>
Cc: binutils@sourceware.org
Subject: [PATCH 3/3] RISC-V: Add testcases disassembling zext.h
Date: Fri, 3 Jun 2022 21:05:47 +0900 [thread overview]
Message-ID: <c57617e6ab099e82473a454e2f28566a2ad2b035.1654257944.git.research_trasio@irq.a4lg.com> (raw)
In-Reply-To: <cover.1654257944.git.research_trasio@irq.a4lg.com>
This commit adds testcases for zext.h instruction (Zbb extension) on
diassembler.
gas/ChangeLog:
* testsuite/gas/riscv/zbb-zext.h-dis-1.s: New test.
* testsuite/gas/riscv/zbb-zext.h-dis-2.s: Likewise.
* testsuite/gas/riscv/zbb-zext.h-dis-1-1.d: Likewise.
* testsuite/gas/riscv/zbb-zext.h-dis-1-2.d: Likewise.
* testsuite/gas/riscv/zbb-zext.h-dis-1-3.d: Likewise.
* testsuite/gas/riscv/zbb-zext.h-dis-2.d: Likewise.
---
gas/testsuite/gas/riscv/zbb-zext.h-dis-1-1.d | 11 +++++++++++
gas/testsuite/gas/riscv/zbb-zext.h-dis-1-2.d | 11 +++++++++++
gas/testsuite/gas/riscv/zbb-zext.h-dis-1-3.d | 11 +++++++++++
gas/testsuite/gas/riscv/zbb-zext.h-dis-1.s | 2 ++
gas/testsuite/gas/riscv/zbb-zext.h-dis-2.d | 11 +++++++++++
gas/testsuite/gas/riscv/zbb-zext.h-dis-2.s | 4 ++++
6 files changed, 50 insertions(+)
create mode 100644 gas/testsuite/gas/riscv/zbb-zext.h-dis-1-1.d
create mode 100644 gas/testsuite/gas/riscv/zbb-zext.h-dis-1-2.d
create mode 100644 gas/testsuite/gas/riscv/zbb-zext.h-dis-1-3.d
create mode 100644 gas/testsuite/gas/riscv/zbb-zext.h-dis-1.s
create mode 100644 gas/testsuite/gas/riscv/zbb-zext.h-dis-2.d
create mode 100644 gas/testsuite/gas/riscv/zbb-zext.h-dis-2.s
diff --git a/gas/testsuite/gas/riscv/zbb-zext.h-dis-1-1.d b/gas/testsuite/gas/riscv/zbb-zext.h-dis-1-1.d
new file mode 100644
index 00000000000..13e3d610342
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zbb-zext.h-dis-1-1.d
@@ -0,0 +1,11 @@
+#as: -march=rv32i_zbb_zbkb
+#source: zbb-zext.h-dis-1.s
+#objdump: -d
+
+.*:[ ]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+[ ]+[0-9a-f]+:[ ]+0805c533[ ]+zext.h[ ]+a0,a1
diff --git a/gas/testsuite/gas/riscv/zbb-zext.h-dis-1-2.d b/gas/testsuite/gas/riscv/zbb-zext.h-dis-1-2.d
new file mode 100644
index 00000000000..e9218a8e3d2
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zbb-zext.h-dis-1-2.d
@@ -0,0 +1,11 @@
+#as: -march=rv32i_zbb_zbkb
+#source: zbb-zext.h-dis-1.s
+#objdump: -d -M no-aliases
+
+.*:[ ]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+[ ]+[0-9a-f]+:[ ]+0805c533[ ]+pack[ ]+a0,a1,zero
diff --git a/gas/testsuite/gas/riscv/zbb-zext.h-dis-1-3.d b/gas/testsuite/gas/riscv/zbb-zext.h-dis-1-3.d
new file mode 100644
index 00000000000..629da4ff984
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zbb-zext.h-dis-1-3.d
@@ -0,0 +1,11 @@
+#as: -march=rv32i_zbb
+#source: zbb-zext.h-dis-1.s
+#objdump: -d -M no-aliases
+
+.*:[ ]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+[ ]+[0-9a-f]+:[ ]+0805c533[ ]+zext.h[ ]+a0,a1
diff --git a/gas/testsuite/gas/riscv/zbb-zext.h-dis-1.s b/gas/testsuite/gas/riscv/zbb-zext.h-dis-1.s
new file mode 100644
index 00000000000..ab04765dd5d
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zbb-zext.h-dis-1.s
@@ -0,0 +1,2 @@
+target:
+ zext.h a0, a1
diff --git a/gas/testsuite/gas/riscv/zbb-zext.h-dis-2.d b/gas/testsuite/gas/riscv/zbb-zext.h-dis-2.d
new file mode 100644
index 00000000000..3b1ee9de01e
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zbb-zext.h-dis-2.d
@@ -0,0 +1,11 @@
+#as: -march=rv32i_zbkb
+#source: zbb-zext.h-dis-2.s
+#objdump: -d
+
+.*:[ ]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+[ ]+[0-9a-f]+:[ ]+0805c533[ ]+pack[ ]+a0,a1,zero
diff --git a/gas/testsuite/gas/riscv/zbb-zext.h-dis-2.s b/gas/testsuite/gas/riscv/zbb-zext.h-dis-2.s
new file mode 100644
index 00000000000..88067d3e87d
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zbb-zext.h-dis-2.s
@@ -0,0 +1,4 @@
+target:
+ .option arch, +zbb
+ zext.h a0, a1
+ .option arch, -zbb
--
2.34.1
next prev parent reply other threads:[~2022-06-03 12:06 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-06-03 12:05 [PATCH 0/3] RISC-V: Implement "generic subsets" for disassembler Tsukasa OI
2022-06-03 12:05 ` [PATCH 1/3] RISC-V: Split disasm opcode matching and printing Tsukasa OI
2022-06-03 12:05 ` [PATCH 2/3] RISC-V: Implement "generic subsets" for disasm Tsukasa OI
2022-06-03 12:05 ` Tsukasa OI [this message]
2022-07-30 4:20 ` [PATCH 0/3] RISC-V: Implement "generic subsets" for disassembler Tsukasa OI
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