From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-sender-0.a4lg.com (mail-sender-0.a4lg.com [IPv6:2401:2500:203:30b:4000:6bfe:4757:0]) by sourceware.org (Postfix) with ESMTPS id 7A34A384D14E for ; Thu, 6 Oct 2022 04:40:46 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 7A34A384D14E Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=irq.a4lg.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=irq.a4lg.com Received: from [127.0.0.1] (localhost [127.0.0.1]) by mail-sender-0.a4lg.com (Postfix) with ESMTPSA id CC7DF300089; Thu, 6 Oct 2022 04:40:44 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=irq.a4lg.com; s=2017s01; t=1665031244; bh=/vCTF/G4QVs7ROme/TFeEqos4+xs1uuKLN+Z6Zsnsus=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: Mime-Version:Content-Transfer-Encoding; b=EZXxt53SsWkBoq+uKQsTq38IKElSd6h/U+plCEp0+2j8awkHeAPLsz5ZMhYBLzbJu Hy4UoZrjS/Cw57HecBo6x165qCbrMvjHdtBL9M4TVG1yG3N9Xa0eSa082aoShVBKs+ wejDw37EPviYtcBbz703EvP3odsVAom2DODMmkCI= From: Tsukasa OI To: Tsukasa OI , Nelson Chu , Kito Cheng , Palmer Dabbelt Cc: binutils@sourceware.org Subject: [PATCH v2 2/2] RISC-V: Improve "bits undefined" diagnostics Date: Thu, 6 Oct 2022 04:40:16 +0000 Message-Id: In-Reply-To: References: Mime-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-12.1 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,GIT_PATCH_0,SPF_HELO_NONE,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: This commit improves internal error message "internal: bad RISC-V opcode (bits 0x%lx undefined): %s %s" to display actual unused bits (excluding non-instruction bits). gas/ChangeLog: * config/tc-riscv.c (validate_riscv_insn): Exclude non- instruction bits from displaying internal diagnostics. Change error message slightly. --- gas/config/tc-riscv.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c index 2e41cec5c9f..34973d7803c 100644 --- a/gas/config/tc-riscv.c +++ b/gas/config/tc-riscv.c @@ -1312,8 +1312,8 @@ validate_riscv_insn (const struct riscv_opcode *opc, int length) if (used_bits != required_bits) { as_bad (_("internal: bad RISC-V opcode " - "(bits 0x%lx undefined): %s %s"), - ~(unsigned long)(used_bits & required_bits), + "(bits 0x%llx undefined or invalid): %s %s"), + (unsigned long long)(used_bits ^ required_bits), opc->name, opc->args); return false; } -- 2.34.1