From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from szxga08-in.huawei.com (szxga08-in.huawei.com [45.249.212.255]) by sourceware.org (Postfix) with ESMTPS id 5CDDC3858432 for ; Wed, 9 Feb 2022 00:56:52 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 5CDDC3858432 Received: from dggpeml500023.china.huawei.com (unknown [172.30.72.56]) by szxga08-in.huawei.com (SkyGuard) with ESMTP id 4JthDj2lmMz1FD1l; Wed, 9 Feb 2022 08:52:37 +0800 (CST) Received: from [10.67.77.175] (10.67.77.175) by dggpeml500023.china.huawei.com (7.185.36.114) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2308.21; Wed, 9 Feb 2022 08:56:49 +0800 Subject: Re: [PATCH] Fix the disassembly of the AArch64 SVE DECP/INCP/SQDECP/SQINCP instruction. To: Jan Beulich CC: Jingtao Cai , Bo Dong , References: <20220207093441.55725-1-zhangshaokun@hisilicon.com> <8b5990b6-a9c0-8365-17b0-fcb99b22a3f0@suse.com> From: Shaokun Zhang Message-ID: Date: Wed, 9 Feb 2022 08:56:49 +0800 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:78.0) Gecko/20100101 Thunderbird/78.8.1 MIME-Version: 1.0 In-Reply-To: <8b5990b6-a9c0-8365-17b0-fcb99b22a3f0@suse.com> Content-Type: text/plain; charset="utf-8" Content-Language: en-US Content-Transfer-Encoding: 7bit X-Originating-IP: [10.67.77.175] X-ClientProxiedBy: dggems704-chm.china.huawei.com (10.3.19.181) To dggpeml500023.china.huawei.com (7.185.36.114) X-CFilter-Loop: Reflected X-Spam-Status: No, score=-6.2 required=5.0 tests=BAYES_00, KAM_DMARC_STATUS, NICE_REPLY_A, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.4 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on server2.sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 09 Feb 2022 00:56:55 -0000 Hi Jan, Thanks for your quick reply. On 2022/2/7 17:44, Jan Beulich wrote: > On 07.02.2022 10:34, Shaokun Zhang via Binutils wrote: >> From: Jingtao Cai >> >> This patch fix qualifier for the AArch64 SVE DECP/INCP/SQDECP/SQINCP instruction, which take the predicate size specifier: >> DECP ., . >> INCP ., . >> SQINCP ., . >> SQDECP ., . >> >> Omitted predicate size specifier will be prohibited in a future release of the architecture, please refer to Arm A64 Instruction set documentation for Armv8-A >> architecture profile, see document[0]. >> >> [0]: https://developer.arm.com/documentation/ddi0596/2021-12/SVE-Instructions/DECP--vector---Decrement-vector-by-count-of-true-predicate-elements- >> >> E.g. : >> >> DECP Z1.H, P0.H >> >> This patch adds support for this kind of operand. >> >> DECP Z1.H, P0 >> >> This instruction leads to messages: >> Assembler messages: >> Error: operand mismatch -- `decp Z1.h,P0' > > IOW unlike the title suggests you change not only the disassembly Correct, current title is not quite accurate and how about `aarch64: allow explicit size specifier for predicate operand of decp/incp`? > logic. Wouldn't it be better to make this a warning initially, and > convert to an error only a few releases later? That way people > don't need to immediately fix their code. > Agree, we can make both `decp z1.h, p0` and `decp z1.h, p0.h` get assembled successfully and emit an warning for `decp z1.h, p0`, then everyone will be happy for now. >> did you mean this? >> decp z1.h, p0.h >> other valid variant(s): >> decp z1.s, p0 >> decp z1.d, p0 > > Isn't this misleading? Should these "other valid variant(s)" also > be output with suffixes? > Oops, apologies for the stupid typo, it does output with suffixes actually. Thanks, > Jan > > . >