From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-sender-0.a4lg.com (mail-sender-0.a4lg.com [IPv6:2401:2500:203:30b:4000:6bfe:4757:0]) by sourceware.org (Postfix) with ESMTPS id 013D93858D1E for ; Sun, 6 Aug 2023 01:53:25 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 013D93858D1E Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=irq.a4lg.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=irq.a4lg.com Received: from [127.0.0.1] (localhost [127.0.0.1]) by mail-sender-0.a4lg.com (Postfix) with ESMTPSA id 41066300089; Sun, 6 Aug 2023 01:53:21 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=irq.a4lg.com; s=2017s01; t=1691286801; bh=+L+FMcCFYhKv1F9ZiwC1x6p1CnmQIo50D6a15wZ3kG0=; h=From:To:Cc:Subject:Date:Message-ID:Mime-Version: Content-Transfer-Encoding; b=ke/DRojqs75qgMKkniTT0t0LOQ6k/Gln/r196NKUk2NQjyNm164QVOgjh2Y8y3A8f +/L13PkKKG9tvjvjakxX58he2ZGUcZsLxqflZ6EAUBNmiN04qHxLZ1MMtG/lGt1dU5 RAws6cf9wrZH3w3kViseDVK8epjTJECEVcLBHJek= From: Tsukasa OI To: Tsukasa OI , Palmer Dabbelt , Andrew Waterman , Jim Wilson , Nelson Chu , Kito Cheng Cc: binutils@sourceware.org Subject: [PATCH] RISC-V: Fix opcode entries of "vmsge{,u}.vx" Date: Sun, 6 Aug 2023 01:53:10 +0000 Message-ID: Mime-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-12.0 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,GIT_PATCH_0,KAM_MANYTO,SPF_HELO_NONE,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: From: Tsukasa OI Their check_func should be "match_never", not "match_opcode". The reasons this error did not cause any disassembler errors are: 1. The problem will not reproduce if "no-aliases" is specified (because macro instructions are handled as aliases). 2. If not, all affected compressed instructions or their aliases precede before "vmsge{,u}.vx" macro instructions. However, it'll easily break if we reorder opcode entries. This commit fixes this issue before the *accident* occurs. opcodes/ChangeLog: * riscv-opc.c (riscv_opcodes): Make sure that we never match to vmsge{,u}.vx instructions unless specified in the assembler. --- opcodes/riscv-opc.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c index 6a854736fec0..37c7694999ad 100644 --- a/opcodes/riscv-opc.c +++ b/opcodes/riscv-opc.c @@ -1606,10 +1606,10 @@ const struct riscv_opcode riscv_opcodes[] = {"vmsgeu.vi", 0, INSN_CLASS_V, "Vd,Vu,0Vm", MATCH_VMSEQVV, MASK_VMSEQVV, match_vs1_eq_vs2, INSN_ALIAS }, {"vmsgeu.vi", 0, INSN_CLASS_V, "Vd,Vt,VkVm", MATCH_VMSGTUVI, MASK_VMSGTUVI, match_opcode, INSN_ALIAS }, -{"vmsge.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", 0, (int) M_VMSGE, match_opcode, INSN_MACRO }, -{"vmsge.vx", 0, INSN_CLASS_V, "Vd,Vt,s,VM,VT", 0, (int) M_VMSGE, match_opcode, INSN_MACRO }, -{"vmsgeu.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", 0, (int) M_VMSGEU, match_opcode, INSN_MACRO }, -{"vmsgeu.vx", 0, INSN_CLASS_V, "Vd,Vt,s,VM,VT", 0, (int) M_VMSGEU, match_opcode, INSN_MACRO }, +{"vmsge.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", 0, (int) M_VMSGE, match_never, INSN_MACRO }, +{"vmsge.vx", 0, INSN_CLASS_V, "Vd,Vt,s,VM,VT", 0, (int) M_VMSGE, match_never, INSN_MACRO }, +{"vmsgeu.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", 0, (int) M_VMSGEU, match_never, INSN_MACRO }, +{"vmsgeu.vx", 0, INSN_CLASS_V, "Vd,Vt,s,VM,VT", 0, (int) M_VMSGEU, match_never, INSN_MACRO }, {"vminu.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VMINUVV, MASK_VMINUVV, match_opcode, 0}, {"vminu.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VMINUVX, MASK_VMINUVX, match_opcode, 0}, base-commit: 5e66f55c62e306afbcc93856bf06e542ddd00997 -- 2.41.0