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From: Tsukasa OI <research_trasio@irq.a4lg.com>
To: Tsukasa OI <research_trasio@irq.a4lg.com>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	Andrew Waterman <andrew@sifive.com>,
	Jim Wilson <jim.wilson.gcc@gmail.com>,
	Nelson Chu <nelson@rivosinc.com>,
	Kito Cheng <kito.cheng@sifive.com>
Cc: binutils@sourceware.org
Subject: [PATCH] RISC-V: Prohibit combination of 'E' and 'H'
Date: Tue,  8 Aug 2023 04:16:42 +0000	[thread overview]
Message-ID: <cc00abb4a434cdb7982eb92e3d2ab15868a745d2.1691468158.git.research_trasio@irq.a4lg.com> (raw)

From: Tsukasa OI <research_trasio@irq.a4lg.com>

According to the ratified privileged specification (version 20211203),
it says:

> The hypervisor extension depends on an "I" base integer ISA with 32 x
> registers (RV32I or RV64I), not RV32E, which has only 16 x registers.

Also in the latest draft, it also prohibits RV64E with the 'H' extension.
This commit prohibits the combination of 'E' and 'H' extensions.

bfd/ChangeLog:

	* elfxx-riscv.c (riscv_parse_check_conflicts): Prohibit 'E' and
	'H' combinations.

gas/ChangeLog:

	* testsuite/gas/riscv/march-fail-rv32eh.d: New failure test to
	make sure that RV32E + 'H' is prohibited.
	* testsuite/gas/riscv/march-fail-rv32eh.l: Likewise.
---
 bfd/elfxx-riscv.c                           | 7 +++++++
 gas/testsuite/gas/riscv/march-fail-rv32eh.d | 3 +++
 gas/testsuite/gas/riscv/march-fail-rv32eh.l | 2 ++
 3 files changed, 12 insertions(+)
 create mode 100644 gas/testsuite/gas/riscv/march-fail-rv32eh.d
 create mode 100644 gas/testsuite/gas/riscv/march-fail-rv32eh.l

diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
index ee4598729480..1655bb2df364 100644
--- a/bfd/elfxx-riscv.c
+++ b/bfd/elfxx-riscv.c
@@ -1949,6 +1949,13 @@ riscv_parse_check_conflicts (riscv_parse_subset_t *rps)
 	(_("rv%d does not support the `e' extension"), xlen);
       no_conflict = false;
     }
+  if (riscv_subset_supports (rps, "e")
+      && riscv_subset_supports (rps, "h"))
+    {
+      rps->error_handler
+	(_("rv%de does not support the `h' extension"), xlen);
+      no_conflict = false;
+    }
   if (riscv_lookup_subset (rps->subset_list, "q", &subset)
       && (subset->major_version < 2 || (subset->major_version == 2
 					&& subset->minor_version < 2))
diff --git a/gas/testsuite/gas/riscv/march-fail-rv32eh.d b/gas/testsuite/gas/riscv/march-fail-rv32eh.d
new file mode 100644
index 000000000000..b57199efa0f6
--- /dev/null
+++ b/gas/testsuite/gas/riscv/march-fail-rv32eh.d
@@ -0,0 +1,3 @@
+#as: -march=rv32eh
+#source: empty.s
+#error_output: march-fail-rv32eh.l
diff --git a/gas/testsuite/gas/riscv/march-fail-rv32eh.l b/gas/testsuite/gas/riscv/march-fail-rv32eh.l
new file mode 100644
index 000000000000..c7cd1ccc2a89
--- /dev/null
+++ b/gas/testsuite/gas/riscv/march-fail-rv32eh.l
@@ -0,0 +1,2 @@
+.*Assembler messages:
+.*Error: .*rv32e does not support the `h' extension

base-commit: d734d43a048b33ee12df2c06c2e782887e9715f6
-- 
2.41.0


             reply	other threads:[~2023-08-08  4:16 UTC|newest]

Thread overview: 4+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-08-08  4:16 Tsukasa OI [this message]
2023-08-30  4:12 ` [PING^1][PATCH] " Tsukasa OI
2023-09-05  1:14   ` Nelson Chu
2023-09-05  1:43     ` Tsukasa OI

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