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Lu" Cc: binutils@sourceware.org References: <20221203041307.34407-1-hjl.tools@gmail.com> <88604f9d-1cc7-0c05-c92e-2561512dc96e@suse.com> <3977276e-762c-661e-6b0d-f757debb5ae0@suse.com> <1ae3e9f1-1207-50ea-7d25-ec7154f739bb@suse.com> <9508b3e4-fef3-2e37-27ae-7c9f48508116@suse.com> From: Jan Beulich In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-ClientProxiedBy: FR0P281CA0055.DEUP281.PROD.OUTLOOK.COM (2603:10a6:d10:49::15) To VE1PR04MB6560.eurprd04.prod.outlook.com (2603:10a6:803:122::25) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: VE1PR04MB6560:EE_|AS8PR04MB8674:EE_ X-MS-Office365-Filtering-Correlation-Id: 6dbaf5fa-8d74-4b75-dc20-08dad8ef427c X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: Wl0OenFX2i2Uh6i65qelNxJRsxFoZkQDNsJ/m4oSN6hMmFM8KJB7uM2VSftOeQYDOeLm+e5m67/j+h1lIgWDjPMyrw5Td71vq3lh2hv7ZYDZ+gCOF91YUJ6MKLZvQYIUzqY5i+3tLimJExVC+8uI05EY/MF9JfwWs+Z5KnfXbu5KRh2SNg+uf+Untcgza/7hya0OCFHhJrldUOWndhTnKdkYKkVcc/rY4aqZAzKVNYI+9r3wlp2CqZKxeq1Ss6Sy4DVex0m5JIOnxckFGCNMeKRZWXGu2hKHBQnO9U+PVoAyW/baLI0igtNXqFITCkgl/dt4VBVUKyliy+P+OWaHACX7C6OveNjHGljISy4C+qO/s9OUDcuYz/7pCv1ef4jjBOKLEam45QJ2SYqazg4Co+h1D3htGWha2tVYpi2WBts2JQg3/41S29hUMwgzNoHfgIkW0Nkyzs1sLH3JrV6TBm/NHzOnaAK8ffHXE7HMHjJzCUpqGREUivFOK+MWOUGGGrsRKdWeCZX+kG5nyx8WUdM4TaBnZ8697HnQ7CFTbARQptrcM+Z0/prw8ixI68+nuTS7z2FgSXG2dwdWSeFWBCn8zwTv5e2RQaZxbJX2AUzsOPwf6cUMXEjoA/A8U2WcmA8+l2cXRbHXq+HLOl+xy+EG+RSMPD6xwIzWxEmcyZcUFLoD5+MsmfN1kevWxNANrJNyTFdn7bbdXctP71a6OTe3BXjEp+DB4nYmMukwDLs= X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:VE1PR04MB6560.eurprd04.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230022)(376002)(366004)(396003)(39860400002)(136003)(346002)(451199015)(83380400001)(2616005)(186003)(86362001)(31696002)(2906002)(38100700002)(5660300002)(8936002)(53546011)(6512007)(26005)(6486002)(478600001)(66946007)(6506007)(66556008)(66476007)(4326008)(8676002)(316002)(41300700001)(6916009)(36756003)(31686004)(43740500002)(45980500001);DIR:OUT;SFP:1101; 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Lu wrote: > On Wed, Dec 7, 2022 at 2:47 AM Jan Beulich wrote: >> >> On 06.12.2022 23:32, H.J. Lu wrote: >>> On Tue, Dec 6, 2022 at 8:36 AM Jan Beulich wrote: >>>> >>>> On 06.12.2022 17:11, H.J. Lu wrote: >>>>> On Mon, Dec 5, 2022 at 11:51 PM Jan Beulich wrote: >>>>>> >>>>>> On 06.12.2022 00:20, H.J. Lu wrote: >>>>>>> On Mon, Dec 5, 2022 at 3:11 AM Jan Beulich wrote: >>>>>>>> >>>>>>>> On 03.12.2022 05:13, H.J. Lu wrote: >>>>>>>>> Since LAR and LSL only access 16 bits of the source operand, regardless >>>>>>>>> of operand size, allow 16-bit register source for LAR and LSL, and always >>>>>>>>> disassemble LAR and LSL with 16-bit source operand. >>>>>>>>> >>>>>>>>> gas/ >>>>>>>>> >>>>>>>>> PR gas/29844 >>>>>>>>> * testsuite/gas/i386/i386.s: Add tests for LAR and LSL. >>>>>>>>> * testsuite/gas/i386/x86_64.s: Likewise. >>>>>>>>> * testsuite/gas/i386/intelbad.s: Remove "lar/lsl eax, ax". >>>>>>>>> * testsuite/gas/i386/i386-intel.d: Updated. >>>>>>>>> * testsuite/gas/i386/i386.d: Likewise. >>>>>>>>> * testsuite/gas/i386/intel-intel.d: Likewise. >>>>>>>>> * testsuite/gas/i386/intel.d: Likewise. >>>>>>>>> * testsuite/gas/i386/intelbad.l: Likewise. >>>>>>>>> * testsuite/gas/i386/x86_64-intel.d: Likewise. >>>>>>>>> * testsuite/gas/i386/x86_64.d: Likewise. >>>>>>>>> >>>>>>>>> opcodes/ >>>>>>>>> >>>>>>>>> PR gas/29844 >>>>>>>>> * i386-dis.c (MOD_0F02): Removed. >>>>>>>>> (MOD_0F03): Likewise. >>>>>>>>> (dis386_twobyte): Restore larS and lslS. >>>>>>>>> (mod_table): Remove MOD_0F02 and MOD_0F03. >>>>>>>>> * i386-opc.tbl: Allow 16-bit register source for LAR and LSL. >>>>>>>>> * i386-tbl.h: Regenerated. >>>>>>>> >>>>>>>> Please can you refrain from immediately committing patches which have >>>>>>>> a risk of being controversial. >>>>>>>> >>>>>>>> In the case here, given there are uses of the 16-bit register operand >>>>>>>> form in the Linux kernel, I can accept the assembler part of the change. >>>>>>>> The lines in i386-opc.tbl, however, need a comment then, as allowing for >>>>>>>> 16-bit registers despite a wider destination is explicitly not in line >>>>>>>> with the SDM. (Interestingly AMD's PM is different in this regard.) >>>>>>>> >>>>>>>> For the disassembler part you're completely undoing what I did, which is >>>>>>>> wrong - again with reference to the SDM. If you want to accommodate for >>>>>>>> AMD's PM, then you need to vary disassembly according to command line >>>>>>>> options specified, with the default being in line with the SDM (I can >>>>>>>> dig out a pretty old version of the doc, but I believe it has always >>>>>>>> been that way, i.e. even before AMD introduced their clones). >>>>>>>> >>>>>>>> I will revert this change unless you come forward with an adjustment >>>>>>>> within the next couple of days. >>>>>>>> >>>>>>> >>>>>>> Given that the only lower 16 bits are used, the 16-bit register source >>>>>>> is more appropriate. I will raise the issue with the Intel SDM author. >>>>>> >>>>>> I see no point in changing the documentation when what's there has been >>>>>> valid for well over 30 years. There are other cases in newer insns where >>>>>> only the low 16 (or 8) bits are used, yet still the 32-bit register name >>>>>> is specified ({,v}pinsr{b,w} come to mind immediately). Also what you've >>>>>> done brought things out of sync with mov-to-sreg (and no, please don't >>>>>> "restore" consistency by also changing disassembly there). >>>>> >>>>> The 16-bit register has been used in both assembler and disassembler >>>>> for well over 30 years. I consider this a flaw in the spec. >>>> >>>> And a flaw in disassembly of move-to-sreg (and maybe other insns)? >>>> Is the spec then also wrong with {,v}pinsr{b,w}? Also note that >>>> while the assembler wants to provide backwards compatibility, the >>>> same is rarely necessary for the disassembler. Hence what it may >>>> or may not have done for over 30 years doesn't really matter. >>>> >>>> Please can we avoid introducing further inconsistencies, and rather >>>> work towards more consistency (and not by then also corrupting >>>> move-to-sreg and possible other insns)? >>>> >>> >>> I have a different view on "inconsistencies". For LAR/LSL, they >>> are different: >>> >>> 1. All operands are integer registers. >>> 2. The operand size prefix doesn't apply to the source. >>> 3. Only the 16 bits of the source are used. >> >> 2 and 3 are true for move-to-sreg and {,v}pinsr{b,w} as well. >> >>> 4. 16 bit source has been in use for more than 30 years. >>> >>> What counts are how the processor behaves >> >> Which means we have further things to fix: For example LTR and LLDT, >> like move-to-sreg, also accept 32- or 64-bit register operands, >> silently ignoring the upper bits. The assembler wants to accept such >> for consistency (even if the SDM doesn't name these variants), and >> the disassembler wants to express operand size by picking the correct >> register name (didn't check if it maybe already does). >> >> This "picking the correct register name" applies to both operands of >> LAR and LSL just as much. > > We have different opinions on what "the correct register name" > should be. Indeed - hence why the patch should never have been committed. Recall you did approve of the earlier patch, which now you've partially reverted without even saying so in your commit? Which is made even worse by the fact that to address PR gas/29844 there was no need at all to also touch the disassembler, i.e. you've mixed in a single commit two entirely separate changes (one controversial, the other not). > When there are more than one integer registers > and the operand size prefix is ignored on one, the register > name with the proper size is the correct register name. Quite differently: Except where necessary (MOVSX, MOVZX, CRC32), register sizes ought to match so there are as few anomalies as possible throughout the entire ISA. With non-matching register sizes it'll be easily ambiguous what an insn's operand size actually is. Jan