From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-sender-0.a4lg.com (mail-sender.a4lg.com [153.120.152.154]) by sourceware.org (Postfix) with ESMTPS id 3DF0C3858D35 for ; Sun, 27 Feb 2022 08:51:14 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 3DF0C3858D35 Received: from [127.0.0.1] (localhost [127.0.0.1]) by mail-sender-0.a4lg.com (Postfix) with ESMTPSA id 458A7300089; Sun, 27 Feb 2022 08:51:11 +0000 (UTC) From: Tsukasa OI To: Tsukasa OI , Palmer Dabbelt , Nelson Chu , Jan Beulich Cc: binutils@sourceware.org Subject: [PATCH v2 0/1] RISC-V: Fix RV32Q conflict Date: Sun, 27 Feb 2022 17:51:03 +0900 Message-Id: In-Reply-To: References: Mime-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-5.4 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, FROM_FMBLA_NEWDOM, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=no autolearn_force=no version=3.4.4 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on server2.sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 27 Feb 2022 08:51:16 -0000 [v2] This commit allows combination of RV32 + 'Q' extension (IEEE 754 binary128 floating point number support), version 2.2 or later. This combination is no longer prohibited by the specification. v1: Changes: v1 -> v2 - Changed/renamed testcase so that no failure occurs. RV32IQ with old ISA (version 2.2 w/ 'Q' 2.0) is prohibited. - Added testcase so that RV32IQ with recent ISA succeeds. RV32IQ with new ISA (version 20190608 w/ 'Q' 2.2) is allowed. - Added testcases for RV32I + 'Q' per extension version - 'Q' extension version 2.0 with RV32I is prohibited. ("rv32iq2" means RV32I + Q version 2".0" so also prohibited.) - 'Q' extension version 2.2 with RV32I is allowed. As I noted in v1, this implementation might be too pedantic. An option is to allow RV32IQ entirely (regardless of version numbers). Tsukasa OI (1): RISC-V: Fix RV32Q conflict bfd/elfxx-riscv.c | 5 +++-- gas/testsuite/gas/riscv/march-fail-rv32iq-isa-2p2.d | 3 +++ gas/testsuite/gas/riscv/march-fail-rv32iq.d | 3 --- gas/testsuite/gas/riscv/march-fail-rv32iq2.d | 3 +++ gas/testsuite/gas/riscv/march-fail-rv32iq2p0.d | 3 +++ .../riscv/{march-fail-rv32iq.l => march-fail-rv32iq2p0.l} | 0 gas/testsuite/gas/riscv/march-ok-rv32iq-isa-20190608.d | 5 +++++ gas/testsuite/gas/riscv/march-ok-rv32iq2p2.d | 5 +++++ 8 files changed, 22 insertions(+), 5 deletions(-) create mode 100644 gas/testsuite/gas/riscv/march-fail-rv32iq-isa-2p2.d delete mode 100644 gas/testsuite/gas/riscv/march-fail-rv32iq.d create mode 100644 gas/testsuite/gas/riscv/march-fail-rv32iq2.d create mode 100644 gas/testsuite/gas/riscv/march-fail-rv32iq2p0.d rename gas/testsuite/gas/riscv/{march-fail-rv32iq.l => march-fail-rv32iq2p0.l} (100%) create mode 100644 gas/testsuite/gas/riscv/march-ok-rv32iq-isa-20190608.d create mode 100644 gas/testsuite/gas/riscv/march-ok-rv32iq2p2.d base-commit: b275570803cefba388595bc42b75b68403eb86f1 -- 2.32.0