From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-sender-0.a4lg.com (mail-sender.a4lg.com [153.120.152.154]) by sourceware.org (Postfix) with ESMTPS id 7690C3858D32 for ; Sat, 30 Jul 2022 03:51:15 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 7690C3858D32 Received: from [127.0.0.1] (localhost [127.0.0.1]) by mail-sender-0.a4lg.com (Postfix) with ESMTPSA id BD21F300089; Sat, 30 Jul 2022 03:51:13 +0000 (UTC) From: Tsukasa OI To: Tsukasa OI , Nelson Chu , Palmer Dabbelt , Kito Cheng Cc: binutils@sourceware.org Subject: [PATCH 0/1] RISC-V: Check shift amount against XLEN (disassembler) Date: Sat, 30 Jul 2022 12:51:11 +0900 Message-Id: In-Reply-To: References: Mime-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-6.4 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sat, 30 Jul 2022 03:51:16 -0000 Hello, This patchset is going to support shift amount checking on the disassembler. Previous Patchset: Tracker on GitHub: In the disassembler, there's no validation whether shift amount is valid on the specific architecture (RV32/64). My previous Idea 1 patchset tried to fix that by adding xlen argument to every match_func (in opcode entries). However, it requires bigger core disassembler changes and maintaining is relatively hard. Idea 2 patchset (this patchset) fixes that by printing invalid0x[SHAMT] instead of actual shift width (SHAMT in hexadecimal like regular shift amounts). If we don't have to print "unrecognized instruction" (such as .4byte) on instrucitons with invalid shift amounts, this patch would be the simplest solution for the invalid shift amount checking support on the disassembler. This patchset supports styling. invalid shift amounts are printed as text, not immediate. It makes invalid shift amounts default white opposed to blue on valid ones. See an example with the GitHub Wiki page linked above. Thanks, Tsukasa Tsukasa OI (1): RISC-V: Check shift amount against XLEN (disasm) gas/testsuite/gas/riscv/shamt-dis-32.d | 34 +++++++++++++++++++ gas/testsuite/gas/riscv/shamt-dis-64.d | 34 +++++++++++++++++++ gas/testsuite/gas/riscv/shamt-dis.s | 47 ++++++++++++++++++++++++++ opcodes/riscv-dis.c | 16 ++++++--- 4 files changed, 127 insertions(+), 4 deletions(-) create mode 100644 gas/testsuite/gas/riscv/shamt-dis-32.d create mode 100644 gas/testsuite/gas/riscv/shamt-dis-64.d create mode 100644 gas/testsuite/gas/riscv/shamt-dis.s base-commit: b245c595aaa59812f8f3a0e8b70ea5f52e045627 -- 2.34.1