From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-sender-0.a4lg.com (mail-sender-0.a4lg.com [IPv6:2401:2500:203:30b:4000:6bfe:4757:0]) by sourceware.org (Postfix) with ESMTPS id 012E73858D39 for ; Fri, 12 Aug 2022 03:40:45 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 012E73858D39 Received: from [127.0.0.1] (localhost [127.0.0.1]) by mail-sender-0.a4lg.com (Postfix) with ESMTPSA id 45D81300089; Fri, 12 Aug 2022 03:40:44 +0000 (UTC) From: Tsukasa OI To: Tsukasa OI , Nelson Chu , Kito Cheng , Palmer Dabbelt Cc: binutils@sourceware.org Subject: [PATCH v2 0/2] RISC-V psABI: Assign DWARF register numbers to vector registers Date: Fri, 12 Aug 2022 12:40:41 +0900 Message-Id: In-Reply-To: References: Mime-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-6.4 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 12 Aug 2022 03:40:47 -0000 Hi! [Changes: v1 -> v2] Remove invented word "VPRs" (at least it has no consistent uses in the RISC-V ecosystem) and replaced with "Vector registers" Surprisingly, I found that no vector registers (v0-v31) are assigned DWARF register numbers. RISC-V ABIs Specification (riscv-elf-psabi-doc) is not ratified yet but at least frozen. So, I consider it's stable to upstream it. According to the documentation, it has register numbers 96 (v0) - 127 (v31). Tracker on GitHub: v1: RISC-V ABIs Specification Version 1.0-rc3: Frozen I also added DWARF register number tests not just for CSRs (existing) and vector registers (I just added), but also for GPRs (0-31) and FPRs (32-63). [REQUEST FOR COMMENTS] Is "v0.t" should be assigned a DWARF register number 96 (same as "v0")? I did not add this but adding it might be an option. Thanks, Tsukasa Tsukasa OI (2): RISC-V: Assign DWARF numbers to vector registers RISC-V: Add testcase for DWARF register numbers binutils/dwarf.c | 28 ++-- gas/config/tc-riscv.c | 3 + gas/testsuite/gas/riscv/dw-regnums.d | 180 ++++++++++++++++++++++++++ gas/testsuite/gas/riscv/dw-regnums.s | 184 +++++++++++++++++++++++++++ 4 files changed, 385 insertions(+), 10 deletions(-) create mode 100644 gas/testsuite/gas/riscv/dw-regnums.d create mode 100644 gas/testsuite/gas/riscv/dw-regnums.s base-commit: 906dca17d429f468d49a6cc4753993581c51a899 -- 2.34.1