From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-sender-0.a4lg.com (mail-sender.a4lg.com [153.120.152.154]) by sourceware.org (Postfix) with ESMTPS id 1018C3851A94; Wed, 31 Aug 2022 02:15:39 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 1018C3851A94 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=irq.a4lg.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=irq.a4lg.com Received: from [127.0.0.1] (localhost [127.0.0.1]) by mail-sender-0.a4lg.com (Postfix) with ESMTPSA id 37859300089; Wed, 31 Aug 2022 02:15:37 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=irq.a4lg.com; s=2017s01; t=1661912137; bh=QKTK4h55Pp2ACA+wpB7KulEXF+0NFs0jzI7VtvhZnYE=; h=From:To:Cc:Subject:Date:Message-Id:Mime-Version: Content-Transfer-Encoding; b=o5gMe9K6fvYwoVR/GoJAnu3ZEEFiC7RbfZOtcNa/m0B4lDrdaXJtEWNMZzGEuxCtt TCxaurRAVjcAjr2TSTb1GYmZUBPqoyOhv0XGIYR5hg+nVKn8WIhpdi6iYZ6/7iL4QJ 2Rpm2aVlINg/liSa5xBabsumxTsme9pbeqTERPIM= From: Tsukasa OI To: Tsukasa OI , Andrew Burgess , Palmer Dabbelt , Claudiu Zissulescu , Chenghua Xu , Nelson Chu Cc: binutils@sourceware.org, gdb-patches@sourceware.org Subject: [PATCH 0/2] gdb, opcodes: Add non-enum disassembler options Date: Wed, 31 Aug 2022 02:15:30 +0000 Message-Id: Mime-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-6.3 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,KAM_MANYTO,SPF_HELO_NONE,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: Hello, This is a part of my work: implement `arch' disassembler option in RISC-V. However, it requires technical changes also affecting opcodes:ARC and MIPS and GDB. It will take some time because we have to wait many Binutils prerequisites but this technical change can be discussed now (due to it affects both Binutils and GDB). PATCH 1/2: Binutils changes PATCH 2/2: GDB changes Independently applying Binutils/GDB changes is completely safe because we haven't implemented any actual non-enum options. [Example: Implement `arch' disassembler option] $ objdump -b binary -m riscv:rv32 -M arch=rv32i_zfinx -D sample.bin (... analyze a binary file with 'RV32I_Zfinx' ISA) You can try my modified version at: [Technical Changes] There is a portable mechanism for disassembler options and used on some architectures: - ARC - Arm - MIPS - PowerPC - RISC-V - S/390 However, it only supports following forms: - [NAME] - [NAME]=[ENUM_VALUE] Valid values for [ENUM_VALUE] must be predefined in `disasm_option_arg_t.values'. For instance, for -M cpu=[CPU] in ARC architecture, opcodes/arc-dis.c builds valid CPU model list from include/elf/arc-cpu.def. This patchset adds following third format: - [NAME]=[ARBITRARY_VALUE] (cannot contain "," though) This is identified by `NULL' value of `disasm_option_arg_t.values' (normally, this is a non-NULL pointer to a NULL-terminated list). Note that this patch modifies following architectures (that use similar code to print disassembler help message) for consistency: - ARC - MIPS - RISC-V In the future, adding "verify" function to disasm_option_arg_t (or some) might be an option as it may provide flexible argument validation. Thanks, Tsukasa Tsukasa OI (2): opcodes: Add non-enum disassembler options gdb: Add non-enum disassembler options gdb/disasm.c | 4 ++++ include/dis-asm.h | 3 ++- opcodes/arc-dis.c | 2 ++ opcodes/mips-dis.c | 2 ++ opcodes/riscv-dis.c | 2 ++ 5 files changed, 12 insertions(+), 1 deletion(-) base-commit: 803584b96d97e1f6ea50b0a0064d2a03ab0baa60 -- 2.34.1