From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-sender-0.a4lg.com (mail-sender-0.a4lg.com [IPv6:2401:2500:203:30b:4000:6bfe:4757:0]) by sourceware.org (Postfix) with ESMTPS id 3E3973858D1E for ; Thu, 8 Sep 2022 06:53:56 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 3E3973858D1E Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=irq.a4lg.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=irq.a4lg.com Received: from [127.0.0.1] (localhost [127.0.0.1]) by mail-sender-0.a4lg.com (Postfix) with ESMTPSA id EEA67300089; Thu, 8 Sep 2022 06:53:53 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=irq.a4lg.com; s=2017s01; t=1662620034; bh=CMa+UedUHY3y2vlgOzfxt+cIH8rtiCPMT+2Bfuby2pQ=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: Mime-Version:Content-Transfer-Encoding; b=ZbbJ49yanwDaAhu2oLmihcePXr8Q3MpaEmawZXXgIkCQ7f1iQTl7+3XANRqY7YHLf gXU8V19h5q1BkmVLrSOoObg8kmgmvL2dkPX592VSpfUjsvQGCczW3RgCQSysdGj69j wAH0SpasJC+mPZ5TX0BpWOJM1TZRsnXW3MPSEFw0= From: Tsukasa OI To: Tsukasa OI , Nelson Chu , Kito Cheng , Palmer Dabbelt Cc: binutils@sourceware.org Subject: [PATCH 0/1] RISC-V: Fix CSR accessibility on vectors Date: Thu, 8 Sep 2022 06:53:38 +0000 Message-Id: In-Reply-To: References: Mime-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-6.4 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,SPF_HELO_NONE,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: Tracker on GitHub: Previous: This is a subset of previous CSR accessibility and implication patchset. It seems making requirement of CSR_CLASS_V from 'V' to 'Zve32x' is less debatable, I splitted this part as a separate patchset. (Not strictly a subset; I added CSR accessibility test for 'V') An excerpt (slightly modified) from previous cover letter follows: On the current version of GNU Binutils, CSRs with CSR_CLASS_V means they require the 'V' extension. However, there are a few vector subextensions that implement vector subsets (intended for embedded processors). - 'Zve64d' (superset of 'Zve64f') - 'Zve64f' (superset of 'Zve32f' and 'Zve64x') - 'Zve64x' (superset of 'Zve32x') - 'Zve32f' (superset of 'Zve32x') - 'Zve32x' | Graph: Dependency graph of some vector/FP extensions and Zicsr | | +-------> D ---+----> F -----> Zicsr | | ^ | ^ | | | / | | V ---> Zve64d ---> Zve64f ---> Zve64x | \ | | | | V V | +-- Zve32f ---> Zve32x | | | | | +---> (Zicsr [should be added?]) They also require general purpose vector CSRs (vstart, vl, vtype and vlenb). So, corresponding CSR_CLASS_V with the 'V' extension is inappropriate (they should require 'Zve32x' instead, the minimum vector subset). Remaining CSRs are: - vxsat - vxrm - vcsr They are related to fixed-point arithmetic and 18.2 "Zve*: Vector Extensions for Embedded Processors" says: > All Zve* extensions support all vector fixed-point arithmetic instructions > (Vector Fixed-Point Arithmetic Instructions), except that vsmul.vv and > vsmul.vx are not supported for EEW=64 in Zve64*. So, their minimum requirement shall be also 'Zve32x', not 'V'. As a consequence, we can conclude that changing requirements of CSR_CLASS_V from 'V' to 'Zve32x' is sufficient to avoid CSR accessibility warnings. I didn't rename CSR_CLASS_V to CSR_CLASS_ZVE32X because the name gets difficult and there's already INSN_CLASS_V (effectively requires 'Zve32x' with some exceptions). Tsukasa OI (1): RISC-V: Fix vector CSR requirements gas/config/tc-riscv.c | 2 +- gas/testsuite/gas/riscv/csr-version-1p10.l | 28 ++++++++++---------- gas/testsuite/gas/riscv/csr-version-1p11.l | 28 ++++++++++---------- gas/testsuite/gas/riscv/csr-version-1p12.l | 28 ++++++++++---------- gas/testsuite/gas/riscv/csr-version-1p9p1.l | 28 ++++++++++---------- gas/testsuite/gas/riscv/vector-csrs-v.d | 21 +++++++++++++++ gas/testsuite/gas/riscv/vector-csrs-zve32f.d | 21 +++++++++++++++ gas/testsuite/gas/riscv/vector-csrs-zve32x.d | 21 +++++++++++++++ gas/testsuite/gas/riscv/vector-csrs-zve64d.d | 21 +++++++++++++++ gas/testsuite/gas/riscv/vector-csrs-zve64f.d | 21 +++++++++++++++ gas/testsuite/gas/riscv/vector-csrs-zve64x.d | 21 +++++++++++++++ gas/testsuite/gas/riscv/vector-csrs.s | 12 +++++++++ 12 files changed, 195 insertions(+), 57 deletions(-) create mode 100644 gas/testsuite/gas/riscv/vector-csrs-v.d create mode 100644 gas/testsuite/gas/riscv/vector-csrs-zve32f.d create mode 100644 gas/testsuite/gas/riscv/vector-csrs-zve32x.d create mode 100644 gas/testsuite/gas/riscv/vector-csrs-zve64d.d create mode 100644 gas/testsuite/gas/riscv/vector-csrs-zve64f.d create mode 100644 gas/testsuite/gas/riscv/vector-csrs-zve64x.d create mode 100644 gas/testsuite/gas/riscv/vector-csrs.s base-commit: f42546b6cc7468ac7d929181ed7b965ab60958ac -- 2.34.1