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From: Tsukasa OI <research_trasio@irq.a4lg.com>
To: Tsukasa OI <research_trasio@irq.a4lg.com>
Cc: binutils@sourceware.org
Subject: [REVIEW ONLY 0/1] RISC-V (unratified): Add 'Zfa' extension
Date: Sun, 18 Sep 2022 10:12:50 +0000	[thread overview]
Message-ID: <cover.1663495968.git.research_trasio@irq.a4lg.com> (raw)

*** WAIT FOR SPECIFICATION FREEZE ***
This is an implementation for unratified and unfrozen RISC-V extension
and not intended to be merged as of now.
The only intent to submit this patchset is to test new instructions for
your (possibly virtual) environment and early review for fast adoption
after ratification.


[Cover Letter: Common in 'Zihintntl' and 'Zfa' patchsets]

As someone (I can't remember) pointed out in the RISC-V BoF of GNU Tools
Cauldron 2022, we don't have a policy to accept unstable extensions yet.
Still, at least we can talk about new extensions now...

1.  To try new instructions/features as fast as possible,
2.  To make actual adoption as fast as possible and
3.  To avoid redoing someone else's work

I'm working on following unratified RISC-V extensions:

1.  'Zihintntl' [resent as v2]
    <https://github.com/a4lg/binutils-gdb/wiki/riscv_zihintntl>
    <https://sourceware.org/pipermail/binutils/2022-July/121682.html>
2.  'Smrnmi' (resumable NMI)
    <https://github.com/a4lg/binutils-gdb/wiki/riscv_smrnmi>
    <https://sourceware.org/pipermail/binutils/2022-July/121689.html>
3.  'Zfa' [NEW]
    <https://github.com/a4lg/binutils-gdb/wiki/riscv_zfa>

I will resend 'Zihintntl' (squashed and applied minor formatting fixes)
and submit new 'Zfa' extension as a remainder of what am I doing.



['Zfa': Standard Extension for Additional Floating-Point Instructions]

This draft standard extension implements:

-   Load immediate instructions
    (allows to load 32 floating point constants)
-   IEEE 754-2019 operations
-   Modular Convert-to-Integer Instruction
    (to accelerate JavaScript Number handling)
-   Move instructions
    (RV32D/RV64Q: move high part)

This is based on:
<https://github.com/riscv/riscv-isa-manual/commit/ae683aec28ec707a3c4bb6f588491f0840d52f43>
(latest commit of the 'zfb' branch as of this writing)

Note that this extension is still highly unstable (except encoding).



[RFC: Adding another character operand prefix?]

Also, it will raise another issue.  It adds an operand type solely for
FLI.[HSDQ] instructions.  This is absolutely necessary because the spec
requires to accept either:

-   Decimal values: 0...29
    (I talked to Andrew and he considers accepting complex expression
    [not just decimal constants] is harmless)
-   Special operands:
    -   "min" (encoded as  1; 1 is also acceptable)
    -   "inf" (encoded as 30; invalid as a constant)
    -   "nan" (encoded as 31; invalid as a constant)

We may need to allocate a prefix for less common operands to avoid
filling the first-class character space with such minor ones.  I tentatively
propose 'W' for this purpose.

Example:
'Zicbop' PREFETCH.[IRW] : 'f' -> "Wf"
         (fetch offset)
'Zfa'    FLI.[HSDQ]     : 'i' -> "Wv"
         (value to load)


Thanks,
Tsukasa




Tsukasa OI (1):
  UNRATIFIED RISC-V: Add 'Zfa' extension

 bfd/elfxx-riscv.c                             | 39 ++++++++
 gas/config/tc-riscv.c                         | 21 ++++
 gas/testsuite/gas/riscv/zfa-32.d              | 10 ++
 gas/testsuite/gas/riscv/zfa-32.s              |  3 +
 gas/testsuite/gas/riscv/zfa-64.d              | 10 ++
 gas/testsuite/gas/riscv/zfa-64.s              |  3 +
 .../gas/riscv/zfa-fail-fcvtmod.w.d.d          |  3 +
 .../gas/riscv/zfa-fail-fcvtmod.w.d.l          |  8 ++
 .../gas/riscv/zfa-fail-fcvtmod.w.d.s          | 11 +++
 gas/testsuite/gas/riscv/zfa-fail-fli.d        |  3 +
 gas/testsuite/gas/riscv/zfa-fail-fli.l        | 21 ++++
 gas/testsuite/gas/riscv/zfa-fail-fli.s        | 21 ++++
 gas/testsuite/gas/riscv/zfa.d                 | 93 +++++++++++++++++
 gas/testsuite/gas/riscv/zfa.s                 | 92 +++++++++++++++++
 include/opcode/riscv-opc.h                    | 99 +++++++++++++++++++
 include/opcode/riscv.h                        |  5 +
 opcodes/riscv-dis.c                           |  7 ++
 opcodes/riscv-opc.c                           | 52 +++++++++-
 18 files changed, 500 insertions(+), 1 deletion(-)
 create mode 100644 gas/testsuite/gas/riscv/zfa-32.d
 create mode 100644 gas/testsuite/gas/riscv/zfa-32.s
 create mode 100644 gas/testsuite/gas/riscv/zfa-64.d
 create mode 100644 gas/testsuite/gas/riscv/zfa-64.s
 create mode 100644 gas/testsuite/gas/riscv/zfa-fail-fcvtmod.w.d.d
 create mode 100644 gas/testsuite/gas/riscv/zfa-fail-fcvtmod.w.d.l
 create mode 100644 gas/testsuite/gas/riscv/zfa-fail-fcvtmod.w.d.s
 create mode 100644 gas/testsuite/gas/riscv/zfa-fail-fli.d
 create mode 100644 gas/testsuite/gas/riscv/zfa-fail-fli.l
 create mode 100644 gas/testsuite/gas/riscv/zfa-fail-fli.s
 create mode 100644 gas/testsuite/gas/riscv/zfa.d
 create mode 100644 gas/testsuite/gas/riscv/zfa.s


base-commit: 4e38ed582cb9a2e09141126c2e0a527816e702e6
-- 
2.34.1


             reply	other threads:[~2022-09-18 10:12 UTC|newest]

Thread overview: 10+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-09-18 10:12 Tsukasa OI [this message]
2022-09-18 10:12 ` [REVIEW ONLY 1/1] UNRATIFIED RISC-V: " Tsukasa OI
2023-03-22 15:47   ` Christoph Müllner
2023-03-22 16:01     ` Philipp Tomsich
2023-03-22 16:07     ` Tsukasa OI
2023-03-22 16:21       ` Christoph Müllner
2023-03-22 17:00         ` Tsukasa OI
2023-03-23 13:17           ` Kito Cheng
2023-03-26 15:43     ` Jeff Law
2023-03-27  0:13       ` Philipp Tomsich

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