From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-sender-0.a4lg.com (mail-sender.a4lg.com [153.120.152.154]) by sourceware.org (Postfix) with ESMTPS id 787B13857B80 for ; Sun, 18 Sep 2022 10:12:56 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 787B13857B80 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=irq.a4lg.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=irq.a4lg.com Received: from [127.0.0.1] (localhost [127.0.0.1]) by mail-sender-0.a4lg.com (Postfix) with ESMTPSA id 4C3EB300089; Sun, 18 Sep 2022 10:12:54 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=irq.a4lg.com; s=2017s01; t=1663495974; bh=YpvzMyUQBh7fzKqhpmd9mxjd05LrT7aYkBqGtORCA38=; h=From:To:Cc:Subject:Date:Message-Id:Mime-Version: Content-Transfer-Encoding; b=FZzi+Y0fTBmQPHFNZAD1IYReUGGYluYafHQrR0Kw4BmzxqRVTciiBhH8KHMNUlQfA LwhyrsVc/X3J2GGiUzxQFZXAOCc/jrppRtZ+ZavZGdWruw4tmBmbKvI9ilMBFVL8TM 6FzlQQdP8HDEd6uyCWejuwgF8lVQgG8HONE4XBck= From: Tsukasa OI To: Tsukasa OI Cc: binutils@sourceware.org Subject: [REVIEW ONLY 0/1] RISC-V (unratified): Add 'Zfa' extension Date: Sun, 18 Sep 2022 10:12:50 +0000 Message-Id: Mime-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-6.2 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,SPF_HELO_NONE,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: *** WAIT FOR SPECIFICATION FREEZE *** This is an implementation for unratified and unfrozen RISC-V extension and not intended to be merged as of now. The only intent to submit this patchset is to test new instructions for your (possibly virtual) environment and early review for fast adoption after ratification. [Cover Letter: Common in 'Zihintntl' and 'Zfa' patchsets] As someone (I can't remember) pointed out in the RISC-V BoF of GNU Tools Cauldron 2022, we don't have a policy to accept unstable extensions yet. Still, at least we can talk about new extensions now... 1. To try new instructions/features as fast as possible, 2. To make actual adoption as fast as possible and 3. To avoid redoing someone else's work I'm working on following unratified RISC-V extensions: 1. 'Zihintntl' [resent as v2] 2. 'Smrnmi' (resumable NMI) 3. 'Zfa' [NEW] I will resend 'Zihintntl' (squashed and applied minor formatting fixes) and submit new 'Zfa' extension as a remainder of what am I doing. ['Zfa': Standard Extension for Additional Floating-Point Instructions] This draft standard extension implements: - Load immediate instructions (allows to load 32 floating point constants) - IEEE 754-2019 operations - Modular Convert-to-Integer Instruction (to accelerate JavaScript Number handling) - Move instructions (RV32D/RV64Q: move high part) This is based on: (latest commit of the 'zfb' branch as of this writing) Note that this extension is still highly unstable (except encoding). [RFC: Adding another character operand prefix?] Also, it will raise another issue. It adds an operand type solely for FLI.[HSDQ] instructions. This is absolutely necessary because the spec requires to accept either: - Decimal values: 0...29 (I talked to Andrew and he considers accepting complex expression [not just decimal constants] is harmless) - Special operands: - "min" (encoded as 1; 1 is also acceptable) - "inf" (encoded as 30; invalid as a constant) - "nan" (encoded as 31; invalid as a constant) We may need to allocate a prefix for less common operands to avoid filling the first-class character space with such minor ones. I tentatively propose 'W' for this purpose. Example: 'Zicbop' PREFETCH.[IRW] : 'f' -> "Wf" (fetch offset) 'Zfa' FLI.[HSDQ] : 'i' -> "Wv" (value to load) Thanks, Tsukasa Tsukasa OI (1): UNRATIFIED RISC-V: Add 'Zfa' extension bfd/elfxx-riscv.c | 39 ++++++++ gas/config/tc-riscv.c | 21 ++++ gas/testsuite/gas/riscv/zfa-32.d | 10 ++ gas/testsuite/gas/riscv/zfa-32.s | 3 + gas/testsuite/gas/riscv/zfa-64.d | 10 ++ gas/testsuite/gas/riscv/zfa-64.s | 3 + .../gas/riscv/zfa-fail-fcvtmod.w.d.d | 3 + .../gas/riscv/zfa-fail-fcvtmod.w.d.l | 8 ++ .../gas/riscv/zfa-fail-fcvtmod.w.d.s | 11 +++ gas/testsuite/gas/riscv/zfa-fail-fli.d | 3 + gas/testsuite/gas/riscv/zfa-fail-fli.l | 21 ++++ gas/testsuite/gas/riscv/zfa-fail-fli.s | 21 ++++ gas/testsuite/gas/riscv/zfa.d | 93 +++++++++++++++++ gas/testsuite/gas/riscv/zfa.s | 92 +++++++++++++++++ include/opcode/riscv-opc.h | 99 +++++++++++++++++++ include/opcode/riscv.h | 5 + opcodes/riscv-dis.c | 7 ++ opcodes/riscv-opc.c | 52 +++++++++- 18 files changed, 500 insertions(+), 1 deletion(-) create mode 100644 gas/testsuite/gas/riscv/zfa-32.d create mode 100644 gas/testsuite/gas/riscv/zfa-32.s create mode 100644 gas/testsuite/gas/riscv/zfa-64.d create mode 100644 gas/testsuite/gas/riscv/zfa-64.s create mode 100644 gas/testsuite/gas/riscv/zfa-fail-fcvtmod.w.d.d create mode 100644 gas/testsuite/gas/riscv/zfa-fail-fcvtmod.w.d.l create mode 100644 gas/testsuite/gas/riscv/zfa-fail-fcvtmod.w.d.s create mode 100644 gas/testsuite/gas/riscv/zfa-fail-fli.d create mode 100644 gas/testsuite/gas/riscv/zfa-fail-fli.l create mode 100644 gas/testsuite/gas/riscv/zfa-fail-fli.s create mode 100644 gas/testsuite/gas/riscv/zfa.d create mode 100644 gas/testsuite/gas/riscv/zfa.s base-commit: 4e38ed582cb9a2e09141126c2e0a527816e702e6 -- 2.34.1