From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-sender-0.a4lg.com (mail-sender-0.a4lg.com [IPv6:2401:2500:203:30b:4000:6bfe:4757:0]) by sourceware.org (Postfix) with ESMTPS id B6FFD3858028 for ; Thu, 22 Sep 2022 06:32:37 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org B6FFD3858028 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=irq.a4lg.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=irq.a4lg.com Received: from [127.0.0.1] (localhost [127.0.0.1]) by mail-sender-0.a4lg.com (Postfix) with ESMTPSA id 17E66300089; Thu, 22 Sep 2022 06:32:36 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=irq.a4lg.com; s=2017s01; t=1663828356; bh=hsW63glFzv7Ox+BpVrXibzpE3j2UB7vWUme66iNG6MA=; h=From:To:Cc:Subject:Date:Message-Id:Mime-Version: Content-Transfer-Encoding; b=qFrnZnMWolIWZL/OfW+h9SGjhnQe+t/pl/+EdqveyiLKJlnXS5Mdg+5wYbP+6NDJ3 QUy3G9bBuFL8BfPTsMQfCy1wLBP/DC1O4hDH73Rc5zeo4p7UB01WK5LRWjtXEGQPms jFwdp6TuaYx1ExR+Gsgs9zohWsDf2Ug66SmidVZw= From: Tsukasa OI To: Tsukasa OI , Nelson Chu , Kito Cheng , Palmer Dabbelt Cc: binutils@sourceware.org Subject: [PATCH v3 0/2] RISC-V psABI: Assign DWARF register numbers to vector registers Date: Thu, 22 Sep 2022 06:32:32 +0000 Message-Id: Mime-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-6.2 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,SPF_HELO_NONE,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: Hello, Surprisingly, I found that no vector registers (v0-v31) are assigned DWARF register numbers. RISC-V ABIs Specification (riscv-elf-psabi-doc) is not ratified yet but at least frozen. So, I consider it's stable to upstream it. According to the documentation, it has register numbers 96 (v0) - 127 (v31). [Changes: v1 -> v2] Remove invented word "VPRs" (at least it has no consistent uses in the RISC-V ecosystem) and replaced with "Vector registers" [Changes: v2 -> v3] Changed reference (v1.0-rc3 -> v1.0-rc4). Tracker on GitHub: RISC-V ABIs Specification Version 1.0-rc4: Frozen I also added DWARF register number tests not just for CSRs (existing) and vector registers (I just added), but also for GPRs (0-31) and FPRs (32-63). Thanks, Tsukasa Tsukasa OI (2): RISC-V: Assign DWARF numbers to vector registers RISC-V: Add testcase for DWARF register numbers binutils/dwarf.c | 28 ++-- gas/config/tc-riscv.c | 3 + gas/testsuite/gas/riscv/dw-regnums.d | 180 ++++++++++++++++++++++++++ gas/testsuite/gas/riscv/dw-regnums.s | 184 +++++++++++++++++++++++++++ 4 files changed, 385 insertions(+), 10 deletions(-) create mode 100644 gas/testsuite/gas/riscv/dw-regnums.d create mode 100644 gas/testsuite/gas/riscv/dw-regnums.s base-commit: 90eca7111355e4c6683c1ab10fd07107ea10f6d1 -- 2.34.1