[PATCH 0/1] RISC-V psABI: Add testcase for DWARF register numbers

[Tsukasa OI <research_trasio@irq.a4lg.com>]

Hello,

This is based on the subset of
"RISC-V psABI: Assign DWARF register numbers to vector registers"
<https://sourceware.org/pipermail/binutils/2022-September/123007.html>.

Although it had csr-dw-regnums.d to test DWARF register numbers for CSRs,
it didn't have DWARF register number test for GPRs/FPRs.
So, this patchset adds it.

The reason I split this (from vector register patchset) is these register
numbers for GPRs/FPRs are widely accepted already and adding this test first
makes possible to completely split vector register patchset and the DWARF
register number test itself.

I also made a change so that we test "fp" (alias of "x8" or "s0"; I forgot
to add this to the test).

Thanks,
Tsukasa




Tsukasa OI (1):
  RISC-V: Add testcase for DWARF register numbers

 gas/testsuite/gas/riscv/dw-regnums.d | 149 ++++++++++++++++++++++++++
 gas/testsuite/gas/riscv/dw-regnums.s | 151 +++++++++++++++++++++++++++
 2 files changed, 300 insertions(+)
 create mode 100644 gas/testsuite/gas/riscv/dw-regnums.d
 create mode 100644 gas/testsuite/gas/riscv/dw-regnums.s


base-commit: 8e037eae6823caf5b9cb5b4feb3de838abb25956
-- 
2.34.1