[PATCH 0/2] RISC-V: Zfinx-related improvements (testcases and fmv.[sdq]) - SPLITTED

[Tsukasa OI <research_trasio@irq.a4lg.com>]

Hello,

GitHub tracker:
<https://github.com/a4lg/binutils-gdb/wiki/riscv_float_combined_1>

A part of my combined 'Zfinx' fixes, in specific, register pair
implementation (original PATCH 3/3) is being rewritten.

The original PATCH 3/3 has following issues and being rewritten based on the
framework to provide common framework to handle aligned register pairs for
both 'Z[dq]inx' and 'Zpsfoperand' (a part of 'P'-extension proposal).  It
also have found following issues:

(1) Lack of 'Zhinxmin' + 'Z[dq]inx' support
(2) Insufficient test coverage
(3) Possibly better handling to improve maintainability

Original 'Zfinx' fixes:
<https://sourceware.org/pipermail/binutils/2022-September/122715.html>

New 'Zfinx' fixes branch (in development):
<https://github.com/a4lg/binutils-gdb/tree/riscv-float-combined>


Meanwhile, could someone at least approve the remaining part?

PATCH 1/2 (formerly PATCH 1/3): Enhance Zfinx/Zdinx/Zqinx testcases
    Jiawei's 'Zhinx' testcases are great and extending the idea to
    'Z[fdq]inx' would be also great.
PATCH 2/2 (formerly PATCH 2/3): Relax Requirements to fmv.[sdq] instructions
    Note that fmv.h instruction is already available on
    both 'Zhinx' and 'Zfh'.  Likewise, we should relax requirements to
    "fmv.[sdq]".  For instance, "fmv.d" is now only a part of 'D' but the
    specification allows both 'D' and 'Zdinx' and it has unique benefits
    as described in the mail above.

I fully explained why this is good to apply previously (see the mail above)
and I didn't hear any objections here.  I sincerely request the comment,
review or approval (even rejection is acceptable as long as it doesn't take
much time).

It's already February when the first version is submitted to this mailing
list and I would like to hear something new (Palmer added Reviewed-by lines
to my early versions but I'm not confident enough that they were approval).

Thanks,
Tsukasa




Tsukasa OI (2):
  RISC-V: Reorganize and enhance 'Zfinx' tests
  RISC-V: Relax "fmv.[sdq]" requirements

 gas/testsuite/gas/riscv/zdinx.d | 30 +++++++++---
 gas/testsuite/gas/riscv/zdinx.s | 46 ++++++++++++-----
 gas/testsuite/gas/riscv/zfinx.d | 27 ++++++++--
 gas/testsuite/gas/riscv/zfinx.s | 42 +++++++++++-----
 gas/testsuite/gas/riscv/zqinx.d | 87 +++++++++++++++++++--------------
 gas/testsuite/gas/riscv/zqinx.s | 87 ++++++++++++++++++++-------------
 opcodes/riscv-opc.c             |  6 +--
 7 files changed, 216 insertions(+), 109 deletions(-)


base-commit: 26681d1c3c43469ca90ca39105278bc1601d4225
-- 
2.34.1