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From: Tsukasa OI <research_trasio@irq.a4lg.com>
To: Tsukasa OI <research_trasio@irq.a4lg.com>
Cc: binutils@sourceware.org
Subject: [PATCH 0/1] RISC-V: Move supervisor instructions after all unprivileged ones
Date: Sat,  1 Oct 2022 05:39:25 +0000	[thread overview]
Message-ID: <cover.1664602716.git.research_trasio@irq.a4lg.com> (raw)

Hello,

GitHub tracker:
<https://github.com/a4lg/binutils-gdb/wiki/riscv_opcode_tidying_csr_1>

This is a small tidying patchset.

This location of supervisor instructions is out of place (because many other
privileged instructions are located at the tail but after the supervisor
instructions, we have many unprivileged instructions including bit
manipulation / crypto / vector instructions).

Not only that, this is harmful to implement pseudoinstructions in the latest
'P'-extension proposal (CLROV and RDOV).

This patchset moves supervisor instructions after all unprivileged
instructions and adjusts some indents.


Thanks,
Tsukasa




Tsukasa OI (1):
  RISC-V: Move supervisor instructions after all unprivileged ones

 opcodes/riscv-opc.c | 64 ++++++++++++++++++++++-----------------------
 1 file changed, 32 insertions(+), 32 deletions(-)


base-commit: 53a265a1f14d17a6f7b106082f610994c5d546e0
-- 
2.34.1


             reply	other threads:[~2022-10-01  5:39 UTC|newest]

Thread overview: 4+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-10-01  5:39 Tsukasa OI [this message]
2022-10-01  5:39 ` [PATCH 1/1] " Tsukasa OI
2022-10-01  7:45   ` Nelson Chu
2022-10-01  8:15     ` Tsukasa OI

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