From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-sender-0.a4lg.com (mail-sender.a4lg.com [153.120.152.154]) by sourceware.org (Postfix) with ESMTPS id 676873858D1E; Tue, 4 Oct 2022 09:46:01 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 676873858D1E Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=irq.a4lg.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=irq.a4lg.com Received: from [127.0.0.1] (localhost [127.0.0.1]) by mail-sender-0.a4lg.com (Postfix) with ESMTPSA id 99A24300089; Tue, 4 Oct 2022 09:45:59 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=irq.a4lg.com; s=2017s01; t=1664876759; bh=wM8DQrdbRugAX5VLaU3xKSitcuvviir8wtl4giOPd8A=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: Mime-Version:Content-Transfer-Encoding; b=XtSBtzYesA7uXc0lfFct2FSBpYarDNp88Dp2xsdWRZP5wF67z+TV2EZAXebq9M0FP gEnqIOU8QiffhhCZChy5nN28NLBdYTd+6gpFMQZYDyuaMjSnSrPMUbmUcR2ZedgLm0 1bnB6crD1X3VXMcgC5qQ7OL5kkmqZy4bwt9vZ9YA= From: Tsukasa OI To: Tsukasa OI , Nelson Chu , Kito Cheng , Palmer Dabbelt , Andrew Burgess , Jan Beulich , Andreas Schwab Cc: binutils@sourceware.org, gdb-patches@sourceware.org Subject: [PATCH v2 0/2] RISC-V: Fix buffer overflow after 176-bit instruction support Date: Tue, 4 Oct 2022 09:45:48 +0000 Message-Id: In-Reply-To: References: Mime-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-6.0 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,KAM_MANYTO,SPF_HELO_NONE,SPF_PASS,TXREP autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: Hello, After commit bb996692bd9 "RISC-V/gas: allow generating up to 176-bit instructions with .insn", I started to see some crashes while running "make check-gas". The cause was simple. Some functions depended on the fact that maximum length returned by riscv_insn_length is 8. But since the commit above increased that upper limit from 64-bits (8 bytes) to 176-bits (22 bytes), we need to increase two buffer sizes to avoid crashes. But note that this change doesn't really support over 64-bit instructions. At least we can safely ignore those long instructions but we must remember that we are still in a partial support for 176-bit instructions. [Changes: v1 -> v2] - Fix assertion failure on riscv_insn::decode - Use new constant RISCV_MAX_INSN_LEN for buffer size PATCH 1: Binutils PATCH 2: GDB (v2: depends on PATCH 1) Thanks, Tsukasa Tsukasa OI (2): RISC-V: Fix buffer overflow on print_insn_riscv gdb/riscv: Partial support for instructions up to 176-bits gdb/riscv-tdep.c | 9 +++++---- include/opcode/riscv.h | 2 ++ opcodes/riscv-dis.c | 2 +- 3 files changed, 8 insertions(+), 5 deletions(-) base-commit: 034235cebd790d4f9a1728043a175d7d7d9338b1 -- 2.34.1