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From: Tsukasa OI <research_trasio@irq.a4lg.com>
To: Tsukasa OI <research_trasio@irq.a4lg.com>,
	Nelson Chu <nelson@rivosinc.com>,
	Kito Cheng <kito.cheng@sifive.com>,
	Palmer Dabbelt <palmer@dabbelt.com>
Cc: binutils@sourceware.org
Subject: [PATCH v2 0/1] RISC-V psABI: Add testcase for DWARF register numbers (supplemental)
Date: Sat,  8 Oct 2022 04:29:52 +0000	[thread overview]
Message-ID: <cover.1665203374.git.research_trasio@irq.a4lg.com> (raw)
In-Reply-To: <cover.1663922476.git.research_trasio@irq.a4lg.com>

Hello,

This is a supplement to my previous patchset and tests DWARF register number
of "fp" (x8 or "s0").

Thanks,
Tsukasa




Tsukasa OI (1):
  RISC-V: Test DWARF register numbers for "fp"

 gas/testsuite/gas/riscv/dw-regnums.d | 1 +
 gas/testsuite/gas/riscv/dw-regnums.s | 3 +++
 2 files changed, 4 insertions(+)


base-commit: 4cbfd0daabd68516651ee37a19d0e24ca4789ea3
-- 
2.34.1


  parent reply	other threads:[~2022-10-08  4:30 UTC|newest]

Thread overview: 5+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-09-23  8:41 [PATCH 0/1] RISC-V psABI: Add testcase for DWARF register numbers Tsukasa OI
2022-09-23  8:41 ` [PATCH 1/1] RISC-V: " Tsukasa OI
2022-10-08  4:29 ` Tsukasa OI [this message]
2022-10-08  4:29   ` [PATCH v2 1/1] RISC-V: Test DWARF register numbers for "fp" Tsukasa OI
2022-10-14  1:33   ` [PATCH v2 0/1] RISC-V psABI: Add testcase for DWARF register numbers (supplemental) Nelson Chu

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