From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-sender-0.a4lg.com (mail-sender.a4lg.com [153.120.152.154]) by sourceware.org (Postfix) with ESMTPS id 889363836004 for ; Tue, 15 Nov 2022 04:31:38 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 889363836004 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=irq.a4lg.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=irq.a4lg.com Received: from [127.0.0.1] (localhost [127.0.0.1]) by mail-sender-0.a4lg.com (Postfix) with ESMTPSA id 9B504300089; Tue, 15 Nov 2022 04:31:34 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=irq.a4lg.com; s=2017s01; t=1668486694; bh=SBzFG0knKLjgS/0Uec9GjY/LJJsB02XT0jHD1yVCfBE=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: Mime-Version:Content-Transfer-Encoding; b=QjhKUzK0jtqSfdFWgWdESsTN2WAUBIv8+azPOSr+N4HC5Q+7mC3QQ0MmMOSBLV4Y3 WMg2sGq/3WoybnyZqfGlLgMCB2+onv0rQguW42HUlg6lwpv8FqoWHsGGjCmWpyeJ5Z 57iQ0GkhjJNXS/h5x5IJKKPTCdPKdRT1mCzPXzyw= From: Tsukasa OI To: Tsukasa OI , Nelson Chu , Kito Cheng , Palmer Dabbelt Cc: binutils@sourceware.org Subject: [PATCH v3 0/8] RISC-V: Various opcode tidying (batch 1) Date: Tue, 15 Nov 2022 04:31:21 +0000 Message-Id: In-Reply-To: References: Mime-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-6.1 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,SPF_HELO_NONE,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: PATCH v1: PATCH v2: Only change between v2 and v3 is a rebase to resolve conflict with commit a8d181c0fdae ("RISC-V: xtheadfmemidx: Use fp register in mnemonics"). So, this is pretty much unchanged from v2. As a reminder, this e-mail is followed by the same cover letter as v2. ============= Hello, This patchset contains various tidying of RISC-V opcodes that would... (a) Make coding style more consistent and/or more readable (b) Remove unused constants (c) Make new instruction names primary (clean old names except aliases) (d) Make opcode entries functionally consistent. I call this "batch 1" and deals with the most obvious (yet small and various) issues. [Overview of this Patchset] PATCH 1/8: (a) Tidying (add space at the tail of pinfo) PATCH 2/8: (a) Tidying (fix obvious misalignments on 'Zbb'/'Zba') PATCH 3/8: (a) Tidying (remove spaces around "|" operator) PATCH 4/8: (b) Remove unused instruction macros PATCH 5/8: (c) SCALL -> ECALL, SBREAK -> EBREAK (RISC-V ISA v2.1) PATCH 6/8: (c) FMV.S.X -> FMV.W.X, FMV.X.S -> FMV.X.W (RISC-V ISA v2.2) PATCH 7/8: (c) Make old instruction names aliases PATCH 8/8: (d) Use defined (and named) constants for instruction defining Thanks, Tsukasa Tsukasa OI (8): RISC-V: Add a space at the end of pinfo RISC-V: Fix obvious misalignments ('Zbb'/'Zba') RISC-V: Remove spaces in opcode entries RISC-V: Remove unused instruction macros RISC-V: Complete tidying up with SCALL and SBREAK RISC-V: Tidying up with fmv.w.x and fmv.x.w RISC-V: Make alias instructions aliases RISC-V: Use defined mask and match values include/opcode/riscv-opc.h | 47 +-- opcodes/riscv-opc.c | 706 ++++++++++++++++++------------------- 2 files changed, 359 insertions(+), 394 deletions(-) base-commit: 8148339a741b37df6df3c4b3c4a7b9e812a79be7 -- 2.37.2