From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-sender-0.a4lg.com (mail-sender-0.a4lg.com [IPv6:2401:2500:203:30b:4000:6bfe:4757:0]) by sourceware.org (Postfix) with ESMTPS id C3AAA388883F for ; Fri, 25 Nov 2022 02:17:35 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org C3AAA388883F Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=irq.a4lg.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=irq.a4lg.com Received: from [127.0.0.1] (localhost [127.0.0.1]) by mail-sender-0.a4lg.com (Postfix) with ESMTPSA id 4D10F300089; Fri, 25 Nov 2022 02:17:33 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=irq.a4lg.com; s=2017s01; t=1669342653; bh=uc6ywzN5DaEPYtmZz2cWp5Hk+maGg1Kye8bqJya/PkQ=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: Mime-Version:Content-Transfer-Encoding; b=iaeQABEEIh5f++m0J5yQqbUl7qHdguwGhdOiZq4sJTdsa/gSHB96r1OTkVJH03kzS YtHcyjjw13FAIT1qzKNH05oEn0dnY4k5kZEUpZcVS0MBAGDeDxponMVvGZ8Ij4aMaD KYFuz1HKTqcfYL/cwFDNy/x1FuTxboMpvPykapD4= From: Tsukasa OI To: Tsukasa OI , Jan Beulich , Nelson Chu Cc: binutils@sourceware.org Subject: [PATCH v3 0/2] RISC-V: Better support for long instructions (64 < x <= 176 [bits]) Date: Fri, 25 Nov 2022 02:17:22 +0000 Message-Id: In-Reply-To: References: Mime-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-6.1 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,SPF_HELO_NONE,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: Hello, c.f. PATCH v1: c.f. PATCH v2: [Changes: v2 -> v3] 1. PATCH v2 1/2 is removed 2. PATCH v2 2/2 is splitted to PATCH v3 {1,2}/2 based on the feedback of Jan Strict ".byte" testcases are only preserved to test new behavior. They are not 4-byte aligned (10 and 22-bytes) and unlikely to change any time soon. I hope this can be a good compromise. [Changes: v1 -> v2] 1. Rebased (as usual) 2. PATCH 2/2: Simplified the logic to extract low instruction bits (will describe later) 3. PATCH 2/2: Changed the commit message slightly Thanks, Tsukasa Tsukasa OI (2): RISC-V: Better support for long instructions (disassembler) RISC-V: Better support for long instructions (assembler) gas/config/tc-riscv.c | 38 ++++++++++++++++++++++------ gas/testsuite/gas/riscv/insn-dwarf.d | 10 +++++++- gas/testsuite/gas/riscv/insn-na.d | 8 ++++++ gas/testsuite/gas/riscv/insn.d | 22 ++++++++++++++++ gas/testsuite/gas/riscv/insn.s | 9 +++++++ opcodes/riscv-dis.c | 13 ++++++---- 6 files changed, 86 insertions(+), 14 deletions(-) base-commit: 18a119b83d1f0f661532e5167af1c5549496759c -- 2.38.1