From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-sender-0.a4lg.com (mail-sender-0.a4lg.com [IPv6:2401:2500:203:30b:4000:6bfe:4757:0]) by sourceware.org (Postfix) with ESMTPS id 788D5385B1A3 for ; Fri, 25 Nov 2022 11:42:27 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 788D5385B1A3 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=irq.a4lg.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=irq.a4lg.com Received: from [127.0.0.1] (localhost [127.0.0.1]) by mail-sender-0.a4lg.com (Postfix) with ESMTPSA id D92D7300089; Fri, 25 Nov 2022 11:42:25 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=irq.a4lg.com; s=2017s01; t=1669376546; bh=Gk18/4tqh7C+BzwRTpolzLO7pjHw/Hd+C/X+lWMAzjI=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: Mime-Version:Content-Transfer-Encoding; b=VMpFFs9tmoHzZxWKnUU0SrmSVhV7p/C6DDPKi7Oz8w9rtilfJBQXprDvXVmgDOQSl c4a1VIW6dHShsAzRLtH5D9PXzyaEYhwWNL+W2O8YO1NkPt3DFXHDK/EPzkGPVzY59z oqywmxH7XaPgaf2RgFs8akH0I7Tx4DvCNJozSzqY= From: Tsukasa OI To: Tsukasa OI , Jan Beulich , Nelson Chu Cc: binutils@sourceware.org Subject: [PATCH v4 0/3] RISC-V: Better support for long instructions (64 < x <= 176 [bits]) Date: Fri, 25 Nov 2022 11:42:19 +0000 Message-Id: In-Reply-To: References: Mime-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-6.1 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,SPF_HELO_NONE,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: Hello, c.f. PATCH v1 (with cover letter with some backgrounds): c.f. PATCH v2: c.f. PATCH v3: [Changes: v3 -> v4] 1. Split to three separate patches (disassembler fix, assembler fix and testcases that require both fixes) 2. PATCH 1/3: Further clarification of the intent of this commit (with examples) on the commit message. No changes in the code. 3. PATCH 2/3: Minor clarification on comments and the commit message. No code changes but some comment changes in tc-riscv.c. 4. PATCH 3/3: Clarify that it tests both fixes. [Changes: v2 -> v3] 1. PATCH v2 1/2 is removed 2. PATCH v2 2/2 is splitted to PATCH v3 {1,2}/2 based on the feedback of Jan Strict ".byte" testcases are only preserved to test new behavior. They are not 4-byte aligned (10 and 22-bytes) and unlikely to change any time soon. [Changes: v1 -> v2] 1. Rebased (as usual) 2. PATCH 2/2: Simplified the logic to extract low instruction bits (will describe later) 3. PATCH 2/2: Changed the commit message slightly Thanks, Tsukasa Tsukasa OI (3): RISC-V: Better support for long instructions (disassembler) RISC-V: Better support for long instructions (assembler) RISC-V: Better support for long instructions (tests) gas/config/tc-riscv.c | 41 ++++++++++++++++++++++------ gas/testsuite/gas/riscv/insn-dwarf.d | 10 ++++++- gas/testsuite/gas/riscv/insn-na.d | 8 ++++++ gas/testsuite/gas/riscv/insn.d | 22 +++++++++++++++ gas/testsuite/gas/riscv/insn.s | 9 ++++++ opcodes/riscv-dis.c | 14 ++++++---- 6 files changed, 89 insertions(+), 15 deletions(-) base-commit: ac8df5a1921904b3928429e696ad8b40c612f829 -- 2.38.1