From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-sender-0.a4lg.com (mail-sender.a4lg.com [153.120.152.154]) by sourceware.org (Postfix) with ESMTPS id 1F5713858D3C for ; Mon, 28 Nov 2022 06:39:48 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 1F5713858D3C Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=irq.a4lg.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=irq.a4lg.com Received: from [127.0.0.1] (localhost [127.0.0.1]) by mail-sender-0.a4lg.com (Postfix) with ESMTPSA id C1C27300089; Mon, 28 Nov 2022 06:39:45 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=irq.a4lg.com; s=2017s01; t=1669617585; bh=TRP/XBEHcy2jaxF7nDO6Qj7Aqo5A2Yt0mTvU3QCPp7w=; h=From:To:Cc:Subject:Date:Message-Id:Mime-Version: Content-Transfer-Encoding; b=aAFiTEJH2s/94yuKVPo8Xu/lMs5O09iK5HpMFXbMpBhPVXIwf0sOS0cWBIPL1OueZ QL+GfC205c31uLW6PMGhsSbnHLVenH4Qc9zK9AaPb/g0D9A4k7hMRFxO425v965+Hp l5EQPJZDbx5fU7k04njH+kgmvVm5jgJewhDwRh74= From: Tsukasa OI To: Tsukasa OI , Nelson Chu , Kito Cheng , Palmer Dabbelt Cc: binutils@sourceware.org Subject: [PATCH 0/3] RISC-V: Support non-standard encodings (on widening FP ops) Date: Mon, 28 Nov 2022 06:39:31 +0000 Message-Id: Mime-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-6.1 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,SPF_HELO_NONE,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: Hello, Some of the floating point instructions does not depend on the rounding mode despite the existence of rm (rounding mode) field. Such examples are widening conversion instructions. Quoting "11.2 Floating-Point Control and Status Register" from the RISC-V ISA Manual (version 20191213): > Some instructions, including widening conversions, have the rm field but > are nevertheless unaffected by the rounding mode; software should set > their rm field to RNE (000). The latest draft of the ISA Manual is clarified further: Quoting "13.2 Floating-Point Control and Status Register" from the RISC-V ISA Manual (version draft-20221119-5234c63): > Some instructions, including widening conversions, have the rm field but > are nevertheless mathematically unaffected by the rounding mode; software > should set their rm field to RNE (000) but implementations must treat the > rm field as usual (in particular, with regard to decoding legal vs. > reserved encodings). For instance, to encode a FCVT.D.S instruction, we should set its rm field to RNE (0b000). However, FCVT.D.S instruction with non-RNE rm field is still a valid instruction (despite that GAS does not allow specifying any rounding modes on FCVT.D.S) and must handle as a valid instruction when disassembled unless an invalid rounding mode is specified. However, current GNU Binutils only supports disassembling widening conversion instructions with rm field of RNE (0b000) except FCVT.Q.L and FCVT.Q.LU instructions (two instructions supported specifying rounding modes for historical reasons). This patchset (in specific, PATCH 3/3) enables special handling of such instructions by adding two new operand types: 1. "WfM": optional rounding mode where specifying rounding mode is not supported in the past. 2. "Wfm": optional rounding mode where specifying rounding mode is supported in the past (used in FCVT.Q.L and FCVT.Q.LU). I designed this patchset to be configurable (allow implementing S Pawan Kumar's proposal if needed) but the behavior in this patchset is as follows: Disassembler: Optional (non-RNE [!= 0b000]) rounding mode is printed only if: (a) "no-aliases" disassembler option is specified, or (b) the rounding mode is invalid (0b101 / 0b110). I think removing condition (a) might be an option. Because, despite that we can now see the actual rounding mode with condition (a), it's not valid as an assembler mnemonic. Condition (b) is an intentional choice to detect invalid encodings. Still, it could be removed, too (I don't recommend though). Assembler: Specifying optional rounding mode is prohibited (except FCVT.Q.L and FCVT.Q.LU) or accepted with a warning (FCVT.Q.L and FCVT.Q.LU). c.f. S Pawan Kumar's proposal: # Before this patchset: objdump -d (with my comment) 8000002c: 42058553 fcvt.d.s fa0,fa1 80000030: 42059553 .4byte 0x42059553 # Valid (but not recommended) encoding of FCVT.D.S 80000034: 4205a553 .4byte 0x4205a553 # Valid (but not recommended) encoding of FCVT.D.S 80000038: 4205b553 .4byte 0x4205b553 # Valid (but not recommended) encoding of FCVT.D.S 8000003c: 4205c553 .4byte 0x4205c553 # Valid (but not recommended) encoding of FCVT.D.S 80000040: 4205f553 .4byte 0x4205f553 # Valid (but not recommended) encoding of FCVT.D.S 80000044: 4205d553 .4byte 0x4205d553 # Invalid FCVT.D.S (reserved rounding mode 0b101) 80000048: 4205e553 .4byte 0x4205e553 # Invalid FCVT.D.S (reserved rounding mode 0b110) # After this patchset: objdump -d 8000002c: 42058553 fcvt.d.s fa0,fa1 80000030: 42059553 fcvt.d.s fa0,fa1 80000034: 4205a553 fcvt.d.s fa0,fa1 80000038: 4205b553 fcvt.d.s fa0,fa1 8000003c: 4205c553 fcvt.d.s fa0,fa1 80000040: 4205f553 fcvt.d.s fa0,fa1 80000044: 4205d553 fcvt.d.s fa0,fa1,unknown 80000048: 4205e553 fcvt.d.s fa0,fa1,unknown # After this patchset: objdump -M no-aliases -d 8000002c: 42058553 fcvt.d.s fa0,fa1 80000030: 42059553 fcvt.d.s fa0,fa1,rtz 80000034: 4205a553 fcvt.d.s fa0,fa1,rdn 80000038: 4205b553 fcvt.d.s fa0,fa1,rup 8000003c: 4205c553 fcvt.d.s fa0,fa1,rmm 80000040: 4205f553 fcvt.d.s fa0,fa1,dyn 80000044: 4205d553 fcvt.d.s fa0,fa1,unknown 80000048: 4205e553 fcvt.d.s fa0,fa1,unknown Due to my development process, it now depends on the commit ("RISC-V: Allocate "various" operand type": PATCH 1/3) which adds "Wif" operand type (not just "WfM" and "Wfm" which is added by PATCH 3/3). PATCH 1/3 is the same patch as this: If requested, I can remove the dependency to PATCH 1/3 (in that case my local development branches will be a bit complex but nothing else happens). Thanks, Tsukasa Tsukasa OI (3): RISC-V: Allocate "various" operand type RISC-V: Reorganize invalid rounding mode test RISC-V: Rounding mode on widening instructions gas/config/tc-riscv.c | 107 +++++++++++++++--- gas/testsuite/gas/riscv/rouding-fail.d | 3 - gas/testsuite/gas/riscv/rouding-fail.l | 3 - gas/testsuite/gas/riscv/rouding-fail.s | 3 - .../gas/riscv/rounding-dis-widening-noalias.d | 13 +++ .../gas/riscv/rounding-dis-widening.d | 13 +++ .../gas/riscv/rounding-dis-widening.s | 8 ++ gas/testsuite/gas/riscv/rounding-fail.d | 3 + gas/testsuite/gas/riscv/rounding-fail.l | 16 +++ gas/testsuite/gas/riscv/rounding-fail.s | 22 ++++ .../gas/riscv/rounding-fcvt.q.l-noalias.d | 15 +++ gas/testsuite/gas/riscv/rounding-fcvt.q.l.d | 15 +++ gas/testsuite/gas/riscv/rounding-fcvt.q.l.l | 3 + gas/testsuite/gas/riscv/rounding-fcvt.q.l.s | 5 + opcodes/riscv-dis.c | 48 +++++++- opcodes/riscv-opc.c | 32 +++--- 16 files changed, 261 insertions(+), 48 deletions(-) delete mode 100644 gas/testsuite/gas/riscv/rouding-fail.d delete mode 100644 gas/testsuite/gas/riscv/rouding-fail.l delete mode 100644 gas/testsuite/gas/riscv/rouding-fail.s create mode 100644 gas/testsuite/gas/riscv/rounding-dis-widening-noalias.d create mode 100644 gas/testsuite/gas/riscv/rounding-dis-widening.d create mode 100644 gas/testsuite/gas/riscv/rounding-dis-widening.s create mode 100644 gas/testsuite/gas/riscv/rounding-fail.d create mode 100644 gas/testsuite/gas/riscv/rounding-fail.l create mode 100644 gas/testsuite/gas/riscv/rounding-fail.s create mode 100644 gas/testsuite/gas/riscv/rounding-fcvt.q.l-noalias.d create mode 100644 gas/testsuite/gas/riscv/rounding-fcvt.q.l.d create mode 100644 gas/testsuite/gas/riscv/rounding-fcvt.q.l.l create mode 100644 gas/testsuite/gas/riscv/rounding-fcvt.q.l.s base-commit: c341f4676af4f9922ca61e1b093d103ed808ae6e -- 2.38.1