From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-sender-0.a4lg.com (mail-sender-0.a4lg.com [IPv6:2401:2500:203:30b:4000:6bfe:4757:0]) by sourceware.org (Postfix) with ESMTPS id 583C93858C83 for ; Sun, 9 Oct 2022 05:09:51 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 583C93858C83 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=irq.a4lg.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=irq.a4lg.com Received: from [127.0.0.1] (localhost [127.0.0.1]) by mail-sender-0.a4lg.com (Postfix) with ESMTPSA id 49D5C300089; Sun, 9 Oct 2022 05:09:48 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=irq.a4lg.com; s=2017s01; t=1665292188; bh=lhjTkO4GkTqmHpUFGheS+gxP5oebgO6GR0PZ68GbXCw=; h=From:To:Cc:Subject:Date:Message-Id:Mime-Version: Content-Transfer-Encoding; b=BpS2/YW16+JTa98zBBcQaOb/YhBcxbffFF4gSRvvMY8KPHqkBmqkfLOuz6+rM1iKe 2ry/9tNYyGVd8+EoReyUZDPTQcBGLpkxD0P7ns34COV2CZj5gyGY3PRzqo7lknQ9XP Z6rQb4n0PGoa7hAyr16R4dBL2IIfJUeeo4hyc2ig= From: Tsukasa OI To: Tsukasa OI , Nelson Chu , Kito Cheng , Palmer Dabbelt Cc: binutils@sourceware.org Subject: [PATCH] RISC-V: Move certain arrays to riscv-opc.c Date: Sun, 9 Oct 2022 05:09:22 +0000 Message-Id: Mime-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-12.1 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,GIT_PATCH_0,SPF_HELO_NONE,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: This is a part of small tidying (declare tables in riscv-opc.c). include/ChangeLog: * opcode/riscv.h (riscv_rm, riscv_pred_succ): Move declarations to opcodes/riscv-opc.c. New non-static definitions. opcodes/ChangeLog: * riscv-opc.c (riscv_rm, riscv_pred_succ): Move from include/opcode/riscv.h. Add description. --- include/opcode/riscv.h | 13 ++----------- opcodes/riscv-opc.c | 13 +++++++++++++ 2 files changed, 15 insertions(+), 11 deletions(-) diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h index f173a2eca25..dddabfdd415 100644 --- a/include/opcode/riscv.h +++ b/include/opcode/riscv.h @@ -46,17 +46,6 @@ static inline unsigned int riscv_insn_length (insn_t insn) return 2; } -static const char * const riscv_rm[8] = -{ - "rne", "rtz", "rdn", "rup", "rmm", 0, 0, "dyn" -}; - -static const char * const riscv_pred_succ[16] = -{ - 0, "w", "r", "rw", "o", "ow", "or", "orw", - "i", "iw", "ir", "irw", "io", "iow", "ior", "iorw" -}; - #define RVC_JUMP_BITS 11 #define RVC_JUMP_REACH ((1ULL << RVC_JUMP_BITS) * RISCV_JUMP_ALIGN) @@ -555,6 +544,8 @@ extern const char * const riscv_gpr_names_numeric[NGPR]; extern const char * const riscv_gpr_names_abi[NGPR]; extern const char * const riscv_fpr_names_numeric[NFPR]; extern const char * const riscv_fpr_names_abi[NFPR]; +extern const char * const riscv_rm[8]; +extern const char * const riscv_pred_succ[16]; extern const char * const riscv_vecr_names_numeric[NVECR]; extern const char * const riscv_vecm_names_numeric[NVECM]; extern const char * const riscv_vsew[8]; diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c index 11bb87d7eaa..04acc8470be 100644 --- a/opcodes/riscv-opc.c +++ b/opcodes/riscv-opc.c @@ -58,6 +58,19 @@ const char * const riscv_fpr_names_abi[NFPR] = "fs8", "fs9", "fs10", "fs11", "ft8", "ft9", "ft10", "ft11" }; +/* Rounding modes. */ +const char * const riscv_rm[8] = +{ + "rne", "rtz", "rdn", "rup", "rmm", 0, 0, "dyn" +}; + +/* FENCE: predecessor/successor sets. */ +const char * const riscv_pred_succ[16] = +{ + 0, "w", "r", "rw", "o", "ow", "or", "orw", + "i", "iw", "ir", "irw", "io", "iow", "ior", "iorw" +}; + /* RVV registers. */ const char * const riscv_vecr_names_numeric[NVECR] = { base-commit: c10a862f17847bc9c50d680c87b87dc51ae4b95e -- 2.34.1