[PATCH 1/2] gas: RISC-V: Add a test for near->far branch conversion

[PATCH 1/2] gas: RISC-V: Add a test for near->far branch conversion

[Palmer Dabbelt]

This works in GAS and has for a very long time, but I couldn't find a
test case for it.  It doesn't appear to be documented anywhere, but GCC
depends on it and I'd bet a bunch of handwritten assembly does too so
it's probably too late to drop.
---
 gas/testsuite/gas/riscv/far-branch.d | 13 +++++++++++++
 gas/testsuite/gas/riscv/far-branch.s |  6 ++++++
 2 files changed, 19 insertions(+)
 create mode 100644 gas/testsuite/gas/riscv/far-branch.d
 create mode 100644 gas/testsuite/gas/riscv/far-branch.s

diff --git a/gas/testsuite/gas/riscv/far-branch.d b/gas/testsuite/gas/riscv/far-branch.d
new file mode 100644
index 00000000000..e781e3eadb5
--- /dev/null
+++ b/gas/testsuite/gas/riscv/far-branch.d
@@ -0,0 +1,13 @@
+#as: -march=rv32i
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+[^:]+:[ 	]+00b51063[ 	]+bne[ 	]+a0,a1,0 <target>
+#...
+[^:]+:[ 	]+00b50463[ 	]+beq[ 	]+a0,a1,.*
+[^:]+:[ 	]+ff9fe06f[ 	]+j[ 	]+0 <target>
diff --git a/gas/testsuite/gas/riscv/far-branch.s b/gas/testsuite/gas/riscv/far-branch.s
new file mode 100644
index 00000000000..2b369ffb538
--- /dev/null
+++ b/gas/testsuite/gas/riscv/far-branch.s
@@ -0,0 +1,6 @@
+target:
+	bne a0, a1, target
+.rep 1024
+	nop
+.endr
+	bne a0, a1, target
-- 
2.39.0

[PATCH 2/2] ld: RISC-V: Test R_RISCV_BRANCH truncation errors

[Palmer Dabbelt]

We can't actually produce binaries with these errors from the assembler,
since it magically converts far branches into multi-instruction
sequences, so instead use objcopy to make the symbol weak after the
assembler has a chance to know that's going to happen.
---
 ld/testsuite/ld-riscv-elf/far-branch-fail-01.s | 16 ++++++++++++++++
 ld/testsuite/ld-riscv-elf/far-branch-fail-02.s | 12 ++++++++++++
 ld/testsuite/ld-riscv-elf/far-branch-fail.d    |  7 +++++++
 ld/testsuite/ld-riscv-elf/ld-riscv-elf.exp     |  1 +
 4 files changed, 36 insertions(+)
 create mode 100644 ld/testsuite/ld-riscv-elf/far-branch-fail-01.s
 create mode 100644 ld/testsuite/ld-riscv-elf/far-branch-fail-02.s
 create mode 100644 ld/testsuite/ld-riscv-elf/far-branch-fail.d

diff --git a/ld/testsuite/ld-riscv-elf/far-branch-fail-01.s b/ld/testsuite/ld-riscv-elf/far-branch-fail-01.s
new file mode 100644
index 00000000000..4c96671c78e
--- /dev/null
+++ b/ld/testsuite/ld-riscv-elf/far-branch-fail-01.s
@@ -0,0 +1,16 @@
+.text
+.global space1
+space1:
+.rep 1024
+	nop
+.endr
+
+.global glob
+glob:
+	addi x0, x0, 2
+
+.global space2
+space2:
+.rep 1024
+	nop
+.endr
diff --git a/ld/testsuite/ld-riscv-elf/far-branch-fail-02.s b/ld/testsuite/ld-riscv-elf/far-branch-fail-02.s
new file mode 100644
index 00000000000..fc51a0bed6e
--- /dev/null
+++ b/ld/testsuite/ld-riscv-elf/far-branch-fail-02.s
@@ -0,0 +1,12 @@
+.text
+.global _start
+_start:
+	beq a0, a1, space1
+	beq a0, a1, glob
+	beq a0, a1, space2
+
+.global glob
+glob:
+.global glob_orig
+glob_orig:
+	addi x0, x0, 1
diff --git a/ld/testsuite/ld-riscv-elf/far-branch-fail.d b/ld/testsuite/ld-riscv-elf/far-branch-fail.d
new file mode 100644
index 00000000000..668b63a8d08
--- /dev/null
+++ b/ld/testsuite/ld-riscv-elf/far-branch-fail.d
@@ -0,0 +1,7 @@
+#name: fail on branch overflows
+#source: far-branch-fail-01.s
+#source: far-branch-fail-02.s RUN_OBJCOPY
+#objcopy_objects: -W glob
+#objdump: -d
+#ld:
+#error: .*relocation truncated to fit: R_RISCV_BRANCH against symbol.*glob.*
diff --git a/ld/testsuite/ld-riscv-elf/ld-riscv-elf.exp b/ld/testsuite/ld-riscv-elf/ld-riscv-elf.exp
index 0f7ccd92ed5..1edbe8bd67a 100644
--- a/ld/testsuite/ld-riscv-elf/ld-riscv-elf.exp
+++ b/ld/testsuite/ld-riscv-elf/ld-riscv-elf.exp
@@ -169,6 +169,7 @@ if [istarget "riscv*-*-*"] {
     run_dump_test "attr-merge-priv-spec-failed-05"
     run_dump_test "attr-merge-priv-spec-failed-06"
     run_dump_test "attr-phdr"
+    run_dump_test "far-branch-fail"
     run_ld_link_tests [list \
 	[list "Weak reference 32" "-T weakref.ld -m[riscv_choose_ilp32_emul]" "" \
 	    "-march=rv32i -mabi=ilp32" {weakref32.s} \
-- 
2.39.0

Re: [PATCH 1/2] gas: RISC-V: Add a test for near->far branch conversion

[Nelson Chu]

I always thought the test cases were already there, because the
assembler branch relaxation (or branch conversion, whatever called)
has been supported since the very beginning of the risc-v porting.
Anyway, both of the gas and ld test cases for this are what we need,
so thanks for adding them :)

Nelson

On Tue, Jan 31, 2023 at 5:07 AM Palmer Dabbelt <palmer@rivosinc.com> wrote:
>
> This works in GAS and has for a very long time, but I couldn't find a
> test case for it.  It doesn't appear to be documented anywhere, but GCC
> depends on it and I'd bet a bunch of handwritten assembly does too so
> it's probably too late to drop.
> ---
>  gas/testsuite/gas/riscv/far-branch.d | 13 +++++++++++++
>  gas/testsuite/gas/riscv/far-branch.s |  6 ++++++
>  2 files changed, 19 insertions(+)
>  create mode 100644 gas/testsuite/gas/riscv/far-branch.d
>  create mode 100644 gas/testsuite/gas/riscv/far-branch.s
>
> diff --git a/gas/testsuite/gas/riscv/far-branch.d b/gas/testsuite/gas/riscv/far-branch.d
> new file mode 100644
> index 00000000000..e781e3eadb5
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/far-branch.d
> @@ -0,0 +1,13 @@
> +#as: -march=rv32i
> +#objdump: -d
> +
> +.*:[   ]+file format .*
> +
> +
> +Disassembly of section .text:
> +
> +0+000 <target>:
> +[^:]+:[        ]+00b51063[     ]+bne[  ]+a0,a1,0 <target>
> +#...
> +[^:]+:[        ]+00b50463[     ]+beq[  ]+a0,a1,.*
> +[^:]+:[        ]+ff9fe06f[     ]+j[    ]+0 <target>
> diff --git a/gas/testsuite/gas/riscv/far-branch.s b/gas/testsuite/gas/riscv/far-branch.s
> new file mode 100644
> index 00000000000..2b369ffb538
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/far-branch.s
> @@ -0,0 +1,6 @@
> +target:
> +       bne a0, a1, target
> +.rep 1024
> +       nop
> +.endr
> +       bne a0, a1, target
> --
> 2.39.0
>

Re: [PATCH 1/2] gas: RISC-V: Add a test for near->far branch conversion

[Jan Beulich]

On 30.01.2023 22:06, Palmer Dabbelt wrote:
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/far-branch.d
> @@ -0,0 +1,13 @@
> +#as: -march=rv32i
> +#objdump: -d
> +
> +.*:[ 	]+file format .*
> +
> +
> +Disassembly of section .text:
> +
> +0+000 <target>:
> +[^:]+:[ 	]+00b51063[ 	]+bne[ 	]+a0,a1,0 <target>
> +#...
> +[^:]+:[ 	]+00b50463[ 	]+beq[ 	]+a0,a1,.*

Isn't the target of this branch kind of relevant here, and hence shouldn't
be "anything" in the expectations?

Jan