* [PATCH][Binutils] aarch64: add SPMU feature and its associated registers
@ 2024-05-15 11:36 Matthieu Longo
2024-05-16 11:37 ` Nick Clifton
0 siblings, 1 reply; 2+ messages in thread
From: Matthieu Longo @ 2024-05-15 11:36 UTC (permalink / raw)
To: binutils; +Cc: Richard Earnshaw, Nick Clifton
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Hi,
AArch64 defines registers for the feature spmu (System Performance
Monitors Extension).
spmu is an Armv8.9-A feature.
Those registers were missed previously.
This patch also adds relevant tests. Regression tested on
aarch64-none-elf, and no regression found.
Ok for binutils-master? I don't have commit access so I need someone to
commit on my behalf.
Regards,
Matthieu.
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From 37bcdb869b9100ae3d366f565c5871fb4be4ffac Mon Sep 17 00:00:00 2001
From: Matthieu Longo <matthieu.longo@arm.com>
Date: Wed, 21 Feb 2024 16:32:51 +0000
Subject: [PATCH] aarch64: add SPMU feature and its associated registers
AArch64 defines new registers for the feature spmu (System Performance
Monitors Extension). spmu is an Armv8.9-A feature.
This patch also adds relevant tests. Regression tested on aarch64-none-elf,
and no regression found.
---
.../gas/aarch64/sysreg/armv8_9-a-sysregs-bad.l | 14 ++++++++++++++
.../gas/aarch64/sysreg/armv8_9-a-sysregs.d | 7 +++++++
.../gas/aarch64/sysreg/armv8_9-a-sysregs.s | 6 ++++++
include/opcode/aarch64.h | 3 +++
opcodes/aarch64-sys-regs.def | 4 ++++
5 files changed, 34 insertions(+)
diff --git a/gas/testsuite/gas/aarch64/sysreg/armv8_9-a-sysregs-bad.l b/gas/testsuite/gas/aarch64/sysreg/armv8_9-a-sysregs-bad.l
index 05431cc501b..9cf94755cf6 100644
--- a/gas/testsuite/gas/aarch64/sysreg/armv8_9-a-sysregs-bad.l
+++ b/gas/testsuite/gas/aarch64/sysreg/armv8_9-a-sysregs-bad.l
@@ -204,6 +204,20 @@
.*: Error: selected processor does not support system register name 'pmicfiltr_el0'
.*: Info: macro invoked from here
.*: Error: selected processor does not support system register name 'pmzr_el0'
+.*: Error: selected processor does not support system register name 'spmaccessr_el1'
+.*: Info: macro invoked from here
+.*: Error: selected processor does not support system register name 'spmaccessr_el1'
+.*: Info: macro invoked from here
+.*: Error: selected processor does not support system register name 'spmcr_el0'
+.*: Info: macro invoked from here
+.*: Error: selected processor does not support system register name 'spmcr_el0'
+.*: Info: macro invoked from here
+.*: Error: selected processor does not support system register name 'spmdevaff_el1'
+.*: Info: macro invoked from here
+.*: Error: selected processor does not support system register name 'spmintenset_el1'
+.*: Info: macro invoked from here
+.*: Error: selected processor does not support system register name 'spmintenset_el1'
+.*: Info: macro invoked from here
.*: Error: selected processor does not support system register name 'pmecr_el1'
.*: Info: macro invoked from here
.*: Error: selected processor does not support system register name 'pmecr_el1'
diff --git a/gas/testsuite/gas/aarch64/sysreg/armv8_9-a-sysregs.d b/gas/testsuite/gas/aarch64/sysreg/armv8_9-a-sysregs.d
index 9913c2be6d3..e420f7077a6 100644
--- a/gas/testsuite/gas/aarch64/sysreg/armv8_9-a-sysregs.d
+++ b/gas/testsuite/gas/aarch64/sysreg/armv8_9-a-sysregs.d
@@ -128,6 +128,13 @@ Disassembly of section \.text:
.*: d51b9600 msr pmicfiltr_el0, x0
.*: d53b9600 mrs x0, pmicfiltr_el0
.*: d51b9d80 msr pmzr_el0, x0
+.*: d5109d60 msr spmaccessr_el1, x0
+.*: d5309d60 mrs x0, spmaccessr_el1
+.*: d5139c00 msr spmcr_el0, x0
+.*: d5339c00 mrs x0, spmcr_el0
+.*: d5309dc0 mrs x0, spmdevaff_el1
+.*: d5109e20 msr spmintenset_el1, x0
+.*: d5309e20 mrs x0, spmintenset_el1
.*: d5189ea0 msr pmecr_el1, x0
.*: d5389ea0 mrs x0, pmecr_el1
.*: d5189ee0 msr pmiar_el1, x0
diff --git a/gas/testsuite/gas/aarch64/sysreg/armv8_9-a-sysregs.s b/gas/testsuite/gas/aarch64/sysreg/armv8_9-a-sysregs.s
index 318d8bb9097..6a01cb43289 100644
--- a/gas/testsuite/gas/aarch64/sysreg/armv8_9-a-sysregs.s
+++ b/gas/testsuite/gas/aarch64/sysreg/armv8_9-a-sysregs.s
@@ -107,6 +107,12 @@
rw_sys_reg sys_reg=pmicfiltr_el0 xreg=x0 r=1 w=1
msr pmzr_el0, x0
+ /* FEAT_SPMU */
+ rw_sys_reg sys_reg=spmaccessr_el1 xreg=x0 r=1 w=1
+ rw_sys_reg sys_reg=spmcr_el0 xreg=x0 r=1 w=1
+ rw_sys_reg sys_reg=spmdevaff_el1 xreg=x0 r=1 w=0
+ rw_sys_reg sys_reg=spmintenset_el1 xreg=x0 r=1 w=1
+
/* FEAT_SEBEP Extension. */
rw_sys_reg sys_reg=pmecr_el1 xreg=x0 r=1 w=1
rw_sys_reg sys_reg=pmiar_el1 xreg=x0 r=1 w=1
diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h
index e8fe93ef127..1ec0b66a654 100644
--- a/include/opcode/aarch64.h
+++ b/include/opcode/aarch64.h
@@ -218,6 +218,8 @@ enum aarch64_feature_bit {
AARCH64_FEATURE_PMUv3_SS,
/* Performance Monitors Instruction Counter Extension. */
AARCH64_FEATURE_PMUv3_ICNTR,
+ /* System Performance Monitors Extension */
+ AARCH64_FEATURE_SPMU,
/* Performance Monitors Synchronous-Exception-Based Event Extension. */
AARCH64_FEATURE_SEBEP,
/* SVE2.1 and SME2.1 non-widening BFloat16 instructions. */
@@ -309,6 +311,7 @@ enum aarch64_feature_bit {
| AARCH64_FEATBIT (X, PMUv3p9) \
| AARCH64_FEATBIT (X, PMUv3_SS) \
| AARCH64_FEATBIT (X, PMUv3_ICNTR) \
+ | AARCH64_FEATBIT (X, SPMU) \
| AARCH64_FEATBIT (X, SEBEP) \
| AARCH64_FEATBIT (X, PREDRES2) \
)
diff --git a/opcodes/aarch64-sys-regs.def b/opcodes/aarch64-sys-regs.def
index 8b65673a5d6..7cbc9a4811f 100644
--- a/opcodes/aarch64-sys-regs.def
+++ b/opcodes/aarch64-sys-regs.def
@@ -867,6 +867,10 @@
SYSREG ("sp_el0", CPENC (3,0,4,1,0), 0, AARCH64_NO_FEATURES)
SYSREG ("sp_el1", CPENC (3,4,4,1,0), 0, AARCH64_NO_FEATURES)
SYSREG ("sp_el2", CPENC (3,6,4,1,0), 0, AARCH64_NO_FEATURES)
+ SYSREG ("spmaccessr_el1", CPENC (2,0,9,13,3), F_ARCHEXT, AARCH64_FEATURE (SPMU))
+ SYSREG ("spmcr_el0", CPENC (2,3,9,12,0), F_ARCHEXT, AARCH64_FEATURE (SPMU))
+ SYSREG ("spmdevaff_el1", CPENC (2,0,9,13,6), F_REG_READ|F_ARCHEXT, AARCH64_FEATURE (SPMU))
+ SYSREG ("spmintenset_el1", CPENC (2,0,9,14,1), F_ARCHEXT, AARCH64_FEATURE (SPMU))
SYSREG ("spsel", CPENC (3,0,4,2,0), 0, AARCH64_NO_FEATURES)
SYSREG ("spsr_abt", CPENC (3,4,4,3,1), 0, AARCH64_NO_FEATURES)
SYSREG ("spsr_el1", CPENC (3,0,4,0,0), 0, AARCH64_NO_FEATURES)
--
2.34.1
^ permalink raw reply [flat|nested] 2+ messages in thread
* Re: [PATCH][Binutils] aarch64: add SPMU feature and its associated registers
2024-05-15 11:36 [PATCH][Binutils] aarch64: add SPMU feature and its associated registers Matthieu Longo
@ 2024-05-16 11:37 ` Nick Clifton
0 siblings, 0 replies; 2+ messages in thread
From: Nick Clifton @ 2024-05-16 11:37 UTC (permalink / raw)
To: Matthieu Longo, binutils; +Cc: Richard Earnshaw
Hi Matthieu,
> AArch64 defines registers for the feature spmu (System Performance Monitors Extension).
> spmu is an Armv8.9-A feature.
> Those registers were missed previously.
>
> This patch also adds relevant tests. Regression tested on aarch64-none-elf, and no regression found.
>
> Ok for binutils-master? I don't have commit access so I need someone to commit on my behalf.
Approved and applied.
Cheers
Nick
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2024-05-16 11:37 ` Nick Clifton
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