From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-sender-0.a4lg.com (mail-sender.a4lg.com [153.120.152.154]) by sourceware.org (Postfix) with ESMTPS id CA0EA384D15E for ; Thu, 6 Oct 2022 09:56:46 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org CA0EA384D15E Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=irq.a4lg.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=irq.a4lg.com Received: from [127.0.0.1] (localhost [127.0.0.1]) by mail-sender-0.a4lg.com (Postfix) with ESMTPSA id 275A9300089; Thu, 6 Oct 2022 09:56:45 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=irq.a4lg.com; s=2017s01; t=1665050205; bh=1C1v2VA1s9Z0h0XEHh5iunC0k8IzNO4SWx8cSZo//+k=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: Mime-Version:Content-Transfer-Encoding; b=l4GqfdTJSZrswEHY4p5lRZyqS3C2BjsweOoBJp3wzTIvoBqVWmp91B3Gns9fZP7Kg oS/+liSGYcQj8w9/4jFXgACSnglj/q4O3FQIznVCLzOQWwDiOLTTDuKY6HxxByDn3V cLuXsVtRxXpODltgdUTIHbFV9Rn+1PpN4IcKIZAE= From: Tsukasa OI To: Tsukasa OI , Nelson Chu , Kito Cheng , Palmer Dabbelt Cc: binutils@sourceware.org Subject: [PATCH v3 1/2] RISC-V: Fallback for instructions longer than 64b Date: Thu, 6 Oct 2022 09:56:30 +0000 Message-Id: In-Reply-To: References: Mime-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-12.1 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,GIT_PATCH_0,SPF_HELO_NONE,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: We don't support instructions longer than 64-bits yet. Still, we can modify validate_riscv_insn function to prevent unexpected behavior by limiting the "length" of an instruction to 64-bit (or less). gas/ChangeLog: * config/tc-riscv.c (validate_riscv_insn): Fix function description comment based on current spec. Limit instruction length up to 64-bit for now. Make sure that required_bits does not corrupt even if unsigned long long is longer than 64-bit. --- gas/config/tc-riscv.c | 13 ++++++++----- 1 file changed, 8 insertions(+), 5 deletions(-) diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c index 22385d1baa0..41d6dfc6062 100644 --- a/gas/config/tc-riscv.c +++ b/gas/config/tc-riscv.c @@ -1109,7 +1109,8 @@ arg_lookup (char **s, const char *const *array, size_t size, unsigned *regnop) /* For consistency checking, verify that all bits are specified either by the match/mask part of the instruction definition, or by the - operand list. The `length` could be 0, 4 or 8, 0 for auto detection. */ + operand list. The `length` could be the actual instruction length or + 0 for auto-detection. */ static bool validate_riscv_insn (const struct riscv_opcode *opc, int length) @@ -1120,11 +1121,13 @@ validate_riscv_insn (const struct riscv_opcode *opc, int length) insn_t required_bits; if (length == 0) - insn_width = 8 * riscv_insn_length (opc->match); - else - insn_width = 8 * length; + length = riscv_insn_length (opc->match); + /* We don't support instructions longer than 64-bits yet. */ + if (length > 8) + length = 8; + insn_width = 8 * length; - required_bits = ~0ULL >> (64 - insn_width); + required_bits = ((insn_t)~0ULL) >> (64 - insn_width); if ((used_bits & opc->match) != (opc->match & required_bits)) { -- 2.34.1