From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 44155 invoked by alias); 1 May 2019 17:13:18 -0000 Mailing-List: contact binutils-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: binutils-owner@sourceware.org Received: (qmail 44085 invoked by uid 89); 1 May 2019 17:13:18 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-25.1 required=5.0 tests=AWL,BAYES_00,GIT_PATCH_0,GIT_PATCH_1,GIT_PATCH_2,GIT_PATCH_3,KAM_LOTSOFHASH,SPF_PASS autolearn=ham version=3.3.1 spammy= X-HELO: foss.arm.com Received: from usa-sjc-mx-foss1.foss.arm.com (HELO foss.arm.com) (217.140.101.70) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Wed, 01 May 2019 17:13:16 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 05D4780D for ; Wed, 1 May 2019 10:13:15 -0700 (PDT) Received: from [10.2.207.62] (e107157-lin.cambridge.arm.com [10.2.207.62]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id A461E3F719 for ; Wed, 1 May 2019 10:13:14 -0700 (PDT) Subject: [PATCH 20/57][Arm][GAS] Add support for MVE instructions: vmaxnmv, vmaxnmav, vminnmv and vminnmav To: binutils@sourceware.org References: <19569550-4d2e-0bb3-592a-d91050d490f6@arm.com> From: "Andre Vieira (lists)" Message-ID: Date: Wed, 01 May 2019 17:13:00 -0000 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.6.1 MIME-Version: 1.0 In-Reply-To: <19569550-4d2e-0bb3-592a-d91050d490f6@arm.com> Content-Type: multipart/mixed; boundary="------------4EA67FAF5E5A35F3E8735B17" X-IsSubscribed: yes X-SW-Source: 2019-05/txt/msg00049.txt.bz2 This is a multi-part message in MIME format. --------------4EA67FAF5E5A35F3E8735B17 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit Content-length: 454 Hi, This patch adds support for MVE instructions VMAXNMV, VMAXNMAV, VMINNMV, and VMINNMAV. gas/ChangeLog: 2019-05-01 Andre Vieira * config/tc-arm.c (do_mve_vmaxnmv): New encoding function. (insns): Add entries for new mnemonics. * testsuite/gas/arm/mve-vmaxnmv-vminnmv-bad.d: New test. * testsuite/gas/arm/mve-vmaxnmv-vminnmv-bad.l: New test. * testsuite/gas/arm/mve-vmaxnmv-vminnmv-bad.s: New test. --------------4EA67FAF5E5A35F3E8735B17 Content-Type: text/x-patch; name="20.patch" Content-Transfer-Encoding: 7bit Content-Disposition: attachment; filename="20.patch" Content-length: 7272 diff --git a/gas/config/tc-arm.c b/gas/config/tc-arm.c index f490b91b685d4c0089bd8c4ad055b534d389aa8b..051ab6837b6b5cf4d8482ef267d5cd4a4a67243c 100644 --- a/gas/config/tc-arm.c +++ b/gas/config/tc-arm.c @@ -17251,6 +17251,26 @@ do_mve_vmladav (void) inst.instruction |= (et.size == 32) << 16; } +static void +do_mve_vmaxnmv (void) +{ + enum neon_shape rs = neon_select_shape (NS_RQ, NS_NULL); + struct neon_type_el et + = neon_check_type (2, rs, N_EQK, N_F_MVE | N_KEY); + + if (inst.cond > COND_ALWAYS) + inst.pred_insn_type = INSIDE_VPT_INSN; + else + inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN; + + if (inst.operands[0].reg == REG_SP) + as_tsktsk (MVE_BAD_SP); + else if (inst.operands[0].reg == REG_PC) + as_tsktsk (MVE_BAD_PC); + + mve_encode_rq (et.size == 16, 64); +} + static void do_neon_qrdmlah (void) { @@ -24424,6 +24444,10 @@ static const struct asm_opcode insns[] = mToC("vfmas", ee311e40, 3, (RMQ, RMQ, RR), mve_vfmas), mToC("vmaxnma", ee3f0e81, 2, (RMQ, RMQ), mve_vmaxnma_vminnma), mToC("vminnma", ee3f1e81, 2, (RMQ, RMQ), mve_vmaxnma_vminnma), + mToC("vmaxnmv", eeee0f00, 2, (RR, RMQ), mve_vmaxnmv), + mToC("vmaxnmav",eeec0f00, 2, (RR, RMQ), mve_vmaxnmv), + mToC("vminnmv", eeee0f80, 2, (RR, RMQ), mve_vmaxnmv), + mToC("vminnmav",eeec0f80, 2, (RR, RMQ), mve_vmaxnmv), #undef ARM_VARIANT #define ARM_VARIANT & fpu_vfp_ext_v1 diff --git a/gas/testsuite/gas/arm/mve-vmaxnmv-vminnmv-bad.d b/gas/testsuite/gas/arm/mve-vmaxnmv-vminnmv-bad.d new file mode 100644 index 0000000000000000000000000000000000000000..aca103c92aec94fdb3629f2416f1318f6cd5b1e2 --- /dev/null +++ b/gas/testsuite/gas/arm/mve-vmaxnmv-vminnmv-bad.d @@ -0,0 +1,5 @@ +#name: bad MVE VMAXNMV, VMAXNMAV, VMINNMV and VMINNMAV instructions +#as: -march=armv8.1-m.main+mve.fp +#error_output: mve-vmaxnmv-vminnmv-bad.l + +.*: +file format .*arm.* diff --git a/gas/testsuite/gas/arm/mve-vmaxnmv-vminnmv-bad.l b/gas/testsuite/gas/arm/mve-vmaxnmv-vminnmv-bad.l new file mode 100644 index 0000000000000000000000000000000000000000..5b30434027c203db386f252e99b26851e2dd8fec --- /dev/null +++ b/gas/testsuite/gas/arm/mve-vmaxnmv-vminnmv-bad.l @@ -0,0 +1,57 @@ +[^:]*: Assembler messages: +[^:]*:10: Error: bad type in SIMD instruction -- `vmaxnmv.f64 r0,q1' +[^:]*:11: Error: bad type in SIMD instruction -- `vmaxnmv.i16 r0,q1' +[^:]*:12: Error: bad type in SIMD instruction -- `vminnmv.f64 r0,q1' +[^:]*:13: Error: bad type in SIMD instruction -- `vminnmv.i16 r0,q1' +[^:]*:14: Error: bad type in SIMD instruction -- `vmaxnmav.f64 r0,q1' +[^:]*:15: Error: bad type in SIMD instruction -- `vmaxnmav.i16 r0,q1' +[^:]*:16: Error: bad type in SIMD instruction -- `vminnmav.f64 r0,q1' +[^:]*:17: Error: bad type in SIMD instruction -- `vminnmav.i16 r0,q1' +[^:]*:18: Warning: instruction is UNPREDICTABLE with SP operand +[^:]*:19: Warning: instruction is UNPREDICTABLE with PC operand +[^:]*:20: Warning: instruction is UNPREDICTABLE with SP operand +[^:]*:21: Warning: instruction is UNPREDICTABLE with PC operand +[^:]*:22: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:22: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:22: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:22: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:22: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:22: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:23: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:23: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:23: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:23: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:23: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:23: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:24: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:24: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:24: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:24: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:24: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:24: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:25: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:25: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:25: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:25: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:25: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:25: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:27: Error: syntax error -- `vmaxnmveq.f32 r0,q1' +[^:]*:28: Error: syntax error -- `vmaxnmveq.f32 r0,q1' +[^:]*:30: Error: syntax error -- `vmaxnmveq.f32 r0,q1' +[^:]*:31: Error: vector predicated instruction should be in VPT/VPST block -- `vmaxnmvt.f32 r0,q1' +[^:]*:33: Error: instruction missing MVE vector predication code -- `vmaxnmv.f32 r0,q1' +[^:]*:35: Error: syntax error -- `vmaxnmaveq.f32 r0,q1' +[^:]*:36: Error: syntax error -- `vmaxnmaveq.f32 r0,q1' +[^:]*:38: Error: syntax error -- `vmaxnmaveq.f32 r0,q1' +[^:]*:39: Error: vector predicated instruction should be in VPT/VPST block -- `vmaxnmavt.f32 r0,q1' +[^:]*:41: Error: instruction missing MVE vector predication code -- `vmaxnmav.f32 r0,q1' +[^:]*:43: Error: syntax error -- `vminnmveq.f32 r0,q1' +[^:]*:44: Error: syntax error -- `vminnmveq.f32 r0,q1' +[^:]*:46: Error: syntax error -- `vminnmveq.f32 r0,q1' +[^:]*:47: Error: vector predicated instruction should be in VPT/VPST block -- `vminnmvt.f32 r0,q1' +[^:]*:49: Error: instruction missing MVE vector predication code -- `vminnmv.f32 r0,q1' +[^:]*:51: Error: syntax error -- `vminnmaveq.f32 r0,q1' +[^:]*:52: Error: syntax error -- `vminnmaveq.f32 r0,q1' +[^:]*:54: Error: syntax error -- `vminnmaveq.f32 r0,q1' +[^:]*:55: Error: vector predicated instruction should be in VPT/VPST block -- `vminnmavt.f32 r0,q1' +[^:]*:57: Error: instruction missing MVE vector predication code -- `vminnmav.f32 r0,q1' diff --git a/gas/testsuite/gas/arm/mve-vmaxnmv-vminnmv-bad.s b/gas/testsuite/gas/arm/mve-vmaxnmv-vminnmv-bad.s new file mode 100644 index 0000000000000000000000000000000000000000..58c4de1e5bcb1e5bf7c525c5ec797056bb2c5bab --- /dev/null +++ b/gas/testsuite/gas/arm/mve-vmaxnmv-vminnmv-bad.s @@ -0,0 +1,57 @@ +.macro cond, op +.irp cond, eq, ne, gt, ge, lt, le +it \cond +\op\().f16 r0, q1 +.endr +.endm + +.syntax unified +.thumb +vmaxnmv.f64 r0, q1 +vmaxnmv.i16 r0, q1 +vminnmv.f64 r0, q1 +vminnmv.i16 r0, q1 +vmaxnmav.f64 r0, q1 +vmaxnmav.i16 r0, q1 +vminnmav.f64 r0, q1 +vminnmav.i16 r0, q1 +vmaxnmv.f16 sp, q1 +vmaxnmav.f32 pc, q1 +vminnmav.f16 sp, q1 +vminnmv.f32 pc, q1 +cond vmaxnmv +cond vminnmv +cond vmaxnmav +cond vminnmav +it eq +vmaxnmveq.f32 r0, q1 +vmaxnmveq.f32 r0, q1 +vpst +vmaxnmveq.f32 r0, q1 +vmaxnmvt.f32 r0, q1 +vpst +vmaxnmv.f32 r0, q1 +it eq +vmaxnmaveq.f32 r0, q1 +vmaxnmaveq.f32 r0, q1 +vpst +vmaxnmaveq.f32 r0, q1 +vmaxnmavt.f32 r0, q1 +vpst +vmaxnmav.f32 r0, q1 +it eq +vminnmveq.f32 r0, q1 +vminnmveq.f32 r0, q1 +vpst +vminnmveq.f32 r0, q1 +vminnmvt.f32 r0, q1 +vpst +vminnmv.f32 r0, q1 +it eq +vminnmaveq.f32 r0, q1 +vminnmaveq.f32 r0, q1 +vpst +vminnmaveq.f32 r0, q1 +vminnmavt.f32 r0, q1 +vpst +vminnmav.f32 r0, q1 --------------4EA67FAF5E5A35F3E8735B17--