From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-sender-0.a4lg.com (mail-sender.a4lg.com [153.120.152.154]) by sourceware.org (Postfix) with ESMTPS id B99DE385C406 for ; Tue, 1 Feb 2022 13:54:04 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org B99DE385C406 From: Tsukasa OI To: Tsukasa OI Cc: binutils@sourceware.org Subject: [PATCH 4/4] RISC-V: Add disassembler tests for Zqinx regs Date: Tue, 1 Feb 2022 22:53:38 +0900 Message-Id: In-Reply-To: References: Mime-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-13.4 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, SPF_HELO_NONE, SPF_PASS, TO_EQ_FM_DIRECT_MX, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.4 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on server2.sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 01 Feb 2022 13:54:06 -0000 This commid adds disassembler tests for invalid Zqinx register numbers (make sure that we don't disassemble invalid encodings). gas/ChangeLog: * testsuite/gas/riscv/zqinx-32-regpair-dis.s: New test to make sure that invalid encodings are not disassembled. * testsuite/gas/riscv/zqinx-32-regpair-dis.d: Likewise. * testsuite/gas/riscv/zqinx-64-regpair-dis.s: New test to make sure that invalid encoding is not disassembled. * testsuite/gas/riscv/zqinx-64-regpair-dis.d: Likewise. --- gas/testsuite/gas/riscv/zqinx-32-regpair-dis.d | 12 ++++++++++++ gas/testsuite/gas/riscv/zqinx-32-regpair-dis.s | 7 +++++++ gas/testsuite/gas/riscv/zqinx-64-regpair-dis.d | 11 +++++++++++ gas/testsuite/gas/riscv/zqinx-64-regpair-dis.s | 5 +++++ 4 files changed, 35 insertions(+) create mode 100644 gas/testsuite/gas/riscv/zqinx-32-regpair-dis.d create mode 100644 gas/testsuite/gas/riscv/zqinx-32-regpair-dis.s create mode 100644 gas/testsuite/gas/riscv/zqinx-64-regpair-dis.d create mode 100644 gas/testsuite/gas/riscv/zqinx-64-regpair-dis.s diff --git a/gas/testsuite/gas/riscv/zqinx-32-regpair-dis.d b/gas/testsuite/gas/riscv/zqinx-32-regpair-dis.d new file mode 100644 index 00000000000..5af92477116 --- /dev/null +++ b/gas/testsuite/gas/riscv/zqinx-32-regpair-dis.d @@ -0,0 +1,12 @@ +#as: -march=rv32ima_zqinx +#source: zqinx-32-regpair-dis.s +#objdump: -dr -Mnumeric + +.*:[ ]+file format .* + +Disassembly of section .text: + +0+000 : +[ ]+[0-9a-f]+:[ ]+06c47253[ ]+fadd.q[ ]+x4,x8,x12 +[ ]+[0-9a-f]+:[ ]+06d4f2d3[ ]+\.4byte[ ]+0x6d4f2d3 +[ ]+[0-9a-f]+:[ ]+06e57353[ ]+\.4byte[ ]+0x6e57353 diff --git a/gas/testsuite/gas/riscv/zqinx-32-regpair-dis.s b/gas/testsuite/gas/riscv/zqinx-32-regpair-dis.s new file mode 100644 index 00000000000..e11e671ecdc --- /dev/null +++ b/gas/testsuite/gas/riscv/zqinx-32-regpair-dis.s @@ -0,0 +1,7 @@ +target: + # fadd.q x4, x8, x12 + .insn 0x06c47253 + # fadd.q x5, x9, x13 (invalid) + .insn 0x06d4f2d3 + # fadd.q x6, x10, x14 (invalid) + .insn 0x06e57353 diff --git a/gas/testsuite/gas/riscv/zqinx-64-regpair-dis.d b/gas/testsuite/gas/riscv/zqinx-64-regpair-dis.d new file mode 100644 index 00000000000..894ed34948e --- /dev/null +++ b/gas/testsuite/gas/riscv/zqinx-64-regpair-dis.d @@ -0,0 +1,11 @@ +#as: -march=rv64ima_zqinx +#source: zqinx-64-regpair-dis.s +#objdump: -dr -Mnumeric + +.*:[ ]+file format .* + +Disassembly of section .text: + +0+000 : +[ ]+[0-9a-f]+:[ ]+06627153[ ]+fadd.q[ ]+x2,x4,x6 +[ ]+[0-9a-f]+:[ ]+0672f1d3[ ]+\.4byte[ ]+0x672f1d3 diff --git a/gas/testsuite/gas/riscv/zqinx-64-regpair-dis.s b/gas/testsuite/gas/riscv/zqinx-64-regpair-dis.s new file mode 100644 index 00000000000..9edeae84ba7 --- /dev/null +++ b/gas/testsuite/gas/riscv/zqinx-64-regpair-dis.s @@ -0,0 +1,5 @@ +target: + # fadd.q x2, x4, x6 + .insn 0x06627153 + # fadd.q x3, x5, x7 (invalid) + .insn 0x0672f1d3 -- 2.32.0