From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-sender-0.a4lg.com (mail-sender-0.a4lg.com [IPv6:2401:2500:203:30b:4000:6bfe:4757:0]) by sourceware.org (Postfix) with ESMTPS id 852F03840080 for ; Fri, 25 Nov 2022 11:42:48 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 852F03840080 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=irq.a4lg.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=irq.a4lg.com Received: from [127.0.0.1] (localhost [127.0.0.1]) by mail-sender-0.a4lg.com (Postfix) with ESMTPSA id D8982300089; Fri, 25 Nov 2022 11:42:46 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=irq.a4lg.com; s=2017s01; t=1669376567; bh=i8tYmFfAQITDugBgAIfslqpoTGqJFweoMTVPWJ0n+8Q=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: Mime-Version:Content-Transfer-Encoding; b=of3xVUdSbEbcAkteM3bszmTZsGz6+dF4wpViIJe/JKbKvTDGxeSwvSuszIvyyu6x4 fI/do1/jnlfe7zS4P2EiHRQN5TZ0ebdMWn8f99WFnpRtr971d2Cc+dQAV6nxVZbp04 yNBfPhVhiHYF3mdFrWJSC3o7T62GpjdpM+ovBpoI= From: Tsukasa OI To: Tsukasa OI , Jan Beulich , Nelson Chu Cc: binutils@sourceware.org Subject: [PATCH v4 2/3] RISC-V: Better support for long instructions (assembler) Date: Fri, 25 Nov 2022 11:42:21 +0000 Message-Id: In-Reply-To: References: Mime-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-12.1 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,GIT_PATCH_0,SPF_HELO_NONE,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: From: Tsukasa OI Commit bb996692bd96 ("RISC-V/gas: allow generating up to 176-bit instructions with .insn") tried to start supporting long instructions but it was insufficient. 1. It heavily depended on the bignum internals (radix of 2^16), 2. It generates "value conflicts with instruction length" even if a big number instruction encoding does not exceed its expected length and 3. Because long opcode was handled separately (from struct riscv_cl_insn), some information like DWARF line number correspondence was missing. To resolve these problems, this commit: 1. Handles bignum (and its encodings) precisely and 2. Incorporates long opcode handling into regular instruction handling. This commit will be tested on the separate commit. gas/ChangeLog: * config/tc-riscv.c (struct riscv_cl_insn): Add long opcode field. (create_insn) Clear long opcode marker. (install_insn) Install longer opcode as well. (s_riscv_insn) Likewise. (riscv_ip_hardcode): Make big number handling stricter. Length and the value conflicts only if the bignum size exceeds the expected maximum length. --- gas/config/tc-riscv.c | 41 ++++++++++++++++++++++++++++++++--------- 1 file changed, 32 insertions(+), 9 deletions(-) diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c index 96d71dd1db60..0682eb355241 100644 --- a/gas/config/tc-riscv.c +++ b/gas/config/tc-riscv.c @@ -42,9 +42,13 @@ struct riscv_cl_insn /* The opcode's entry in riscv_opcodes. */ const struct riscv_opcode *insn_mo; - /* The encoded instruction bits. */ + /* The encoded instruction bits + (first bits enough to extract instruction length on a long opcode). */ insn_t insn_opcode; + /* The long encoded instruction bits ([0] is non-zero on a long opcode). */ + char insn_long_opcode[RISCV_MAX_INSN_LEN]; + /* The frag that contains the instruction. */ struct frag *frag; @@ -720,6 +724,7 @@ create_insn (struct riscv_cl_insn *insn, const struct riscv_opcode *mo) { insn->insn_mo = mo; insn->insn_opcode = mo->match; + insn->insn_long_opcode[0] = 0; insn->frag = NULL; insn->where = 0; insn->fixp = NULL; @@ -731,7 +736,10 @@ static void install_insn (const struct riscv_cl_insn *insn) { char *f = insn->frag->fr_literal + insn->where; - number_to_chars_littleendian (f, insn->insn_opcode, insn_length (insn)); + if (insn->insn_long_opcode[0] != 0) + memcpy (f, insn->insn_long_opcode, insn_length (insn)); + else + number_to_chars_littleendian (f, insn->insn_opcode, insn_length (insn)); } /* Move INSN to offset WHERE in FRAG. Adjust the fixups accordingly @@ -3503,7 +3511,9 @@ riscv_ip_hardcode (char *str, values[num++] = (insn_t) imm_expr->X_add_number; break; case O_big: - values[num++] = generic_bignum[0]; + /* Extract lower 32-bits of a big number. + Assume that generic_bignum_to_int32 work on such number. */ + values[num++] = (insn_t) generic_bignum_to_int32 (); break; default: /* The first value isn't constant, so it should be @@ -3530,12 +3540,25 @@ riscv_ip_hardcode (char *str, if (imm_expr->X_op == O_big) { - if (bytes != imm_expr->X_add_number * CHARS_PER_LITTLENUM) + unsigned int llen = 0; + for (LITTLENUM_TYPE lval = generic_bignum[imm_expr->X_add_number - 1]; + lval != 0; llen++) + lval >>= BITS_PER_CHAR; + unsigned int repr_bytes + = (imm_expr->X_add_number - 1) * CHARS_PER_LITTLENUM + llen; + if (bytes < repr_bytes) return _("value conflicts with instruction length"); - char *f = frag_more (bytes); - for (num = 0; num < imm_expr->X_add_number; ++num) - number_to_chars_littleendian (f + num * CHARS_PER_LITTLENUM, - generic_bignum[num], CHARS_PER_LITTLENUM); + for (num = 0; num < imm_expr->X_add_number - 1; ++num) + number_to_chars_littleendian ( + ip->insn_long_opcode + num * CHARS_PER_LITTLENUM, + generic_bignum[num], + CHARS_PER_LITTLENUM); + if (llen != 0) + number_to_chars_littleendian ( + ip->insn_long_opcode + num * CHARS_PER_LITTLENUM, + generic_bignum[num], + llen); + memset(ip->insn_long_opcode + repr_bytes, 0, bytes - repr_bytes); return NULL; } @@ -4612,7 +4635,7 @@ s_riscv_insn (int x ATTRIBUTE_UNUSED) else as_bad ("%s `%s'", error.msg, error.statement); } - else if (imm_expr.X_op != O_big) + else { gas_assert (insn.insn_mo->pinfo != INSN_MACRO); append_insn (&insn, &imm_expr, imm_reloc); -- 2.38.1