From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 67961 invoked by alias); 6 Mar 2020 14:54:03 -0000 Mailing-List: contact binutils-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: binutils-owner@sourceware.org Received: (qmail 67952 invoked by uid 89); 6 Mar 2020 14:54:03 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-9.4 required=5.0 tests=AWL,BAYES_00,GIT_PATCH_2,GIT_PATCH_3,SPF_PASS autolearn=ham version=3.3.1 spammy= X-HELO: mx2.suse.de Received: from mx2.suse.de (HELO mx2.suse.de) (195.135.220.15) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Fri, 06 Mar 2020 14:53:58 +0000 Received: from relay2.suse.de (unknown [195.135.220.254]) by mx2.suse.de (Postfix) with ESMTP id 7B209AD5D; Fri, 6 Mar 2020 14:53:56 +0000 (UTC) Subject: Re: [PATCH 2/6] x86-64: Intel64 adjustments for conditional jumps To: "H.J. Lu" Cc: "binutils@sourceware.org" References: <17ee93b3-33ea-5c10-23b2-408c7fb5b5a2@suse.com> From: Jan Beulich Message-ID: Date: Fri, 06 Mar 2020 14:54:00 -0000 User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:68.0) Gecko/20100101 Thunderbird/68.5.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 7bit X-IsSubscribed: yes X-SW-Source: 2020-03/txt/msg00151.txt On 06.03.2020 15:39, H.J. Lu wrote: > On Fri, Mar 6, 2020 at 12:12 AM Jan Beulich wrote: >> >> Just like for unconditional direct JMP, AMD and Intel differ in their >> handling. Mirror JMP handling to Jcc. >> >> gas/ >> 2020-03-XX Jan Beulich >> >> * testsuite/gas/i386/x86-64-branch-2.s, >> testsuite/gas/i386/x86-64-branch-3.s: Add Jcc cases. >> * testsuite/gas/i386/ilp32/x86-64-branch.d, >> testsuite/gas/i386/opcode-suffix.d, >> testsuite/gas/i386/x86-64-branch-2.d, >> testsuite/gas/i386/x86-64-branch-3.d, >> testsuite/gas/i386/x86-64-branch.d: Adjust expectations. >> >> opcodes/ >> 2020-03-XX Jan Beulich >> >> * i386-dis.c (safe-ctype.h): Include. >> (X86_64_0F8x): New enumerator. >> (dis386): Extend comment ahead of it. >> (dis386_twobyte): Vector Jcc to X86_64_0F8x. >> (condition_code): New. >> (x86_64_table): Add X86_64_0F8x entry. >> (print_insn): Set condition_code. Move advancing of codep after >> it. >> (putop): Handle two-char escape case for 'C'. Handle 'C' prefix >> case for 'P' and '@'. >> * i386-opc.tbl (j): Split into AMD64 and Intel64 variants. >> * i386-tbl.h: Re-generate. >> --- >> I wonder if the suffix handling done here wouldn't also be the more >> suitable one for JMP and CALL. In particular the 'q' suffix printed >> unconditionally in 64-bit mode is more of a problem than helpful imo. >> >> --- a/gas/testsuite/gas/i386/ilp32/x86-64-branch.d >> +++ b/gas/testsuite/gas/i386/ilp32/x86-64-branch.d >> @@ -22,7 +22,7 @@ Disassembly of section .text: >> [ ]*[a-f0-9]+: e9 00 00 00 00 jmpq 0x24 20: R_X86_64_PC32 \*ABS\*\+0x10003c >> [ ]*[a-f0-9]+: 66 e8 00 00 00 00 data16 callq 0x2a 26: R_X86_64_PLT32 foo-0x4 >> [ ]*[a-f0-9]+: 66 e9 00 00 00 00 data16 jmpq 0x30 2c: R_X86_64_PLT32 foo-0x4 >> -[ ]*[a-f0-9]+: 66 0f 82 00 00 00 00 data16 jb 0x37 33: R_X86_64_PLT32 foo-0x4 >> +[ ]*[a-f0-9]+: 66 0f 82 00 00 00 00 data16 jbq 0x37 33: R_X86_64_PLT32 foo-0x4 >> [ ]*[a-f0-9]+: 66 c3 data16 retq * >> [ ]*[a-f0-9]+: 66 c2 08 00 data16 retq \$0x8 >> [ ]*[a-f0-9]+: ff d0 callq \*%rax > > I think it is a very bad idea to add suffix to jcc. Well, do you have an alternative suggestion, also in line with JMP then? (See the somewhat related post-commit-message remark above as well.) I'd like to note that a suffix gets put there _only_ if there's also a data16 prefix (to be able to tell apart the different cases). Jan