* [PATCH 1/6] x86: reduce AVX512-FP16 set of insns decoded through vex_w_table[]
2022-01-05 11:31 [PATCH 0/6] x86: AVX512* / EVEX decoding adjustments Jan Beulich
@ 2022-01-05 11:32 ` Jan Beulich
2022-01-05 11:33 ` [PATCH 2/6] x86: reduce AVX512 FP " Jan Beulich
` (5 subsequent siblings)
6 siblings, 0 replies; 8+ messages in thread
From: Jan Beulich @ 2022-01-05 11:32 UTC (permalink / raw)
To: Binutils
Like already indicated during review of the original submission, there's
really only very few insns where going through this table is easier /
cheaper than using suitable macros. Utilize %XH more and introduce
similar %XS and %XD (which subsequently can be used for further table
size reduction).
While there also switch to using oappend() in 'XH' macro processing.
--- a/opcodes/i386-dis.c
+++ b/opcodes/i386-dis.c
@@ -1095,8 +1095,8 @@ enum
PREFIX_EVEX_0F38AA,
PREFIX_EVEX_0F38AB,
- PREFIX_EVEX_0F3A08_W_0,
- PREFIX_EVEX_0F3A0A_W_0,
+ PREFIX_EVEX_0F3A08,
+ PREFIX_EVEX_0F3A0A,
PREFIX_EVEX_0F3A26,
PREFIX_EVEX_0F3A27,
PREFIX_EVEX_0F3A56,
@@ -1116,10 +1116,8 @@ enum
PREFIX_EVEX_MAP5_51,
PREFIX_EVEX_MAP5_58,
PREFIX_EVEX_MAP5_59,
- PREFIX_EVEX_MAP5_5A_W_0,
- PREFIX_EVEX_MAP5_5A_W_1,
- PREFIX_EVEX_MAP5_5B_W_0,
- PREFIX_EVEX_MAP5_5B_W_1,
+ PREFIX_EVEX_MAP5_5A,
+ PREFIX_EVEX_MAP5_5B,
PREFIX_EVEX_MAP5_5C,
PREFIX_EVEX_MAP5_5D,
PREFIX_EVEX_MAP5_5E,
@@ -1129,7 +1127,7 @@ enum
PREFIX_EVEX_MAP5_7A,
PREFIX_EVEX_MAP5_7B,
PREFIX_EVEX_MAP5_7C,
- PREFIX_EVEX_MAP5_7D_W_0,
+ PREFIX_EVEX_MAP5_7D,
PREFIX_EVEX_MAP6_13,
PREFIX_EVEX_MAP6_56,
@@ -1629,9 +1627,7 @@ enum
EVEX_W_0F3883,
EVEX_W_0F3A05,
- EVEX_W_0F3A08,
EVEX_W_0F3A09,
- EVEX_W_0F3A0A,
EVEX_W_0F3A0B,
EVEX_W_0F3A18_L_n,
EVEX_W_0F3A19_L_n,
@@ -1648,21 +1644,8 @@ enum
EVEX_W_0F3A70,
EVEX_W_0F3A72,
- EVEX_W_MAP5_5A,
- EVEX_W_MAP5_5B,
- EVEX_W_MAP5_78_P_0,
- EVEX_W_MAP5_78_P_2,
- EVEX_W_MAP5_79_P_0,
- EVEX_W_MAP5_79_P_2,
- EVEX_W_MAP5_7A_P_2,
+ EVEX_W_MAP5_5B_P_0,
EVEX_W_MAP5_7A_P_3,
- EVEX_W_MAP5_7B_P_2,
- EVEX_W_MAP5_7C_P_0,
- EVEX_W_MAP5_7C_P_2,
- EVEX_W_MAP5_7D,
-
- EVEX_W_MAP6_13_P_0,
- EVEX_W_MAP6_13_P_2,
};
typedef void (*op_rtn) (int bytemode, int sizeflag);
@@ -1723,7 +1706,9 @@ struct dis386 {
"XZ" => print 'x', 'y', or 'z' if suffix_always is true or no
register operands and no broadcast.
"XW" => print 's', 'd' depending on the VEX.W bit (for FMA)
+ "XD" => print 'd' if EVEX.W=1, EVEX.W=0 is not a valid encoding
"XH" => print 'h' if EVEX.W=0, EVEX.W=1 is not a valid encoding (for FP16)
+ "XS" => print 's' if EVEX.W=0, EVEX.W=1 is not a valid encoding
"XV" => print "{vex3}" pseudo prefix
"LQ" => print 'l' ('d' in Intel mode) or 'q' for memory operand, cond
being false, or no operand at all in 64bit mode, or if suffix_always
@@ -10480,6 +10465,23 @@ putop (const char *in_template, int size
}
break;
case 'D':
+ if (len == 1)
+ {
+ switch (last[0])
+ {
+ case 'X':
+ if (vex.w)
+ *obufp++ = 'd';
+ else
+ oappend ("{bad}");
+ break;
+ default:
+ abort ();
+ }
+ break;
+ }
+ if (len)
+ abort ();
if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
break;
USED_REX (REX_W);
@@ -10565,13 +10567,7 @@ putop (const char *in_template, int size
if (vex.w == 0)
*obufp++ = 'h';
else
- {
- *obufp++ = '{';
- *obufp++ = 'b';
- *obufp++ = 'a';
- *obufp++ = 'd';
- *obufp++ = '}';
- }
+ oappend ("{bad}");
}
else
abort ();
@@ -10735,9 +10731,13 @@ putop (const char *in_template, int size
used_prefixes |= (prefixes & PREFIX_DATA);
}
}
+ break;
}
- else if (l == 1 && last[0] == 'L')
+ if (l != 1)
+ abort ();
+ switch (last[0])
{
+ case 'L':
if (address_mode == mode_64bit
&& !(prefixes & PREFIX_ADDR))
{
@@ -10747,9 +10747,15 @@ putop (const char *in_template, int size
}
goto case_S;
+ case 'X':
+ if (!vex.w)
+ *obufp++ = 's';
+ else
+ oappend ("{bad}");
+ break;
+ default:
+ abort ();
}
- else
- abort ();
break;
case 'V':
if (l == 0)
--- a/opcodes/i386-dis-evex.h
+++ b/opcodes/i386-dis-evex.h
@@ -593,9 +593,9 @@ static const struct dis386 evex_table[][
{ Bad_Opcode },
{ Bad_Opcode },
/* 08 */
- { VEX_W_TABLE (EVEX_W_0F3A08) },
+ { PREFIX_TABLE (PREFIX_EVEX_0F3A08) },
{ VEX_W_TABLE (EVEX_W_0F3A09) },
- { VEX_W_TABLE (EVEX_W_0F3A0A) },
+ { PREFIX_TABLE (PREFIX_EVEX_0F3A0A) },
{ VEX_W_TABLE (EVEX_W_0F3A0B) },
{ Bad_Opcode },
{ Bad_Opcode },
@@ -976,8 +976,8 @@ static const struct dis386 evex_table[][
/* 58 */
{ PREFIX_TABLE (PREFIX_EVEX_MAP5_58) },
{ PREFIX_TABLE (PREFIX_EVEX_MAP5_59) },
- { VEX_W_TABLE (EVEX_W_MAP5_5A) },
- { VEX_W_TABLE (EVEX_W_MAP5_5B) },
+ { PREFIX_TABLE (PREFIX_EVEX_MAP5_5A) },
+ { PREFIX_TABLE (PREFIX_EVEX_MAP5_5B) },
{ PREFIX_TABLE (PREFIX_EVEX_MAP5_5C) },
{ PREFIX_TABLE (PREFIX_EVEX_MAP5_5D) },
{ PREFIX_TABLE (PREFIX_EVEX_MAP5_5E) },
@@ -1015,7 +1015,7 @@ static const struct dis386 evex_table[][
{ PREFIX_TABLE (PREFIX_EVEX_MAP5_7A) },
{ PREFIX_TABLE (PREFIX_EVEX_MAP5_7B) },
{ PREFIX_TABLE (PREFIX_EVEX_MAP5_7C) },
- { VEX_W_TABLE (EVEX_W_MAP5_7D) },
+ { PREFIX_TABLE (PREFIX_EVEX_MAP5_7D) },
{ "vmovw", { Edw, XMScalar }, PREFIX_DATA },
{ Bad_Opcode },
/* 80 */
--- a/opcodes/i386-dis-evex-prefix.h
+++ b/opcodes/i386-dis-evex-prefix.h
@@ -375,17 +375,17 @@
{ "vfmsub213s%XW", { XMScalar, VexScalar, EXdq, EXxEVexR }, 0 },
{ "v4fnmaddss", { XMScalar, VexScalar, Mxmm }, 0 },
},
- /* PREFIX_EVEX_0F3A08_W_0 */
+ /* PREFIX_EVEX_0F3A08 */
{
- { "vrndscaleph", { XM, EXxh, EXxEVexS, Ib }, 0 },
+ { "vrndscalep%XH", { XM, EXxh, EXxEVexS, Ib }, 0 },
{ Bad_Opcode },
- { "vrndscaleps", { XM, EXx, EXxEVexS, Ib }, 0 },
+ { "vrndscalep%XS", { XM, EXx, EXxEVexS, Ib }, 0 },
},
- /* PREFIX_EVEX_0F3A0A_W_0 */
+ /* PREFIX_EVEX_0F3A0A */
{
- { "vrndscalesh", { XMScalar, VexScalar, EXw, EXxEVexS, Ib }, 0 },
+ { "vrndscales%XH", { XMScalar, VexScalar, EXw, EXxEVexS, Ib }, 0 },
{ Bad_Opcode },
- { "vrndscaless", { XMScalar, VexScalar, EXd, EXxEVexS, Ib }, 0 },
+ { "vrndscales%XS", { XMScalar, VexScalar, EXd, EXxEVexS, Ib }, 0 },
},
/* PREFIX_EVEX_0F3A26 */
{
@@ -482,27 +482,18 @@
{ "vmulp%XH", { XM, Vex, EXxh, EXxEVexR }, 0 },
{ "vmuls%XH", { XMM, VexScalar, EXw, EXxEVexR }, 0 },
},
- /* PREFIX_EVEX_MAP5_5A_W_0 */
+ /* PREFIX_EVEX_MAP5_5A */
{
- { "vcvtph2pd", { XM, EXxmmqdh, EXxEVexS }, 0 },
- { "vcvtsh2sd", { XMM, VexScalar, EXw, EXxEVexS }, 0 },
- },
- /* PREFIX_EVEX_MAP5_5A_W_1 */
- {
- { Bad_Opcode },
- { Bad_Opcode },
- { "vcvtpd2ph%XZ", { XMM, EXx, EXxEVexR }, 0 },
- { "vcvtsd2sh", { XMM, VexScalar, EXq, EXxEVexR }, 0 },
- },
- /* PREFIX_EVEX_MAP5_5B_W_0 */
- {
- { "vcvtdq2ph%XY", { XMxmmq, EXx, EXxEVexR }, 0 },
- { "vcvttph2dq", { XM, EXxmmqh, EXxEVexS }, 0 },
- { "vcvtph2dq", { XM, EXxmmqh, EXxEVexR }, 0 },
- },
- /* PREFIX_EVEX_MAP5_5B_W_1 */
- {
- { "vcvtqq2ph%XZ", { XMM, EXx, EXxEVexR }, 0 },
+ { "vcvtp%XH2pd", { XM, EXxmmqdh, EXxEVexS }, 0 },
+ { "vcvts%XH2sd", { XMM, VexScalar, EXw, EXxEVexS }, 0 },
+ { "vcvtp%XD2ph%XZ", { XMM, EXx, EXxEVexR }, 0 },
+ { "vcvts%XD2sh", { XMM, VexScalar, EXq, EXxEVexR }, 0 },
+ },
+ /* PREFIX_EVEX_MAP5_5B */
+ {
+ { VEX_W_TABLE (EVEX_W_MAP5_5B_P_0) },
+ { "vcvttp%XH2dq", { XM, EXxmmqh, EXxEVexS }, 0 },
+ { "vcvtp%XH2dq", { XM, EXxmmqh, EXxEVexR }, 0 },
},
/* PREFIX_EVEX_MAP5_5C */
{
@@ -526,47 +517,47 @@
},
/* PREFIX_EVEX_MAP5_78 */
{
- { VEX_W_TABLE (EVEX_W_MAP5_78_P_0) },
+ { "vcvttp%XH2udq", { XM, EXxmmqh, EXxEVexS }, 0 },
{ "vcvttsh2usi", { Gdq, EXw, EXxEVexS }, 0 },
- { VEX_W_TABLE (EVEX_W_MAP5_78_P_2) },
+ { "vcvttp%XH2uqq", { XM, EXxmmqdh, EXxEVexS }, 0 },
},
/* PREFIX_EVEX_MAP5_79 */
{
- { VEX_W_TABLE (EVEX_W_MAP5_79_P_0) },
+ { "vcvtp%XH2udq", { XM, EXxmmqh, EXxEVexR }, 0 },
{ "vcvtsh2usi", { Gdq, EXw, EXxEVexR }, 0 },
- { VEX_W_TABLE (EVEX_W_MAP5_79_P_2) },
+ { "vcvtp%XH2uqq", { XM, EXxmmqdh, EXxEVexR }, 0 },
},
/* PREFIX_EVEX_MAP5_7A */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (EVEX_W_MAP5_7A_P_2) },
+ { "vcvttp%XH2qq", { XM, EXxmmqdh, EXxEVexS }, 0 },
{ VEX_W_TABLE (EVEX_W_MAP5_7A_P_3) },
},
/* PREFIX_EVEX_MAP5_7B */
{
{ Bad_Opcode },
{ "vcvtusi2sh{%LQ|}", { XMScalar, VexScalar, EXxEVexR, Edq }, 0 },
- { VEX_W_TABLE (EVEX_W_MAP5_7B_P_2) },
+ { "vcvtp%XH2qq", { XM, EXxmmqdh, EXxEVexR }, 0 },
},
/* PREFIX_EVEX_MAP5_7C */
{
- { VEX_W_TABLE (EVEX_W_MAP5_7C_P_0) },
+ { "vcvttp%XH2uw", { XM, EXxh, EXxEVexS }, 0 },
{ Bad_Opcode },
- { VEX_W_TABLE (EVEX_W_MAP5_7C_P_2) },
+ { "vcvttp%XH2w", { XM, EXxh, EXxEVexS }, 0 },
},
- /* PREFIX_EVEX_MAP5_7D_W_0 */
+ /* PREFIX_EVEX_MAP5_7D */
{
- { "vcvtph2uw", { XM, EXxh, EXxEVexR }, 0 },
- { "vcvtw2ph", { XM, EXxh, EXxEVexR }, 0 },
- { "vcvtph2w", { XM, EXxh, EXxEVexR }, 0 },
- { "vcvtuw2ph", { XM, EXxh, EXxEVexR }, 0 },
+ { "vcvtp%XH2uw", { XM, EXxh, EXxEVexR }, 0 },
+ { "vcvtw2p%XH", { XM, EXxh, EXxEVexR }, 0 },
+ { "vcvtp%XH2w", { XM, EXxh, EXxEVexR }, 0 },
+ { "vcvtuw2p%XH", { XM, EXxh, EXxEVexR }, 0 },
},
/* PREFIX_EVEX_MAP6_13 */
{
- { VEX_W_TABLE (EVEX_W_MAP6_13_P_0) },
+ { "vcvts%XH2ss", { XMM, VexScalar, EXw, EXxEVexS }, 0 },
{ Bad_Opcode },
- { VEX_W_TABLE (EVEX_W_MAP6_13_P_2) },
+ { "vcvtp%XH2psx", { XM, EXxmmqh, EXxEVexS }, 0 },
},
/* PREFIX_EVEX_MAP6_56 */
{
--- a/opcodes/i386-dis-evex-w.h
+++ b/opcodes/i386-dis-evex-w.h
@@ -550,19 +550,11 @@
{ Bad_Opcode },
{ "vpermilpd", { XM, EXx, Ib }, PREFIX_DATA },
},
- /* EVEX_W_0F3A08 */
- {
- { PREFIX_TABLE (PREFIX_EVEX_0F3A08_W_0) },
- },
/* EVEX_W_0F3A09 */
{
{ Bad_Opcode },
{ "vrndscalepd", { XM, EXx, EXxEVexS, Ib }, PREFIX_DATA },
},
- /* EVEX_W_0F3A0A */
- {
- { PREFIX_TABLE (PREFIX_EVEX_0F3A0A_W_0) },
- },
/* EVEX_W_0F3A0B */
{
{ Bad_Opcode },
@@ -636,62 +628,13 @@
{ Bad_Opcode },
{ "vpshrdw", { XM, Vex, EXx, Ib }, 0 },
},
- /* EVEX_W_MAP5_5A */
- {
- { PREFIX_TABLE (PREFIX_EVEX_MAP5_5A_W_0) },
- { PREFIX_TABLE (PREFIX_EVEX_MAP5_5A_W_1) },
- },
- /* EVEX_W_MAP5_5B */
- {
- { PREFIX_TABLE (PREFIX_EVEX_MAP5_5B_W_0) },
- { PREFIX_TABLE (PREFIX_EVEX_MAP5_5B_W_1) },
- },
- /* EVEX_W_MAP5_78_P_0 */
- {
- { "vcvttph2udq", { XM, EXxmmqh, EXxEVexS }, 0 },
- },
- /* EVEX_W_MAP5_78_P_2 */
- {
- { "vcvttph2uqq", { XM, EXxmmqdh, EXxEVexS }, 0 },
- },
- /* EVEX_W_MAP5_79_P_0 */
- {
- { "vcvtph2udq", { XM, EXxmmqh, EXxEVexR }, 0 },
- },
- /* EVEX_W_MAP5_79_P_2 */
+ /* EVEX_W_MAP5_5B_P_0 */
{
- { "vcvtph2uqq", { XM, EXxmmqdh, EXxEVexR }, 0 },
- },
- /* EVEX_W_MAP5_7A_P_2 */
- {
- { "vcvttph2qq", { XM, EXxmmqdh, EXxEVexS }, 0 },
+ { "vcvtdq2ph%XY", { XMxmmq, EXx, EXxEVexR }, 0 },
+ { "vcvtqq2ph%XZ", { XMM, EXx, EXxEVexR }, 0 },
},
/* EVEX_W_MAP5_7A_P_3 */
{
{ "vcvtudq2ph%XY", { XMxmmq, EXx, EXxEVexR }, 0 },
{ "vcvtuqq2ph%XZ", { XMM, EXx, EXxEVexR }, 0 },
},
- /* EVEX_W_MAP5_7B_P_2 */
- {
- { "vcvtph2qq", { XM, EXxmmqdh, EXxEVexR }, 0 },
- },
- /* EVEX_W_MAP5_7C_P_0 */
- {
- { "vcvttph2uw", { XM, EXxh, EXxEVexS }, 0 },
- },
- /* EVEX_W_MAP5_7C_P_2 */
- {
- { "vcvttph2w", { XM, EXxh, EXxEVexS }, 0 },
- },
- /* EVEX_W_MAP5_7D */
- {
- { PREFIX_TABLE (PREFIX_EVEX_MAP5_7D_W_0) },
- },
- /* EVEX_W_MAP6_13_P_0 */
- {
- { "vcvtsh2ss", { XMM, VexScalar, EXw, EXxEVexS }, 0 },
- },
- /* EVEX_W_MAP6_13_P_2 */
- {
- { "vcvtph2psx", { XM, EXxmmqh, EXxEVexS }, 0 },
- },
^ permalink raw reply [flat|nested] 8+ messages in thread* [PATCH 2/6] x86: reduce AVX512 FP set of insns decoded through vex_w_table[]
2022-01-05 11:31 [PATCH 0/6] x86: AVX512* / EVEX decoding adjustments Jan Beulich
2022-01-05 11:32 ` [PATCH 1/6] x86: reduce AVX512-FP16 set of insns decoded through vex_w_table[] Jan Beulich
@ 2022-01-05 11:33 ` Jan Beulich
2022-01-05 11:34 ` [PATCH 3/6] x86: record further wrong uses of EVEX.b Jan Beulich
` (4 subsequent siblings)
6 siblings, 0 replies; 8+ messages in thread
From: Jan Beulich @ 2022-01-05 11:33 UTC (permalink / raw)
To: Binutils
Like for AVX512-FP16, there's not that many FP insns where going through
this table is easier / cheaper than using suitable macros. Utilize %XS
and %XD more to eliminate a fair number of table entries.
While doing this I noticed a few anomalies. Where lines get touched /
moved anyway, these are being addressed right here:
- vmovshdup used EXx for its 2nd operand, thus displaying seemingly
valid broadcast when EVEX.b is set with a memory operand; use
EXEvexXNoBcst instead just like vmovsldup already does
- vmovlhps used EXx for its 3rd operand, when all sibling entries use
EXq; switch to EXq there for consistency (the two differ only for
memory operands)
---
Note that a similar issue to that with vmovshdup exists in AT&T mode for
vmovddup, but that needs fixing elsewhere and hence doesn't get taken
care of right here. Quite likely there are more similar issues elsewhere
anyway.
--- a/opcodes/i386-dis.c
+++ b/opcodes/i386-dis.c
@@ -1504,36 +1504,7 @@ enum
VEX_W_0FXOP_09_E2_L_0,
VEX_W_0FXOP_09_E3_L_0,
- EVEX_W_0F10_P_1,
- EVEX_W_0F10_P_3,
- EVEX_W_0F11_P_1,
- EVEX_W_0F11_P_3,
- EVEX_W_0F12_P_0_M_1,
- EVEX_W_0F12_P_1,
- EVEX_W_0F12_P_3,
- EVEX_W_0F16_P_0_M_1,
- EVEX_W_0F16_P_1,
- EVEX_W_0F51_P_1,
- EVEX_W_0F51_P_3,
- EVEX_W_0F58_P_1,
- EVEX_W_0F58_P_3,
- EVEX_W_0F59_P_1,
- EVEX_W_0F59_P_3,
- EVEX_W_0F5A_P_0,
- EVEX_W_0F5A_P_1,
- EVEX_W_0F5A_P_2,
- EVEX_W_0F5A_P_3,
EVEX_W_0F5B_P_0,
- EVEX_W_0F5B_P_1,
- EVEX_W_0F5B_P_2,
- EVEX_W_0F5C_P_1,
- EVEX_W_0F5C_P_3,
- EVEX_W_0F5D_P_1,
- EVEX_W_0F5D_P_3,
- EVEX_W_0F5E_P_1,
- EVEX_W_0F5E_P_3,
- EVEX_W_0F5F_P_1,
- EVEX_W_0F5F_P_3,
EVEX_W_0F62,
EVEX_W_0F66,
EVEX_W_0F6A,
@@ -1561,15 +1532,11 @@ enum
EVEX_W_0F7F_P_1,
EVEX_W_0F7F_P_2,
EVEX_W_0F7F_P_3,
- EVEX_W_0FC2_P_1,
- EVEX_W_0FC2_P_3,
EVEX_W_0FD2,
EVEX_W_0FD3,
EVEX_W_0FD4,
EVEX_W_0FD6,
EVEX_W_0FE6_P_1,
- EVEX_W_0FE6_P_2,
- EVEX_W_0FE6_P_3,
EVEX_W_0FE7,
EVEX_W_0FF2,
EVEX_W_0FF3,
@@ -1577,7 +1544,7 @@ enum
EVEX_W_0FFA,
EVEX_W_0FFB,
EVEX_W_0FFE,
- EVEX_W_0F380D,
+
EVEX_W_0F3810_P_1,
EVEX_W_0F3810_P_2,
EVEX_W_0F3811_P_1,
@@ -1585,7 +1552,6 @@ enum
EVEX_W_0F3812_P_1,
EVEX_W_0F3812_P_2,
EVEX_W_0F3813_P_1,
- EVEX_W_0F3813_P_2,
EVEX_W_0F3814_P_1,
EVEX_W_0F3815_P_1,
EVEX_W_0F3819_L_n,
@@ -1614,21 +1580,15 @@ enum
EVEX_W_0F3835_P_2,
EVEX_W_0F3837,
EVEX_W_0F383A_P_1,
- EVEX_W_0F3852_P_1,
EVEX_W_0F3859,
EVEX_W_0F385A_M_0_L_n,
EVEX_W_0F385B_M_0_L_2,
EVEX_W_0F3870,
- EVEX_W_0F3872_P_1,
EVEX_W_0F3872_P_2,
- EVEX_W_0F3872_P_3,
EVEX_W_0F387A,
EVEX_W_0F387B,
EVEX_W_0F3883,
- EVEX_W_0F3A05,
- EVEX_W_0F3A09,
- EVEX_W_0F3A0B,
EVEX_W_0F3A18_L_n,
EVEX_W_0F3A19_L_n,
EVEX_W_0F3A1A_L_2,
--- a/opcodes/i386-dis-evex.h
+++ b/opcodes/i386-dis-evex.h
@@ -307,7 +307,7 @@ static const struct dis386 evex_table[][
{ Bad_Opcode },
{ "vpmulhrsw", { XM, Vex, EXx }, PREFIX_DATA },
{ VEX_W_TABLE (VEX_W_0F380C) },
- { VEX_W_TABLE (EVEX_W_0F380D) },
+ { "vpermilp%XD", { XM, Vex, EXx }, PREFIX_DATA },
{ Bad_Opcode },
{ Bad_Opcode },
/* 10 */
@@ -589,14 +589,14 @@ static const struct dis386 evex_table[][
{ Bad_Opcode },
{ "valign%DQ", { XM, Vex, EXx, Ib }, PREFIX_DATA },
{ VEX_W_TABLE (VEX_W_0F3A04) },
- { VEX_W_TABLE (EVEX_W_0F3A05) },
+ { "vpermilp%XD", { XM, EXx, Ib }, PREFIX_DATA },
{ Bad_Opcode },
{ Bad_Opcode },
/* 08 */
{ PREFIX_TABLE (PREFIX_EVEX_0F3A08) },
- { VEX_W_TABLE (EVEX_W_0F3A09) },
+ { "vrndscalep%XD", { XM, EXx, EXxEVexS, Ib }, PREFIX_DATA },
{ PREFIX_TABLE (PREFIX_EVEX_0F3A0A) },
- { VEX_W_TABLE (EVEX_W_0F3A0B) },
+ { "vrndscales%XD", { XMScalar, VexScalar, EXq, EXxEVexS, Ib }, PREFIX_DATA },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
--- a/opcodes/i386-dis-evex-mod.h
+++ b/opcodes/i386-dis-evex-mod.h
@@ -1,7 +1,7 @@
{
/* MOD_EVEX_0F12_PREFIX_0 */
{ "vmovlpX", { XMM, Vex, EXq }, PREFIX_OPCODE },
- { VEX_W_TABLE (EVEX_W_0F12_P_0_M_1) },
+ { "vmovhlp%XS", { XMM, Vex, EXq }, 0 },
},
{
/* MOD_EVEX_0F12_PREFIX_2 */
@@ -14,7 +14,7 @@
{
/* MOD_EVEX_0F16_PREFIX_0 */
{ "vmovhpX", { XMM, Vex, EXq }, PREFIX_OPCODE },
- { VEX_W_TABLE (EVEX_W_0F16_P_0_M_1) },
+ { "vmovlhp%XS", { XMM, Vex, EXq }, 0 },
},
{
/* MOD_EVEX_0F16_PREFIX_2 */
--- a/opcodes/i386-dis-evex-prefix.h
+++ b/opcodes/i386-dis-evex-prefix.h
@@ -1,28 +1,28 @@
/* PREFIX_EVEX_0F10 */
{
{ "vmovupX", { XM, EXEvexXNoBcst }, PREFIX_OPCODE },
- { VEX_W_TABLE (EVEX_W_0F10_P_1) },
+ { "vmovs%XS", { XMScalar, VexScalarR, EXd }, 0 },
{ "vmovupX", { XM, EXEvexXNoBcst }, PREFIX_OPCODE },
- { VEX_W_TABLE (EVEX_W_0F10_P_3) },
+ { "vmovs%XD", { XMScalar, VexScalarR, EXq }, 0 },
},
/* PREFIX_EVEX_0F11 */
{
{ "vmovupX", { EXxS, XM }, PREFIX_OPCODE },
- { VEX_W_TABLE (EVEX_W_0F11_P_1) },
+ { "vmovs%XS", { EXdS, VexScalarR, XMScalar }, 0 },
{ "vmovupX", { EXxS, XM }, PREFIX_OPCODE },
- { VEX_W_TABLE (EVEX_W_0F11_P_3) },
+ { "vmovs%XD", { EXqS, VexScalarR, XMScalar }, 0 },
},
/* PREFIX_EVEX_0F12 */
{
{ MOD_TABLE (MOD_EVEX_0F12_PREFIX_0) },
- { VEX_W_TABLE (EVEX_W_0F12_P_1) },
+ { "vmov%XSldup", { XM, EXEvexXNoBcst }, 0 },
{ MOD_TABLE (MOD_EVEX_0F12_PREFIX_2) },
- { VEX_W_TABLE (EVEX_W_0F12_P_3) },
+ { "vmov%XDdup", { XM, EXymmq }, 0 },
},
/* PREFIX_EVEX_0F16 */
{
{ MOD_TABLE (MOD_EVEX_0F16_PREFIX_0) },
- { VEX_W_TABLE (EVEX_W_0F16_P_1) },
+ { "vmov%XShdup", { XM, EXEvexXNoBcst }, 0 },
{ MOD_TABLE (MOD_EVEX_0F16_PREFIX_2) },
},
/* PREFIX_EVEX_0F2A */
@@ -35,64 +35,64 @@
/* PREFIX_EVEX_0F51 */
{
{ "vsqrtpX", { XM, EXx, EXxEVexR }, PREFIX_OPCODE },
- { VEX_W_TABLE (EVEX_W_0F51_P_1) },
+ { "vsqrts%XS", { XMScalar, VexScalar, EXd, EXxEVexR }, 0 },
{ "vsqrtpX", { XM, EXx, EXxEVexR }, PREFIX_OPCODE },
- { VEX_W_TABLE (EVEX_W_0F51_P_3) },
+ { "vsqrts%XD", { XMScalar, VexScalar, EXq, EXxEVexR }, 0 },
},
/* PREFIX_EVEX_0F58 */
{
{ "vaddpX", { XM, Vex, EXx, EXxEVexR }, PREFIX_OPCODE },
- { VEX_W_TABLE (EVEX_W_0F58_P_1) },
+ { "vadds%XS", { XMScalar, VexScalar, EXd, EXxEVexR }, 0 },
{ "vaddpX", { XM, Vex, EXx, EXxEVexR }, PREFIX_OPCODE },
- { VEX_W_TABLE (EVEX_W_0F58_P_3) },
+ { "vadds%XD", { XMScalar, VexScalar, EXq, EXxEVexR }, 0 },
},
/* PREFIX_EVEX_0F59 */
{
{ "vmulpX", { XM, Vex, EXx, EXxEVexR }, PREFIX_OPCODE },
- { VEX_W_TABLE (EVEX_W_0F59_P_1) },
+ { "vmuls%XS", { XMScalar, VexScalar, EXd, EXxEVexR }, 0 },
{ "vmulpX", { XM, Vex, EXx, EXxEVexR }, PREFIX_OPCODE },
- { VEX_W_TABLE (EVEX_W_0F59_P_3) },
+ { "vmuls%XD", { XMScalar, VexScalar, EXq, EXxEVexR }, 0 },
},
/* PREFIX_EVEX_0F5A */
{
- { VEX_W_TABLE (EVEX_W_0F5A_P_0) },
- { VEX_W_TABLE (EVEX_W_0F5A_P_1) },
- { VEX_W_TABLE (EVEX_W_0F5A_P_2) },
- { VEX_W_TABLE (EVEX_W_0F5A_P_3) },
+ { "vcvtp%XS2pd", { XM, EXEvexHalfBcstXmmq, EXxEVexS }, 0 },
+ { "vcvts%XS2sd", { XMScalar, VexScalar, EXd, EXxEVexS }, 0 },
+ { "vcvtp%XD2ps%XY", { XMxmmq, EXx, EXxEVexR }, 0 },
+ { "vcvts%XD2ss", { XMScalar, VexScalar, EXq, EXxEVexR }, 0 },
},
/* PREFIX_EVEX_0F5B */
{
{ VEX_W_TABLE (EVEX_W_0F5B_P_0) },
- { VEX_W_TABLE (EVEX_W_0F5B_P_1) },
- { VEX_W_TABLE (EVEX_W_0F5B_P_2) },
+ { "vcvttp%XS2dq", { XM, EXx, EXxEVexS }, 0 },
+ { "vcvtp%XS2dq", { XM, EXx, EXxEVexR }, 0 },
},
/* PREFIX_EVEX_0F5C */
{
{ "vsubpX", { XM, Vex, EXx, EXxEVexR }, PREFIX_OPCODE },
- { VEX_W_TABLE (EVEX_W_0F5C_P_1) },
+ { "vsubs%XS", { XMScalar, VexScalar, EXd, EXxEVexR }, 0 },
{ "vsubpX", { XM, Vex, EXx, EXxEVexR }, PREFIX_OPCODE },
- { VEX_W_TABLE (EVEX_W_0F5C_P_3) },
+ { "vsubs%XD", { XMScalar, VexScalar, EXq, EXxEVexR }, 0 },
},
/* PREFIX_EVEX_0F5D */
{
{ "vminpX", { XM, Vex, EXx, EXxEVexS }, PREFIX_OPCODE },
- { VEX_W_TABLE (EVEX_W_0F5D_P_1) },
+ { "vmins%XS", { XMScalar, VexScalar, EXd, EXxEVexS }, 0 },
{ "vminpX", { XM, Vex, EXx, EXxEVexS }, PREFIX_OPCODE },
- { VEX_W_TABLE (EVEX_W_0F5D_P_3) },
+ { "vmins%XD", { XMScalar, VexScalar, EXq, EXxEVexS }, 0 },
},
/* PREFIX_EVEX_0F5E */
{
{ "vdivpX", { XM, Vex, EXx, EXxEVexR }, PREFIX_OPCODE },
- { VEX_W_TABLE (EVEX_W_0F5E_P_1) },
+ { "vdivs%XS", { XMScalar, VexScalar, EXd, EXxEVexR }, 0 },
{ "vdivpX", { XM, Vex, EXx, EXxEVexR }, PREFIX_OPCODE },
- { VEX_W_TABLE (EVEX_W_0F5E_P_3) },
+ { "vdivs%XD", { XMScalar, VexScalar, EXq, EXxEVexR }, 0 },
},
/* PREFIX_EVEX_0F5F */
{
{ "vmaxpX", { XM, Vex, EXx, EXxEVexS }, PREFIX_OPCODE },
- { VEX_W_TABLE (EVEX_W_0F5F_P_1) },
+ { "vmaxs%XS", { XMScalar, VexScalar, EXd, EXxEVexS }, 0 },
{ "vmaxpX", { XM, Vex, EXx, EXxEVexS }, PREFIX_OPCODE },
- { VEX_W_TABLE (EVEX_W_0F5F_P_3) },
+ { "vmaxs%XD", { XMScalar, VexScalar, EXq, EXxEVexS }, 0 },
},
/* PREFIX_EVEX_0F6F */
{
@@ -152,16 +152,16 @@
/* PREFIX_EVEX_0FC2 */
{
{ "vcmppX", { MaskG, Vex, EXx, EXxEVexS, CMP }, PREFIX_OPCODE },
- { VEX_W_TABLE (EVEX_W_0FC2_P_1) },
+ { "vcmps%XS", { MaskG, VexScalar, EXd, EXxEVexS, CMP }, 0 },
{ "vcmppX", { MaskG, Vex, EXx, EXxEVexS, CMP }, PREFIX_OPCODE },
- { VEX_W_TABLE (EVEX_W_0FC2_P_3) },
+ { "vcmps%XD", { MaskG, VexScalar, EXq, EXxEVexS, CMP }, 0 },
},
/* PREFIX_EVEX_0FE6 */
{
{ Bad_Opcode },
{ VEX_W_TABLE (EVEX_W_0FE6_P_1) },
- { VEX_W_TABLE (EVEX_W_0FE6_P_2) },
- { VEX_W_TABLE (EVEX_W_0FE6_P_3) },
+ { "vcvttp%XD2dq%XY", { XMxmmq, EXx, EXxEVexS }, 0 },
+ { "vcvtp%XD2dq%XY", { XMxmmq, EXx, EXxEVexR }, 0 },
},
/* PREFIX_EVEX_0F3810 */
{
@@ -185,7 +185,7 @@
{
{ Bad_Opcode },
{ VEX_W_TABLE (EVEX_W_0F3813_P_1) },
- { VEX_W_TABLE (EVEX_W_0F3813_P_2) },
+ { "vcvtph2p%XS", { XM, EXxmmq, EXxEVexS }, 0 },
},
/* PREFIX_EVEX_0F3814 */
{
@@ -322,7 +322,7 @@
/* PREFIX_EVEX_0F3852 */
{
{ Bad_Opcode },
- { VEX_W_TABLE (EVEX_W_0F3852_P_1) },
+ { "vdpbf16p%XS", { XM, Vex, EXx }, 0 },
{ "vpdpwssd", { XM, Vex, EXx }, 0 },
{ "vp4dpwssd", { XM, Vex, EXxmm }, 0 },
},
@@ -343,9 +343,9 @@
/* PREFIX_EVEX_0F3872 */
{
{ Bad_Opcode },
- { VEX_W_TABLE (EVEX_W_0F3872_P_1) },
+ { "vcvtnep%XS2bf16%XY", { XMxmmq, EXx }, 0 },
{ VEX_W_TABLE (EVEX_W_0F3872_P_2) },
- { VEX_W_TABLE (EVEX_W_0F3872_P_3) },
+ { "vcvtne2p%XS2bf16", { XM, Vex, EXx}, 0 },
},
/* PREFIX_EVEX_0F389A */
{
--- a/opcodes/i386-dis-evex-w.h
+++ b/opcodes/i386-dis-evex-w.h
@@ -1,136 +1,8 @@
- /* EVEX_W_0F10_P_1 */
- {
- { "vmovss", { XMScalar, VexScalarR, EXd }, 0 },
- },
- /* EVEX_W_0F10_P_3 */
- {
- { Bad_Opcode },
- { "vmovsd", { XMScalar, VexScalarR, EXq }, 0 },
- },
- /* EVEX_W_0F11_P_1 */
- {
- { "vmovss", { EXdS, VexScalarR, XMScalar }, 0 },
- },
- /* EVEX_W_0F11_P_3 */
- {
- { Bad_Opcode },
- { "vmovsd", { EXqS, VexScalarR, XMScalar }, 0 },
- },
- /* EVEX_W_0F12_P_0_M_1 */
- {
- { "vmovhlps", { XMM, Vex, EXq }, 0 },
- },
- /* EVEX_W_0F12_P_1 */
- {
- { "vmovsldup", { XM, EXEvexXNoBcst }, 0 },
- },
- /* EVEX_W_0F12_P_3 */
- {
- { Bad_Opcode },
- { "vmovddup", { XM, EXymmq }, 0 },
- },
- /* EVEX_W_0F16_P_0_M_1 */
- {
- { "vmovlhps", { XMM, Vex, EXx }, 0 },
- },
- /* EVEX_W_0F16_P_1 */
- {
- { "vmovshdup", { XM, EXx }, 0 },
- },
- /* EVEX_W_0F51_P_1 */
- {
- { "vsqrtss", { XMScalar, VexScalar, EXd, EXxEVexR }, 0 },
- },
- /* EVEX_W_0F51_P_3 */
- {
- { Bad_Opcode },
- { "vsqrtsd", { XMScalar, VexScalar, EXq, EXxEVexR }, 0 },
- },
- /* EVEX_W_0F58_P_1 */
- {
- { "vaddss", { XMScalar, VexScalar, EXd, EXxEVexR }, 0 },
- },
- /* EVEX_W_0F58_P_3 */
- {
- { Bad_Opcode },
- { "vaddsd", { XMScalar, VexScalar, EXq, EXxEVexR }, 0 },
- },
- /* EVEX_W_0F59_P_1 */
- {
- { "vmulss", { XMScalar, VexScalar, EXd, EXxEVexR }, 0 },
- },
- /* EVEX_W_0F59_P_3 */
- {
- { Bad_Opcode },
- { "vmulsd", { XMScalar, VexScalar, EXq, EXxEVexR }, 0 },
- },
- /* EVEX_W_0F5A_P_0 */
- {
- { "vcvtps2pd", { XM, EXEvexHalfBcstXmmq, EXxEVexS }, 0 },
- },
- /* EVEX_W_0F5A_P_1 */
- {
- { "vcvtss2sd", { XMScalar, VexScalar, EXd, EXxEVexS }, 0 },
- },
- /* EVEX_W_0F5A_P_2 */
- {
- { Bad_Opcode },
- { "vcvtpd2ps%XY", { XMxmmq, EXx, EXxEVexR }, 0 },
- },
- /* EVEX_W_0F5A_P_3 */
- {
- { Bad_Opcode },
- { "vcvtsd2ss", { XMScalar, VexScalar, EXq, EXxEVexR }, 0 },
- },
/* EVEX_W_0F5B_P_0 */
{
{ "vcvtdq2ps", { XM, EXx, EXxEVexR }, 0 },
{ "vcvtqq2ps%XY", { XMxmmq, EXx, EXxEVexR }, 0 },
},
- /* EVEX_W_0F5B_P_1 */
- {
- { "vcvttps2dq", { XM, EXx, EXxEVexS }, 0 },
- },
- /* EVEX_W_0F5B_P_2 */
- {
- { "vcvtps2dq", { XM, EXx, EXxEVexR }, 0 },
- },
- /* EVEX_W_0F5C_P_1 */
- {
- { "vsubss", { XMScalar, VexScalar, EXd, EXxEVexR }, 0 },
- },
- /* EVEX_W_0F5C_P_3 */
- {
- { Bad_Opcode },
- { "vsubsd", { XMScalar, VexScalar, EXq, EXxEVexR }, 0 },
- },
- /* EVEX_W_0F5D_P_1 */
- {
- { "vminss", { XMScalar, VexScalar, EXd, EXxEVexS }, 0 },
- },
- /* EVEX_W_0F5D_P_3 */
- {
- { Bad_Opcode },
- { "vminsd", { XMScalar, VexScalar, EXq, EXxEVexS }, 0 },
- },
- /* EVEX_W_0F5E_P_1 */
- {
- { "vdivss", { XMScalar, VexScalar, EXd, EXxEVexR }, 0 },
- },
- /* EVEX_W_0F5E_P_3 */
- {
- { Bad_Opcode },
- { "vdivsd", { XMScalar, VexScalar, EXq, EXxEVexR }, 0 },
- },
- /* EVEX_W_0F5F_P_1 */
- {
- { "vmaxss", { XMScalar, VexScalar, EXd, EXxEVexS }, 0 },
- },
- /* EVEX_W_0F5F_P_3 */
- {
- { Bad_Opcode },
- { "vmaxsd", { XMScalar, VexScalar, EXq, EXxEVexS }, 0 },
- },
/* EVEX_W_0F62 */
{
{ "vpunpckldq", { XM, Vex, EXx }, PREFIX_DATA },
@@ -258,15 +130,6 @@
{ "vmovdqu8", { EXxS, XM }, 0 },
{ "vmovdqu16", { EXxS, XM }, 0 },
},
- /* EVEX_W_0FC2_P_1 */
- {
- { "vcmpss", { MaskG, VexScalar, EXd, EXxEVexS, CMP }, 0 },
- },
- /* EVEX_W_0FC2_P_3 */
- {
- { Bad_Opcode },
- { "vcmpsd", { MaskG, VexScalar, EXq, EXxEVexS, CMP }, 0 },
- },
/* EVEX_W_0FD2 */
{
{ "vpsrld", { XM, Vex, EXxmm }, PREFIX_DATA },
@@ -291,16 +154,6 @@
{ "vcvtdq2pd", { XM, EXEvexHalfBcstXmmq }, 0 },
{ "vcvtqq2pd", { XM, EXx, EXxEVexR }, 0 },
},
- /* EVEX_W_0FE6_P_2 */
- {
- { Bad_Opcode },
- { "vcvttpd2dq%XY", { XMxmmq, EXx, EXxEVexS }, 0 },
- },
- /* EVEX_W_0FE6_P_3 */
- {
- { Bad_Opcode },
- { "vcvtpd2dq%XY", { XMxmmq, EXx, EXxEVexR }, 0 },
- },
/* EVEX_W_0FE7 */
{
{ "vmovntdq", { EXEvexXNoBcst, XM }, PREFIX_DATA },
@@ -332,11 +185,6 @@
{
{ "vpaddd", { XM, Vex, EXx }, PREFIX_DATA },
},
- /* EVEX_W_0F380D */
- {
- { Bad_Opcode },
- { "vpermilpd", { XM, Vex, EXx }, PREFIX_DATA },
- },
/* EVEX_W_0F3810_P_1 */
{
{ "vpmovuswb", { EXxmmq, XM }, 0 },
@@ -368,10 +216,6 @@
{
{ "vpmovusdw", { EXxmmq, XM }, 0 },
},
- /* EVEX_W_0F3813_P_2 */
- {
- { "vcvtph2ps", { XM, EXxmmq, EXxEVexS }, 0 },
- },
/* EVEX_W_0F3814_P_1 */
{
{ "vpmovusqw", { EXxmmqd, XM }, 0 },
@@ -492,11 +336,6 @@
{
{ MOD_TABLE (MOD_EVEX_0F383A_P_1_W_0) },
},
- /* EVEX_W_0F3852_P_1 */
- {
- { "vdpbf16ps", { XM, Vex, EXx }, 0 },
- { Bad_Opcode },
- },
/* EVEX_W_0F3859 */
{
{ "vbroadcasti32x2", { XM, EXq }, PREFIX_DATA },
@@ -517,21 +356,11 @@
{ Bad_Opcode },
{ "vpshldvw", { XM, Vex, EXx }, PREFIX_DATA },
},
- /* EVEX_W_0F3872_P_1 */
- {
- { "vcvtneps2bf16%XY", { XMxmmq, EXx }, 0 },
- { Bad_Opcode },
- },
/* EVEX_W_0F3872_P_2 */
{
{ Bad_Opcode },
{ "vpshrdvw", { XM, Vex, EXx }, 0 },
},
- /* EVEX_W_0F3872_P_3 */
- {
- { "vcvtne2ps2bf16", { XM, Vex, EXx}, 0 },
- { Bad_Opcode },
- },
/* EVEX_W_0F387A */
{
{ MOD_TABLE (MOD_EVEX_0F387A_W_0) },
@@ -545,21 +374,6 @@
{ Bad_Opcode },
{ "vpmultishiftqb", { XM, Vex, EXx }, PREFIX_DATA },
},
- /* EVEX_W_0F3A05 */
- {
- { Bad_Opcode },
- { "vpermilpd", { XM, EXx, Ib }, PREFIX_DATA },
- },
- /* EVEX_W_0F3A09 */
- {
- { Bad_Opcode },
- { "vrndscalepd", { XM, EXx, EXxEVexS, Ib }, PREFIX_DATA },
- },
- /* EVEX_W_0F3A0B */
- {
- { Bad_Opcode },
- { "vrndscalesd", { XMScalar, VexScalar, EXq, EXxEVexS, Ib }, PREFIX_DATA },
- },
/* EVEX_W_0F3A18_L_n */
{
{ "vinsertf32x4", { XM, Vex, EXxmm, Ib }, PREFIX_DATA },
^ permalink raw reply [flat|nested] 8+ messages in thread* [PATCH 3/6] x86: record further wrong uses of EVEX.b
2022-01-05 11:31 [PATCH 0/6] x86: AVX512* / EVEX decoding adjustments Jan Beulich
2022-01-05 11:32 ` [PATCH 1/6] x86: reduce AVX512-FP16 set of insns decoded through vex_w_table[] Jan Beulich
2022-01-05 11:33 ` [PATCH 2/6] x86: reduce AVX512 FP " Jan Beulich
@ 2022-01-05 11:34 ` Jan Beulich
2022-01-05 11:35 ` [PATCH 4/6] x86: consistently use scalar_mode for AVX512-FP16 scalar insns Jan Beulich
` (3 subsequent siblings)
6 siblings, 0 replies; 8+ messages in thread
From: Jan Beulich @ 2022-01-05 11:34 UTC (permalink / raw)
To: Binutils
For one EVEX.W set does not imply EVEX.b is uniformly valid. Reject it
for modes which occur for insns allowing for EVEX.W to be set (noticed
with VMOV{H,L}PD and VMOVDDUP, and only in AT&T mode, but not checked
whether further insns would also have been impacted; I expect e.g.
VCMPSD would have had the same issue). And then the present concept of
broadcast makes no sense at all when the memory operand of an insn is
the destination.
--- a/opcodes/i386-dis.c
+++ b/opcodes/i386-dis.c
@@ -11877,6 +11877,11 @@ OP_E_memory (int bytemode, int sizeflag)
if (vex.b)
{
evex_used |= EVEX_b_used;
+
+ /* Broadcast can only ever be valid for memory sources. */
+ if (obufp == op_out[0])
+ vex.no_broadcast = 1;
+
if (!vex.no_broadcast)
{
if (bytemode == xh_mode)
@@ -11901,6 +11906,9 @@ OP_E_memory (int bytemode, int sizeflag)
}
}
}
+ else if (bytemode == q_mode
+ || bytemode == ymmq_mode)
+ vex.no_broadcast = 1;
else if (vex.w
|| bytemode == evex_half_bcst_xmmqdh_mode
|| bytemode == evex_half_bcst_xmmq_mode)
^ permalink raw reply [flat|nested] 8+ messages in thread* [PATCH 4/6] x86: consistently use scalar_mode for AVX512-FP16 scalar insns
2022-01-05 11:31 [PATCH 0/6] x86: AVX512* / EVEX decoding adjustments Jan Beulich
` (2 preceding siblings ...)
2022-01-05 11:34 ` [PATCH 3/6] x86: record further wrong uses of EVEX.b Jan Beulich
@ 2022-01-05 11:35 ` Jan Beulich
2022-01-05 11:35 ` [PATCH 5/6] x86: share yet more VEX table entries with EVEX decoding Jan Beulich
` (2 subsequent siblings)
6 siblings, 0 replies; 8+ messages in thread
From: Jan Beulich @ 2022-01-05 11:35 UTC (permalink / raw)
To: Binutils
For some reason the original AVFX512F insns were not taken as a basis
here, causing unnecessary divergence. While not an active issue, it is
still relevant to note that OP_XMM() has special treatment of e.g.
scalar_mode (marking broadcast as invalid). Such would better be
consistent for all sufficiently similar insns.
--- a/opcodes/i386-dis-evex.h
+++ b/opcodes/i386-dis-evex.h
@@ -1216,7 +1216,7 @@ static const struct dis386 evex_table[][
{ Bad_Opcode },
{ Bad_Opcode },
{ "vscalefp%XH", { XM, Vex, EXxh, EXxEVexR }, PREFIX_DATA },
- { "vscalefs%XH", { XMM, VexScalar, EXw, EXxEVexR }, PREFIX_DATA },
+ { "vscalefs%XH", { XMScalar, VexScalar, EXw, EXxEVexR }, PREFIX_DATA },
{ Bad_Opcode },
{ Bad_Opcode },
/* 30 */
@@ -1241,7 +1241,7 @@ static const struct dis386 evex_table[][
{ Bad_Opcode },
{ Bad_Opcode },
{ "vgetexpp%XH", { XM, EXxh, EXxEVexS }, PREFIX_DATA },
- { "vgetexps%XH", { XMM, VexScalar, EXw, EXxEVexS }, PREFIX_DATA },
+ { "vgetexps%XH", { XMScalar, VexScalar, EXw, EXxEVexS }, PREFIX_DATA },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
@@ -1252,9 +1252,9 @@ static const struct dis386 evex_table[][
{ Bad_Opcode },
{ Bad_Opcode },
{ "vrcpp%XH", { XM, EXxh }, PREFIX_DATA },
- { "vrcps%XH", { XMM, VexScalar, EXw }, PREFIX_DATA },
+ { "vrcps%XH", { XMScalar, VexScalar, EXw }, PREFIX_DATA },
{ "vrsqrtp%XH", { XM, EXxh }, PREFIX_DATA },
- { "vrsqrts%XH", { XMM, VexScalar, EXw }, PREFIX_DATA },
+ { "vrsqrts%XH", { XMScalar, VexScalar, EXw }, PREFIX_DATA },
/* 50 */
{ Bad_Opcode },
{ Bad_Opcode },
@@ -1338,13 +1338,13 @@ static const struct dis386 evex_table[][
{ "vfmsubadd132p%XH", { XM, Vex, EXxh, EXxEVexR }, PREFIX_DATA },
/* 98 */
{ "vfmadd132p%XH", { XM, Vex, EXxh, EXxEVexR }, PREFIX_DATA },
- { "vfmadd132s%XH", { XMM, VexScalar, EXw, EXxEVexR }, PREFIX_DATA },
+ { "vfmadd132s%XH", { XMScalar, VexScalar, EXw, EXxEVexR }, PREFIX_DATA },
{ "vfmsub132p%XH", { XM, Vex, EXxh, EXxEVexR }, PREFIX_DATA },
- { "vfmsub132s%XH", { XMM, VexScalar, EXw, EXxEVexR }, PREFIX_DATA },
+ { "vfmsub132s%XH", { XMScalar, VexScalar, EXw, EXxEVexR }, PREFIX_DATA },
{ "vfnmadd132p%XH", { XM, Vex, EXxh, EXxEVexR }, PREFIX_DATA },
- { "vfnmadd132s%XH", { XMM, VexScalar, EXw, EXxEVexR }, PREFIX_DATA },
+ { "vfnmadd132s%XH", { XMScalar, VexScalar, EXw, EXxEVexR }, PREFIX_DATA },
{ "vfnmsub132p%XH", { XM, Vex, EXxh, EXxEVexR }, PREFIX_DATA },
- { "vfnmsub132s%XH", { XMM, VexScalar, EXw, EXxEVexR }, PREFIX_DATA },
+ { "vfnmsub132s%XH", { XMScalar, VexScalar, EXw, EXxEVexR }, PREFIX_DATA },
/* A0 */
{ Bad_Opcode },
{ Bad_Opcode },
@@ -1356,13 +1356,13 @@ static const struct dis386 evex_table[][
{ "vfmsubadd213p%XH", { XM, Vex, EXxh, EXxEVexR }, PREFIX_DATA },
/* A8 */
{ "vfmadd213p%XH", { XM, Vex, EXxh, EXxEVexR }, PREFIX_DATA },
- { "vfmadd213s%XH", { XMM, VexScalar, EXw, EXxEVexR }, PREFIX_DATA },
+ { "vfmadd213s%XH", { XMScalar, VexScalar, EXw, EXxEVexR }, PREFIX_DATA },
{ "vfmsub213p%XH", { XM, Vex, EXxh, EXxEVexR }, PREFIX_DATA },
- { "vfmsub213s%XH", { XMM, VexScalar, EXw, EXxEVexR }, PREFIX_DATA },
+ { "vfmsub213s%XH", { XMScalar, VexScalar, EXw, EXxEVexR }, PREFIX_DATA },
{ "vfnmadd213p%XH", { XM, Vex, EXxh, EXxEVexR }, PREFIX_DATA },
- { "vfnmadd213s%XH", { XMM, VexScalar, EXw, EXxEVexR }, PREFIX_DATA },
+ { "vfnmadd213s%XH", { XMScalar, VexScalar, EXw, EXxEVexR }, PREFIX_DATA },
{ "vfnmsub213p%XH", { XM, Vex, EXxh, EXxEVexR }, PREFIX_DATA },
- { "vfnmsub213s%XH", { XMM, VexScalar, EXw, EXxEVexR }, PREFIX_DATA },
+ { "vfnmsub213s%XH", { XMScalar, VexScalar, EXw, EXxEVexR }, PREFIX_DATA },
/* B0 */
{ Bad_Opcode },
{ Bad_Opcode },
@@ -1374,13 +1374,13 @@ static const struct dis386 evex_table[][
{ "vfmsubadd231p%XH", { XM, Vex, EXxh, EXxEVexR }, PREFIX_DATA },
/* B8 */
{ "vfmadd231p%XH", { XM, Vex, EXxh, EXxEVexR }, PREFIX_DATA },
- { "vfmadd231s%XH", { XMM, VexScalar, EXw, EXxEVexR }, PREFIX_DATA },
+ { "vfmadd231s%XH", { XMScalar, VexScalar, EXw, EXxEVexR }, PREFIX_DATA },
{ "vfmsub231p%XH", { XM, Vex, EXxh, EXxEVexR }, PREFIX_DATA },
- { "vfmsub231s%XH", { XMM, VexScalar, EXw, EXxEVexR }, PREFIX_DATA },
+ { "vfmsub231s%XH", { XMScalar, VexScalar, EXw, EXxEVexR }, PREFIX_DATA },
{ "vfnmadd231p%XH", { XM, Vex, EXxh, EXxEVexR }, PREFIX_DATA },
- { "vfnmadd231s%XH", { XMM, VexScalar, EXw, EXxEVexR }, PREFIX_DATA },
+ { "vfnmadd231s%XH", { XMScalar, VexScalar, EXw, EXxEVexR }, PREFIX_DATA },
{ "vfnmsub231p%XH", { XM, Vex, EXxh, EXxEVexR }, PREFIX_DATA },
- { "vfnmsub231s%XH", { XMM, VexScalar, EXw, EXxEVexR }, PREFIX_DATA },
+ { "vfnmsub231s%XH", { XMScalar, VexScalar, EXw, EXxEVexR }, PREFIX_DATA },
/* C0 */
{ Bad_Opcode },
{ Bad_Opcode },
--- a/opcodes/i386-dis-evex-prefix.h
+++ b/opcodes/i386-dis-evex-prefix.h
@@ -440,7 +440,7 @@
},
/* PREFIX_EVEX_MAP5_1D */
{
- { "vcvtss2s%XH", { XMM, VexScalar, EXd, EXxEVexR }, 0 },
+ { "vcvtss2s%XH", { XMScalar, VexScalar, EXd, EXxEVexR }, 0 },
{ Bad_Opcode },
{ "vcvtps2p%XHx%XY", { XMxmmq, EXx, EXxEVexR }, 0 },
},
@@ -470,24 +470,24 @@
/* PREFIX_EVEX_MAP5_51 */
{
{ "vsqrtp%XH", { XM, EXxh, EXxEVexR }, 0 },
- { "vsqrts%XH", { XMM, VexScalar, EXw, EXxEVexR }, 0 },
+ { "vsqrts%XH", { XMScalar, VexScalar, EXw, EXxEVexR }, 0 },
},
/* PREFIX_EVEX_MAP5_58 */
{
{ "vaddp%XH", { XM, Vex, EXxh, EXxEVexR }, 0 },
- { "vadds%XH", { XMM, VexScalar, EXw, EXxEVexR }, 0 },
+ { "vadds%XH", { XMScalar, VexScalar, EXw, EXxEVexR }, 0 },
},
/* PREFIX_EVEX_MAP5_59 */
{
{ "vmulp%XH", { XM, Vex, EXxh, EXxEVexR }, 0 },
- { "vmuls%XH", { XMM, VexScalar, EXw, EXxEVexR }, 0 },
+ { "vmuls%XH", { XMScalar, VexScalar, EXw, EXxEVexR }, 0 },
},
/* PREFIX_EVEX_MAP5_5A */
{
{ "vcvtp%XH2pd", { XM, EXxmmqdh, EXxEVexS }, 0 },
- { "vcvts%XH2sd", { XMM, VexScalar, EXw, EXxEVexS }, 0 },
+ { "vcvts%XH2sd", { XMScalar, VexScalar, EXw, EXxEVexS }, 0 },
{ "vcvtp%XD2ph%XZ", { XMM, EXx, EXxEVexR }, 0 },
- { "vcvts%XD2sh", { XMM, VexScalar, EXq, EXxEVexR }, 0 },
+ { "vcvts%XD2sh", { XMScalar, VexScalar, EXq, EXxEVexR }, 0 },
},
/* PREFIX_EVEX_MAP5_5B */
{
@@ -498,22 +498,22 @@
/* PREFIX_EVEX_MAP5_5C */
{
{ "vsubp%XH", { XM, Vex, EXxh, EXxEVexR }, 0 },
- { "vsubs%XH", { XMM, VexScalar, EXw, EXxEVexR }, 0 },
+ { "vsubs%XH", { XMScalar, VexScalar, EXw, EXxEVexR }, 0 },
},
/* PREFIX_EVEX_MAP5_5D */
{
{ "vminp%XH", { XM, Vex, EXxh, EXxEVexS }, 0 },
- { "vmins%XH", { XMM, VexScalar, EXw, EXxEVexS }, 0 },
+ { "vmins%XH", { XMScalar, VexScalar, EXw, EXxEVexS }, 0 },
},
/* PREFIX_EVEX_MAP5_5E */
{
{ "vdivp%XH", { XM, Vex, EXxh, EXxEVexR }, 0 },
- { "vdivs%XH", { XMM, VexScalar, EXw, EXxEVexR }, 0 },
+ { "vdivs%XH", { XMScalar, VexScalar, EXw, EXxEVexR }, 0 },
},
/* PREFIX_EVEX_MAP5_5F */
{
{ "vmaxp%XH", { XM, Vex, EXxh, EXxEVexS }, 0 },
- { "vmaxs%XH", { XMM, VexScalar, EXw, EXxEVexS }, 0 },
+ { "vmaxs%XH", { XMScalar, VexScalar, EXw, EXxEVexS }, 0 },
},
/* PREFIX_EVEX_MAP5_78 */
{
@@ -555,7 +555,7 @@
},
/* PREFIX_EVEX_MAP6_13 */
{
- { "vcvts%XH2ss", { XMM, VexScalar, EXw, EXxEVexS }, 0 },
+ { "vcvts%XH2ss", { XMScalar, VexScalar, EXw, EXxEVexS }, 0 },
{ Bad_Opcode },
{ "vcvtp%XH2psx", { XM, EXxmmqh, EXxEVexS }, 0 },
},
@@ -569,9 +569,9 @@
/* PREFIX_EVEX_MAP6_57 */
{
{ Bad_Opcode },
- { "vfmaddcs%XH", { { DistinctDest_Fixup, xmm_mode }, VexScalar, EXd, EXxEVexR }, 0 },
+ { "vfmaddcs%XH", { { DistinctDest_Fixup, scalar_mode }, VexScalar, EXd, EXxEVexR }, 0 },
{ Bad_Opcode },
- { "vfcmaddcs%XH", { { DistinctDest_Fixup, xmm_mode }, VexScalar, EXd, EXxEVexR }, 0 },
+ { "vfcmaddcs%XH", { { DistinctDest_Fixup, scalar_mode }, VexScalar, EXd, EXxEVexR }, 0 },
},
/* PREFIX_EVEX_MAP6_D6 */
{
@@ -583,7 +583,7 @@
/* PREFIX_EVEX_MAP6_D7 */
{
{ Bad_Opcode },
- { "vfmulcs%XH", { { DistinctDest_Fixup, xmm_mode }, VexScalar, EXd, EXxEVexR }, 0 },
+ { "vfmulcs%XH", { { DistinctDest_Fixup, scalar_mode }, VexScalar, EXd, EXxEVexR }, 0 },
{ Bad_Opcode },
- { "vfcmulcs%XH", { { DistinctDest_Fixup, xmm_mode }, VexScalar, EXd, EXxEVexR }, 0 },
+ { "vfcmulcs%XH", { { DistinctDest_Fixup, scalar_mode }, VexScalar, EXd, EXxEVexR }, 0 },
},
^ permalink raw reply [flat|nested] 8+ messages in thread* [PATCH 5/6] x86: share yet more VEX table entries with EVEX decoding
2022-01-05 11:31 [PATCH 0/6] x86: AVX512* / EVEX decoding adjustments Jan Beulich
` (3 preceding siblings ...)
2022-01-05 11:35 ` [PATCH 4/6] x86: consistently use scalar_mode for AVX512-FP16 scalar insns Jan Beulich
@ 2022-01-05 11:35 ` Jan Beulich
2022-01-05 11:36 ` [PATCH 6/6] x86: drop ymmxmm_mode Jan Beulich
2022-01-05 15:02 ` [PATCH 0/6] x86: AVX512* / EVEX decoding adjustments H.J. Lu
6 siblings, 0 replies; 8+ messages in thread
From: Jan Beulich @ 2022-01-05 11:35 UTC (permalink / raw)
To: Binutils
On top of prior similar work more opportunities have appeared in the
meantime. Note that this also happens to address the prior lack of
decoding of EVEX.L'L for VMOV{L,H}P{S,D} and VMOV{LH,HL}PS.
--- a/opcodes/i386-dis.c
+++ b/opcodes/i386-dis.c
@@ -838,13 +838,6 @@ enum
MOD_XOP_09_12,
- MOD_EVEX_0F12_PREFIX_0,
- MOD_EVEX_0F12_PREFIX_2,
- MOD_EVEX_0F13,
- MOD_EVEX_0F16_PREFIX_0,
- MOD_EVEX_0F16_PREFIX_2,
- MOD_EVEX_0F17,
- MOD_EVEX_0F2B,
MOD_EVEX_0F381A,
MOD_EVEX_0F381B,
MOD_EVEX_0F3828_P_1,
@@ -1036,20 +1029,7 @@ enum
PREFIX_VEX_0F38F7_L_0,
PREFIX_VEX_0F3AF0_L_0,
- PREFIX_EVEX_0F10,
- PREFIX_EVEX_0F11,
- PREFIX_EVEX_0F12,
- PREFIX_EVEX_0F16,
- PREFIX_EVEX_0F2A,
- PREFIX_EVEX_0F51,
- PREFIX_EVEX_0F58,
- PREFIX_EVEX_0F59,
- PREFIX_EVEX_0F5A,
PREFIX_EVEX_0F5B,
- PREFIX_EVEX_0F5C,
- PREFIX_EVEX_0F5D,
- PREFIX_EVEX_0F5E,
- PREFIX_EVEX_0F5F,
PREFIX_EVEX_0F6F,
PREFIX_EVEX_0F70,
PREFIX_EVEX_0F78,
@@ -1666,9 +1646,9 @@ struct dis386 {
"XZ" => print 'x', 'y', or 'z' if suffix_always is true or no
register operands and no broadcast.
"XW" => print 's', 'd' depending on the VEX.W bit (for FMA)
- "XD" => print 'd' if EVEX.W=1, EVEX.W=0 is not a valid encoding
+ "XD" => print 'd' if !EVEX or EVEX.W=1, EVEX.W=0 is not a valid encoding
"XH" => print 'h' if EVEX.W=0, EVEX.W=1 is not a valid encoding (for FP16)
- "XS" => print 's' if EVEX.W=0, EVEX.W=1 is not a valid encoding
+ "XS" => print 's' if !EVEX or EVEX.W=0, EVEX.W=1 is not a valid encoding
"XV" => print "{vex3}" pseudo prefix
"LQ" => print 'l' ('d' in Intel mode) or 'q' for memory operand, cond
being false, or no operand at all in 64bit mode, or if suffix_always
@@ -3616,41 +3596,41 @@ static const struct dis386 prefix_table[
/* PREFIX_VEX_0F10 */
{
- { "vmovups", { XM, EXx }, 0 },
- { "vmovss", { XMScalar, VexScalarR, EXd }, 0 },
- { "vmovupd", { XM, EXx }, 0 },
- { "vmovsd", { XMScalar, VexScalarR, EXq }, 0 },
+ { "vmovupX", { XM, EXEvexXNoBcst }, PREFIX_OPCODE },
+ { "vmovs%XS", { XMScalar, VexScalarR, EXd }, 0 },
+ { "vmovupX", { XM, EXEvexXNoBcst }, PREFIX_OPCODE },
+ { "vmovs%XD", { XMScalar, VexScalarR, EXq }, 0 },
},
/* PREFIX_VEX_0F11 */
{
- { "vmovups", { EXxS, XM }, 0 },
- { "vmovss", { EXdS, VexScalarR, XMScalar }, 0 },
- { "vmovupd", { EXxS, XM }, 0 },
- { "vmovsd", { EXqS, VexScalarR, XMScalar }, 0 },
+ { "vmovupX", { EXxS, XM }, PREFIX_OPCODE },
+ { "vmovs%XS", { EXdS, VexScalarR, XMScalar }, 0 },
+ { "vmovupX", { EXxS, XM }, PREFIX_OPCODE },
+ { "vmovs%XD", { EXqS, VexScalarR, XMScalar }, 0 },
},
/* PREFIX_VEX_0F12 */
{
{ MOD_TABLE (MOD_VEX_0F12_PREFIX_0) },
- { "vmovsldup", { XM, EXx }, 0 },
+ { "vmov%XSldup", { XM, EXEvexXNoBcst }, 0 },
{ MOD_TABLE (MOD_VEX_0F12_PREFIX_2) },
- { "vmovddup", { XM, EXymmq }, 0 },
+ { "vmov%XDdup", { XM, EXymmq }, 0 },
},
/* PREFIX_VEX_0F16 */
{
{ MOD_TABLE (MOD_VEX_0F16_PREFIX_0) },
- { "vmovshdup", { XM, EXx }, 0 },
+ { "vmov%XShdup", { XM, EXEvexXNoBcst }, 0 },
{ MOD_TABLE (MOD_VEX_0F16_PREFIX_2) },
},
/* PREFIX_VEX_0F2A */
{
{ Bad_Opcode },
- { "vcvtsi2ss{%LQ|}", { XMScalar, VexScalar, Edq }, 0 },
+ { "vcvtsi2ss{%LQ|}", { XMScalar, VexScalar, EXxEVexR, Edq }, 0 },
{ Bad_Opcode },
- { "vcvtsi2sd{%LQ|}", { XMScalar, VexScalar, Edq }, 0 },
+ { "vcvtsi2sd{%LQ|}", { XMScalar, VexScalar, EXxEVexR64, Edq }, 0 },
},
/* PREFIX_VEX_0F2C */
@@ -3795,10 +3775,10 @@ static const struct dis386 prefix_table[
/* PREFIX_VEX_0F51 */
{
- { "vsqrtps", { XM, EXx }, 0 },
- { "vsqrtss", { XMScalar, VexScalar, EXd }, 0 },
- { "vsqrtpd", { XM, EXx }, 0 },
- { "vsqrtsd", { XMScalar, VexScalar, EXq }, 0 },
+ { "vsqrtpX", { XM, EXx, EXxEVexR }, PREFIX_OPCODE },
+ { "vsqrts%XS", { XMScalar, VexScalar, EXd, EXxEVexR }, 0 },
+ { "vsqrtpX", { XM, EXx, EXxEVexR }, PREFIX_OPCODE },
+ { "vsqrts%XD", { XMScalar, VexScalar, EXq, EXxEVexR }, 0 },
},
/* PREFIX_VEX_0F52 */
@@ -3815,26 +3795,26 @@ static const struct dis386 prefix_table[
/* PREFIX_VEX_0F58 */
{
- { "vaddps", { XM, Vex, EXx }, 0 },
- { "vaddss", { XMScalar, VexScalar, EXd }, 0 },
- { "vaddpd", { XM, Vex, EXx }, 0 },
- { "vaddsd", { XMScalar, VexScalar, EXq }, 0 },
+ { "vaddpX", { XM, Vex, EXx, EXxEVexR }, PREFIX_OPCODE },
+ { "vadds%XS", { XMScalar, VexScalar, EXd, EXxEVexR }, 0 },
+ { "vaddpX", { XM, Vex, EXx, EXxEVexR }, PREFIX_OPCODE },
+ { "vadds%XD", { XMScalar, VexScalar, EXq, EXxEVexR }, 0 },
},
/* PREFIX_VEX_0F59 */
{
- { "vmulps", { XM, Vex, EXx }, 0 },
- { "vmulss", { XMScalar, VexScalar, EXd }, 0 },
- { "vmulpd", { XM, Vex, EXx }, 0 },
- { "vmulsd", { XMScalar, VexScalar, EXq }, 0 },
+ { "vmulpX", { XM, Vex, EXx, EXxEVexR }, PREFIX_OPCODE },
+ { "vmuls%XS", { XMScalar, VexScalar, EXd, EXxEVexR }, 0 },
+ { "vmulpX", { XM, Vex, EXx, EXxEVexR }, PREFIX_OPCODE },
+ { "vmuls%XD", { XMScalar, VexScalar, EXq, EXxEVexR }, 0 },
},
/* PREFIX_VEX_0F5A */
{
- { "vcvtps2pd", { XM, EXxmmq }, 0 },
- { "vcvtss2sd", { XMScalar, VexScalar, EXd }, 0 },
- { "vcvtpd2ps%XY",{ XMM, EXx }, 0 },
- { "vcvtsd2ss", { XMScalar, VexScalar, EXq }, 0 },
+ { "vcvtp%XS2pd", { XM, EXEvexHalfBcstXmmq, EXxEVexS }, 0 },
+ { "vcvts%XS2sd", { XMScalar, VexScalar, EXd, EXxEVexS }, 0 },
+ { "vcvtp%XD2ps%XY", { XMxmmq, EXx, EXxEVexR }, 0 },
+ { "vcvts%XD2ss", { XMScalar, VexScalar, EXq, EXxEVexR }, 0 },
},
/* PREFIX_VEX_0F5B */
@@ -3846,34 +3826,34 @@ static const struct dis386 prefix_table[
/* PREFIX_VEX_0F5C */
{
- { "vsubps", { XM, Vex, EXx }, 0 },
- { "vsubss", { XMScalar, VexScalar, EXd }, 0 },
- { "vsubpd", { XM, Vex, EXx }, 0 },
- { "vsubsd", { XMScalar, VexScalar, EXq }, 0 },
+ { "vsubpX", { XM, Vex, EXx, EXxEVexR }, PREFIX_OPCODE },
+ { "vsubs%XS", { XMScalar, VexScalar, EXd, EXxEVexR }, 0 },
+ { "vsubpX", { XM, Vex, EXx, EXxEVexR }, PREFIX_OPCODE },
+ { "vsubs%XD", { XMScalar, VexScalar, EXq, EXxEVexR }, 0 },
},
/* PREFIX_VEX_0F5D */
{
- { "vminps", { XM, Vex, EXx }, 0 },
- { "vminss", { XMScalar, VexScalar, EXd }, 0 },
- { "vminpd", { XM, Vex, EXx }, 0 },
- { "vminsd", { XMScalar, VexScalar, EXq }, 0 },
+ { "vminpX", { XM, Vex, EXx, EXxEVexS }, PREFIX_OPCODE },
+ { "vmins%XS", { XMScalar, VexScalar, EXd, EXxEVexS }, 0 },
+ { "vminpX", { XM, Vex, EXx, EXxEVexS }, PREFIX_OPCODE },
+ { "vmins%XD", { XMScalar, VexScalar, EXq, EXxEVexS }, 0 },
},
/* PREFIX_VEX_0F5E */
{
- { "vdivps", { XM, Vex, EXx }, 0 },
- { "vdivss", { XMScalar, VexScalar, EXd }, 0 },
- { "vdivpd", { XM, Vex, EXx }, 0 },
- { "vdivsd", { XMScalar, VexScalar, EXq }, 0 },
+ { "vdivpX", { XM, Vex, EXx, EXxEVexR }, PREFIX_OPCODE },
+ { "vdivs%XS", { XMScalar, VexScalar, EXd, EXxEVexR }, 0 },
+ { "vdivpX", { XM, Vex, EXx, EXxEVexR }, PREFIX_OPCODE },
+ { "vdivs%XD", { XMScalar, VexScalar, EXq, EXxEVexR }, 0 },
},
/* PREFIX_VEX_0F5F */
{
- { "vmaxps", { XM, Vex, EXx }, 0 },
- { "vmaxss", { XMScalar, VexScalar, EXd }, 0 },
- { "vmaxpd", { XM, Vex, EXx }, 0 },
- { "vmaxsd", { XMScalar, VexScalar, EXq }, 0 },
+ { "vmaxpX", { XM, Vex, EXx, EXxEVexS }, PREFIX_OPCODE },
+ { "vmaxs%XS", { XMScalar, VexScalar, EXd, EXxEVexS }, 0 },
+ { "vmaxpX", { XM, Vex, EXx, EXxEVexS }, PREFIX_OPCODE },
+ { "vmaxs%XD", { XMScalar, VexScalar, EXq, EXxEVexS }, 0 },
},
/* PREFIX_VEX_0F6F */
@@ -6732,12 +6712,12 @@ static const struct dis386 vex_table[][2
static const struct dis386 vex_len_table[][2] = {
/* VEX_LEN_0F12_P_0_M_0 / VEX_LEN_0F12_P_2_M_0 */
{
- { "vmovlpX", { XM, Vex, EXq }, 0 },
+ { "vmovlpX", { XM, Vex, EXq }, PREFIX_OPCODE },
},
/* VEX_LEN_0F12_P_0_M_1 */
{
- { "vmovhlps", { XM, Vex, EXq }, 0 },
+ { "vmovhlp%XS", { XM, Vex, EXq }, 0 },
},
/* VEX_LEN_0F13_M_0 */
@@ -6747,12 +6727,12 @@ static const struct dis386 vex_len_table
/* VEX_LEN_0F16_P_0_M_0 / VEX_LEN_0F16_P_2_M_0 */
{
- { "vmovhpX", { XM, Vex, EXq }, 0 },
+ { "vmovhpX", { XM, Vex, EXq }, PREFIX_OPCODE },
},
/* VEX_LEN_0F16_P_0_M_1 */
{
- { "vmovlhps", { XM, Vex, EXq }, 0 },
+ { "vmovlhp%XS", { XM, Vex, EXq }, 0 },
},
/* VEX_LEN_0F17_M_0 */
@@ -10430,7 +10410,7 @@ putop (const char *in_template, int size
switch (last[0])
{
case 'X':
- if (vex.w)
+ if (!vex.evex || vex.w)
*obufp++ = 'd';
else
oappend ("{bad}");
@@ -10708,7 +10688,7 @@ putop (const char *in_template, int size
goto case_S;
case 'X':
- if (!vex.w)
+ if (!vex.evex || !vex.w)
*obufp++ = 's';
else
oappend ("{bad}");
--- a/opcodes/i386-dis-evex.h
+++ b/opcodes/i386-dis-evex.h
@@ -20,14 +20,14 @@ static const struct dis386 evex_table[][
{ Bad_Opcode },
{ Bad_Opcode },
/* 10 */
- { PREFIX_TABLE (PREFIX_EVEX_0F10) },
- { PREFIX_TABLE (PREFIX_EVEX_0F11) },
- { PREFIX_TABLE (PREFIX_EVEX_0F12) },
- { MOD_TABLE (MOD_EVEX_0F13) },
+ { PREFIX_TABLE (PREFIX_VEX_0F10) },
+ { PREFIX_TABLE (PREFIX_VEX_0F11) },
+ { PREFIX_TABLE (PREFIX_VEX_0F12) },
+ { MOD_TABLE (MOD_VEX_0F13) },
{ "vunpcklpX", { XM, Vex, EXx }, PREFIX_OPCODE },
{ "vunpckhpX", { XM, Vex, EXx }, PREFIX_OPCODE },
- { PREFIX_TABLE (PREFIX_EVEX_0F16) },
- { MOD_TABLE (MOD_EVEX_0F17) },
+ { PREFIX_TABLE (PREFIX_VEX_0F16) },
+ { MOD_TABLE (MOD_VEX_0F17) },
/* 18 */
{ Bad_Opcode },
{ Bad_Opcode },
@@ -49,8 +49,8 @@ static const struct dis386 evex_table[][
/* 28 */
{ "vmovapX", { XM, EXx }, PREFIX_OPCODE },
{ "vmovapX", { EXxS, XM }, PREFIX_OPCODE },
- { PREFIX_TABLE (PREFIX_EVEX_0F2A) },
- { MOD_TABLE (MOD_EVEX_0F2B) },
+ { PREFIX_TABLE (PREFIX_VEX_0F2A) },
+ { MOD_TABLE (MOD_VEX_0F2B) },
{ PREFIX_TABLE (PREFIX_VEX_0F2C) },
{ PREFIX_TABLE (PREFIX_VEX_0F2D) },
{ PREFIX_TABLE (PREFIX_VEX_0F2E) },
@@ -93,7 +93,7 @@ static const struct dis386 evex_table[][
{ Bad_Opcode },
/* 50 */
{ Bad_Opcode },
- { PREFIX_TABLE (PREFIX_EVEX_0F51) },
+ { PREFIX_TABLE (PREFIX_VEX_0F51) },
{ Bad_Opcode },
{ Bad_Opcode },
{ "vandpX", { XM, Vex, EXx }, PREFIX_OPCODE },
@@ -101,14 +101,14 @@ static const struct dis386 evex_table[][
{ "vorpX", { XM, Vex, EXx }, PREFIX_OPCODE },
{ "vxorpX", { XM, Vex, EXx }, PREFIX_OPCODE },
/* 58 */
- { PREFIX_TABLE (PREFIX_EVEX_0F58) },
- { PREFIX_TABLE (PREFIX_EVEX_0F59) },
- { PREFIX_TABLE (PREFIX_EVEX_0F5A) },
+ { PREFIX_TABLE (PREFIX_VEX_0F58) },
+ { PREFIX_TABLE (PREFIX_VEX_0F59) },
+ { PREFIX_TABLE (PREFIX_VEX_0F5A) },
{ PREFIX_TABLE (PREFIX_EVEX_0F5B) },
- { PREFIX_TABLE (PREFIX_EVEX_0F5C) },
- { PREFIX_TABLE (PREFIX_EVEX_0F5D) },
- { PREFIX_TABLE (PREFIX_EVEX_0F5E) },
- { PREFIX_TABLE (PREFIX_EVEX_0F5F) },
+ { PREFIX_TABLE (PREFIX_VEX_0F5C) },
+ { PREFIX_TABLE (PREFIX_VEX_0F5D) },
+ { PREFIX_TABLE (PREFIX_VEX_0F5E) },
+ { PREFIX_TABLE (PREFIX_VEX_0F5F) },
/* 60 */
{ "vpunpcklbw", { XM, Vex, EXx }, PREFIX_DATA },
{ "vpunpcklwd", { XM, Vex, EXx }, PREFIX_DATA },
--- a/opcodes/i386-dis-evex-mod.h
+++ b/opcodes/i386-dis-evex-mod.h
@@ -1,33 +1,3 @@
- {
- /* MOD_EVEX_0F12_PREFIX_0 */
- { "vmovlpX", { XMM, Vex, EXq }, PREFIX_OPCODE },
- { "vmovhlp%XS", { XMM, Vex, EXq }, 0 },
- },
- {
- /* MOD_EVEX_0F12_PREFIX_2 */
- { "vmovlpX", { XMM, Vex, EXq }, PREFIX_OPCODE },
- },
- {
- /* MOD_EVEX_0F13 */
- { "vmovlpX", { EXq, XMM }, PREFIX_OPCODE },
- },
- {
- /* MOD_EVEX_0F16_PREFIX_0 */
- { "vmovhpX", { XMM, Vex, EXq }, PREFIX_OPCODE },
- { "vmovlhp%XS", { XMM, Vex, EXq }, 0 },
- },
- {
- /* MOD_EVEX_0F16_PREFIX_2 */
- { "vmovhpX", { XMM, Vex, EXq }, PREFIX_OPCODE },
- },
- {
- /* MOD_EVEX_0F17 */
- { "vmovhpX", { EXq, XMM }, PREFIX_OPCODE },
- },
- {
- /* MOD_EVEX_0F2B */
- { "vmovntpX", { EXx, XM }, PREFIX_OPCODE },
- },
/* MOD_EVEX_0F381A */
{
{ EVEX_LEN_TABLE (EVEX_LEN_0F381A_M_0) },
--- a/opcodes/i386-dis-evex-prefix.h
+++ b/opcodes/i386-dis-evex-prefix.h
@@ -1,99 +1,9 @@
- /* PREFIX_EVEX_0F10 */
- {
- { "vmovupX", { XM, EXEvexXNoBcst }, PREFIX_OPCODE },
- { "vmovs%XS", { XMScalar, VexScalarR, EXd }, 0 },
- { "vmovupX", { XM, EXEvexXNoBcst }, PREFIX_OPCODE },
- { "vmovs%XD", { XMScalar, VexScalarR, EXq }, 0 },
- },
- /* PREFIX_EVEX_0F11 */
- {
- { "vmovupX", { EXxS, XM }, PREFIX_OPCODE },
- { "vmovs%XS", { EXdS, VexScalarR, XMScalar }, 0 },
- { "vmovupX", { EXxS, XM }, PREFIX_OPCODE },
- { "vmovs%XD", { EXqS, VexScalarR, XMScalar }, 0 },
- },
- /* PREFIX_EVEX_0F12 */
- {
- { MOD_TABLE (MOD_EVEX_0F12_PREFIX_0) },
- { "vmov%XSldup", { XM, EXEvexXNoBcst }, 0 },
- { MOD_TABLE (MOD_EVEX_0F12_PREFIX_2) },
- { "vmov%XDdup", { XM, EXymmq }, 0 },
- },
- /* PREFIX_EVEX_0F16 */
- {
- { MOD_TABLE (MOD_EVEX_0F16_PREFIX_0) },
- { "vmov%XShdup", { XM, EXEvexXNoBcst }, 0 },
- { MOD_TABLE (MOD_EVEX_0F16_PREFIX_2) },
- },
- /* PREFIX_EVEX_0F2A */
- {
- { Bad_Opcode },
- { "vcvtsi2ss{%LQ|}", { XMScalar, VexScalar, EXxEVexR, Edq }, 0 },
- { Bad_Opcode },
- { "vcvtsi2sd{%LQ|}", { XMScalar, VexScalar, EXxEVexR64, Edq }, 0 },
- },
- /* PREFIX_EVEX_0F51 */
- {
- { "vsqrtpX", { XM, EXx, EXxEVexR }, PREFIX_OPCODE },
- { "vsqrts%XS", { XMScalar, VexScalar, EXd, EXxEVexR }, 0 },
- { "vsqrtpX", { XM, EXx, EXxEVexR }, PREFIX_OPCODE },
- { "vsqrts%XD", { XMScalar, VexScalar, EXq, EXxEVexR }, 0 },
- },
- /* PREFIX_EVEX_0F58 */
- {
- { "vaddpX", { XM, Vex, EXx, EXxEVexR }, PREFIX_OPCODE },
- { "vadds%XS", { XMScalar, VexScalar, EXd, EXxEVexR }, 0 },
- { "vaddpX", { XM, Vex, EXx, EXxEVexR }, PREFIX_OPCODE },
- { "vadds%XD", { XMScalar, VexScalar, EXq, EXxEVexR }, 0 },
- },
- /* PREFIX_EVEX_0F59 */
- {
- { "vmulpX", { XM, Vex, EXx, EXxEVexR }, PREFIX_OPCODE },
- { "vmuls%XS", { XMScalar, VexScalar, EXd, EXxEVexR }, 0 },
- { "vmulpX", { XM, Vex, EXx, EXxEVexR }, PREFIX_OPCODE },
- { "vmuls%XD", { XMScalar, VexScalar, EXq, EXxEVexR }, 0 },
- },
- /* PREFIX_EVEX_0F5A */
- {
- { "vcvtp%XS2pd", { XM, EXEvexHalfBcstXmmq, EXxEVexS }, 0 },
- { "vcvts%XS2sd", { XMScalar, VexScalar, EXd, EXxEVexS }, 0 },
- { "vcvtp%XD2ps%XY", { XMxmmq, EXx, EXxEVexR }, 0 },
- { "vcvts%XD2ss", { XMScalar, VexScalar, EXq, EXxEVexR }, 0 },
- },
/* PREFIX_EVEX_0F5B */
{
{ VEX_W_TABLE (EVEX_W_0F5B_P_0) },
{ "vcvttp%XS2dq", { XM, EXx, EXxEVexS }, 0 },
{ "vcvtp%XS2dq", { XM, EXx, EXxEVexR }, 0 },
},
- /* PREFIX_EVEX_0F5C */
- {
- { "vsubpX", { XM, Vex, EXx, EXxEVexR }, PREFIX_OPCODE },
- { "vsubs%XS", { XMScalar, VexScalar, EXd, EXxEVexR }, 0 },
- { "vsubpX", { XM, Vex, EXx, EXxEVexR }, PREFIX_OPCODE },
- { "vsubs%XD", { XMScalar, VexScalar, EXq, EXxEVexR }, 0 },
- },
- /* PREFIX_EVEX_0F5D */
- {
- { "vminpX", { XM, Vex, EXx, EXxEVexS }, PREFIX_OPCODE },
- { "vmins%XS", { XMScalar, VexScalar, EXd, EXxEVexS }, 0 },
- { "vminpX", { XM, Vex, EXx, EXxEVexS }, PREFIX_OPCODE },
- { "vmins%XD", { XMScalar, VexScalar, EXq, EXxEVexS }, 0 },
- },
- /* PREFIX_EVEX_0F5E */
- {
- { "vdivpX", { XM, Vex, EXx, EXxEVexR }, PREFIX_OPCODE },
- { "vdivs%XS", { XMScalar, VexScalar, EXd, EXxEVexR }, 0 },
- { "vdivpX", { XM, Vex, EXx, EXxEVexR }, PREFIX_OPCODE },
- { "vdivs%XD", { XMScalar, VexScalar, EXq, EXxEVexR }, 0 },
- },
- /* PREFIX_EVEX_0F5F */
- {
- { "vmaxpX", { XM, Vex, EXx, EXxEVexS }, PREFIX_OPCODE },
- { "vmaxs%XS", { XMScalar, VexScalar, EXd, EXxEVexS }, 0 },
- { "vmaxpX", { XM, Vex, EXx, EXxEVexS }, PREFIX_OPCODE },
- { "vmaxs%XD", { XMScalar, VexScalar, EXq, EXxEVexS }, 0 },
- },
/* PREFIX_EVEX_0F6F */
{
{ Bad_Opcode },
^ permalink raw reply [flat|nested] 8+ messages in thread* [PATCH 6/6] x86: drop ymmxmm_mode
2022-01-05 11:31 [PATCH 0/6] x86: AVX512* / EVEX decoding adjustments Jan Beulich
` (4 preceding siblings ...)
2022-01-05 11:35 ` [PATCH 5/6] x86: share yet more VEX table entries with EVEX decoding Jan Beulich
@ 2022-01-05 11:36 ` Jan Beulich
2022-01-05 15:02 ` [PATCH 0/6] x86: AVX512* / EVEX decoding adjustments H.J. Lu
6 siblings, 0 replies; 8+ messages in thread
From: Jan Beulich @ 2022-01-05 11:36 UTC (permalink / raw)
To: Binutils
This enumerator is not used by any table entry.
--- a/opcodes/i386-dis.c
+++ b/opcodes/i386-dis.c
@@ -511,8 +511,6 @@ enum
ymm_mode,
/* quad word, ymmword or zmmword memory operand. */
ymmq_mode,
- /* 32-byte YMM or 16-byte word operand */
- ymmxmm_mode,
/* TMM operand */
tmm_mode,
/* d_mode in 32bit, q_mode in 64bit mode. */
@@ -11224,20 +11222,6 @@ intel_operand_size (int bytemode, int si
break;
default:
abort ();
- }
- break;
- case ymmxmm_mode:
- if (!need_vex)
- abort ();
-
- switch (vex.length)
- {
- case 128:
- case 256:
- oappend ("XMMWORD PTR ");
- break;
- default:
- abort ();
}
break;
case o_mode:
^ permalink raw reply [flat|nested] 8+ messages in thread* Re: [PATCH 0/6] x86: AVX512* / EVEX decoding adjustments
2022-01-05 11:31 [PATCH 0/6] x86: AVX512* / EVEX decoding adjustments Jan Beulich
` (5 preceding siblings ...)
2022-01-05 11:36 ` [PATCH 6/6] x86: drop ymmxmm_mode Jan Beulich
@ 2022-01-05 15:02 ` H.J. Lu
6 siblings, 0 replies; 8+ messages in thread
From: H.J. Lu @ 2022-01-05 15:02 UTC (permalink / raw)
To: Jan Beulich; +Cc: Binutils
On Wed, Jan 05, 2022 at 12:31:34PM +0100, Jan Beulich wrote:
> This carries out a few things which were mentioned previously, plus
> a few more adjustments noticed as desirable along the way.
>
> 1: reduce AVX512-FP16 set of insns decoded through vex_w_table[]
> 2: reduce AVX512 FP set of insns decoded through vex_w_table[]
> 3: record further wrong uses of EVEX.b
> 4: consistently use scalar_mode for AVX512-FP16 scalar insns
> 5: share yet more VEX table entries with EVEX decoding
> 6: drop ymmxmm_mode
>
> Jan
>
OK for all.
Thanks.
H.J.
^ permalink raw reply [flat|nested] 8+ messages in thread